JP2953061B2 - High breakdown voltage MOS transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high voltage MOS transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art A high voltage MOS transistor shown in FIG. 7 is known. In the figure, 1 is a p-type semiconductor substrate, 2 is an n-type well, 3 is a p − -type electric field relaxation region, 4 is a p + -type drain region, and is surrounded by the electric field relaxation region 3. . Reference numeral 5 denotes a p + -type source region. A channel is formed between the source region 5 and the electric field relaxation region 3, and a gate electrode 7 made of polycrystalline silicon is formed on the channel via a gate insulating film 6. .

[0003] Reference numeral 8 denotes a field insulating film formed by selective oxidation of the surface portion of the semiconductor substrate. The electric field relaxation region 3 is located below the field insulating film 8.

As described above, conventionally, in many cases, the drain withstand voltage is merely increased by surrounding the high-concentration drain region 4 with the low-concentration electric field relaxation region 3. In such a case, the drain breakdown voltage is generally determined by the product of the impurity concentration of the high concentration drain region 4 and the well 2 in which the high concentration drain region 4 is formed.
-It becomes the breakdown voltage of the pn junction between the high-concentration drain regions 4.

[0005]

By the way, with the high integration of ICs, high breakdown voltage MOS transistors are also required to be miniaturized. Therefore, it is required to increase the impurity concentration of the source region and the drain region. I mean,
In order to reduce the cell size, the size of the source region and the drain region must be reduced.However, as long as the impurity concentration is not increased, their parasitic resistance must be increased, which is not preferable in terms of transistor characteristics. It is. However, when the impurity concentration of the source region and the drain region is increased, the breakdown voltage of the junction between the p + -type drain region 4 and the well 2 is reduced as described above, and the drain breakdown voltage is reduced. This is a problem that cannot be ignored as a high breakdown voltage MOS transistor.

The present invention has been made to solve such a problem, and an object of the present invention is to increase the drain breakdown voltage without increasing the resistance of the source region and the drain.

[0007]

A high withstand voltage MOS according to claim 1
The transistor forms only a low-concentration electric field relaxation region as a drain-side region on the surface of the semiconductor substrate, and
A low concentration drain region in contact with the electric field relaxation region and a high concentration drain region connected thereto are formed on a semiconductor substrate by a semiconductor layer.
According to a second aspect of the present invention, there is provided a high voltage MOS transistor and a method of manufacturing the same, wherein a step of forming an electric field relaxation region by selective ion implantation of an impurity, a step of forming a field insulating film by selective oxidation, a step of forming a gate electrode, a low concentration drain region and Growing a semiconductor layer to be a high-concentration drain region.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The high breakdown voltage MOS transistor according to the present invention and a method for manufacturing the same will be described in detail with reference to the drawings. FIG.
FIG. 2 is a cross-sectional view showing one embodiment of the high breakdown voltage MOS transistor of the present invention. Reference numeral 1 denotes a p-type semiconductor substrate, and reference numeral 2 denotes a well formed on the surface of the semiconductor substrate 1, which corresponds to the surface of the semiconductor substrate in the claims. Numeral 3 is a p @-type electric field relaxation region, and a half on the source region side is located below the field insulating film 8, and the other half 3a is a field insulating film 8
It is exposed on the semiconductor surface where it deviates. 5 is p
The + source region is appropriately separated from the electric field relaxation region 3, and the channel between the source region 5 and the electric field relaxation region 3 is a channel. A gate electrode 7 made of polycrystalline silicon is formed on the channel via a gate insulating film 6.

Reference numeral 9 denotes a silicon semiconductor layer formed by a vapor growth method. 9a is a portion 3a of the semiconductor layer 9 exposed on the semiconductor surface of the electric field relaxation region 3 and an opening 8
The low-concentration drain region 3a is a low-concentration drain region contacted by a, and the crystallinity of the low-concentration drain region 3a grows as it is to form an epitaxial layer. Reference numeral 9b denotes a portion of the semiconductor layer 9 located on the field insulating film 8, and the crystallinity of the low-concentration drain region 3a does not reach this level and is in a polycrystalline silicon state.

In this high-breakdown-voltage MOS transistor, the high-concentration drain region 9b and the low-concentration drain region 9a are not in direct contact with the well 2, which is the surface portion of the semiconductor substrate 1, and the drain breakdown voltage is equal to the electric field relaxation region 3 and the well 2 Field relaxation region 3. well 2 determined by the product of impurity concentration
This is the junction breakdown voltage. The impurity concentration of the electric field relaxation region 3 is much lower than that of the conventional high concentration drain region 4 (see FIG. 7). Therefore, the drain withstand voltage is considerably higher than in the past.

As described above, according to the high breakdown voltage MOS transistor of FIG. 1, the drain breakdown voltage can be extremely increased. By sufficiently increasing the impurity concentration of the high-concentration drain region 9b, the resistance parasitic to the drain can be reduced as before or lower than before.

FIGS. 2 to 6 show the high breakdown voltage MO shown in FIG.
It is sectional drawing which shows the manufacturing method of S transistor in order of a process. The high voltage MOS transistor forms a part of the CMOS IC. (1) A pad film 10 made of SiO2 is formed on the well 2, and an oxidation resistant film 11 made of Si3 N4 is selectively formed on the pad film 10. FIG. 2 shows a state after the oxidation resistant film 11 is formed. (2) Next, the impurity is ion-implanted while selectively covering the surface of the semiconductor substrate with the resist film 12, thereby forming the p − -type electric field relaxation region 3 as shown in FIG. This electric field relaxation region 3 is an n-channel MOSFE (not shown).
This is performed simultaneously with the formation of the p-type channel stopper that prevents the generation of the n-type parasitic channel of T. Therefore, the formation of the electric field relaxation region 3 does not increase the number of manufacturing steps of the CMOS IC. (3) Next, the field insulating film 8 is formed by selective thermal oxidation of the semiconductor. FIG. 4 shows a state where the oxidation resistant film is removed after the field insulating film 8 is formed.

(4) Next, the thin insulating film on the surface is removed to expose the portion serving as the source region and the surface of the electric field relaxation region 3a, and then the gate insulating film 6 is formed. 6 is removed to expose the electric field relaxing region 3a, and then the gate electrode 7, the low concentration drain region 9a, and the high concentration drain region 9b are exposed.
Is grown by CVD. The gate electrode 7 is formed by patterning the semiconductor layer.
And the low-concentration drain region 9a and the high-concentration drain region 9b
And a semiconductor layer 9 to be formed. FIG. 5 shows a state after the formation of the gate electrode 7 and the semiconductor layer 9. Note that 9a and 9b in FIG. 5 merely distinguish the semiconductor layer 9 conceptually, and cannot distinguish them at this stage. The gate electrode 7 and the high-concentration drain region 9b are made of polycrystalline silicon because the underlayer is made of SiO2.
Since a) is used, it becomes an epitaxially grown layer and sufficiently plays a role as a drain. The feature of the present high-breakdown-voltage MOS transistor is that it has a low-concentration drain region 9a and a high-concentration drain region 9b made of a semiconductor layer.
The low-concentration drain region 9a and the high-concentration drain region 9
Since the semiconductor layer 9 to be b can be formed simultaneously with the gate electrode 7, the formation thereof does not cause an increase in the number of manufacturing steps of the high breakdown voltage MOS transistor. (5) Next, the low concentration drain region 9a is formed by the resist film 12.
By ion-implanting p-type impurities while masking, the p + -type source region 5 is formed as shown in FIG. 5 and the impurity concentration of the high-concentration drain region 9b is increased. Since this resist film 12 can be formed simultaneously with the resist film covering the formation portion of the n-channel MOS transistor, this formation does not involve an increase in the number of manufacturing steps of the high breakdown voltage MOS transistor.

According to such a method of manufacturing a high-voltage MOS transistor, the low-concentration drain region 9a and the high-concentration drain region 9b can be formed simultaneously with the gate electrode 7, and the high-voltage MOS transistor can be formed with almost no increase in the number of manufacturing steps. Can have a high breakdown voltage.

[0015]

According to the high voltage MOS transistor of the first aspect, a high concentration source region and an electric field relaxation region of the same conductivity type are provided on the surface of the semiconductor substrate as appropriate, and the source region and the high concentration source region are separated from each other. A gate electrode is formed on a portion between the electric field relaxing region and the gate insulating film via a gate insulating film, and extends on the field insulating film on the semiconductor substrate in contact with a portion of the electric field relaxing region on the side opposite to the source region. The semiconductor device is characterized in that the contacted portion has an epitaxial low-concentration drain region and the portion on the field insulating film has a high-concentration drain region.
Therefore, according to the present high-voltage MOS transistor, only the low-concentration electric field relaxation region as the drain-side region contacts the surface of the semiconductor substrate to form a junction, and the high-concentration drain region does not form a junction. Therefore, the withstand voltage of the drain is determined by the product of the impurity concentration of the low-concentration electric field relaxation region and the semiconductor substrate, and can be lower than in the conventional case. According to a second aspect of the present invention, there is provided a method of manufacturing a high withstand voltage MOS transistor, wherein a step of forming an electric field relaxation region by selectively ion-implanting an impurity into a surface portion of a semiconductor substrate; Forming a field insulating film by oxidizing a semiconductor surface portion by masking a portion of the electric field relaxation region to be in contact with the semiconductor layer with an oxidation-resistant film; and forming a gate electrode on the semiconductor substrate;
Growing a semiconductor layer to be a low-concentration drain region and a high-concentration drain region; and ion-implanting impurities using the gate electrode and a resist film covering the low-concentration drain region as a mask. Forming a source region and increasing the impurity concentration of a portion of the semiconductor layer which becomes a high-concentration drain region. Therefore, this high voltage MOS
According to the method for manufacturing a transistor, since the low-concentration drain region and the high-concentration drain region are formed simultaneously with the gate electrode, the drain breakdown voltage of the high-breakdown-voltage MOS transistor can be increased without increasing the number of manufacturing steps.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a high breakdown voltage MOS transistor of the present invention and a method of manufacturing the same.

FIG. 2 is a sectional view showing a first step of a method for manufacturing the high withstand voltage MOS transistor shown in FIG. 1;

FIG. 3 is a sectional view showing a second step of the method for manufacturing the high withstand voltage MOS transistor shown in FIG. 1;

FIG. 4 is a sectional view showing a third step of the method for manufacturing the high withstand voltage MOS transistor shown in FIG. 1;

FIG. 5 is a sectional view showing a fourth step of the method for manufacturing the high withstand voltage MOS transistor shown in FIG. 1;

FIG. 6 is a sectional view showing a fifth step of the method for manufacturing the high withstand voltage MOS transistor shown in FIG. 1;

FIG. 7 is a sectional view of a conventional example.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 semiconductor substrate surface (well) 3 electric field relaxation region 5 source region 6 gate insulating film 7 gate electrode 8 field insulating film 9 semiconductor layer 9 a low-concentration drain region 9 b high-concentration drain region 11 oxidation-resistant film 12 resist film

Claims (2)

(57) [Claims] 1. A high-concentration source region and an electric field relaxation region of the same conductivity type as the high concentration source region are provided on a surface portion of a semiconductor substrate as appropriate, and a high concentration source region is formed on a portion between the source region and the electric field relaxation region. A gate electrode is formed on the semiconductor substrate via a gate insulating film, and extends over the field insulating film in contact with a portion of the electric field relaxation region on the side opposite to the source region, and the contacted portion forms an epitaxial low concentration drain region. Characterized in that a semiconductor layer having a high concentration drain region on a field insulating film is formed. A step of forming an electric field relaxation region by selectively ion-implanting an impurity into a surface portion of the semiconductor substrate; a step of forming a source region, a portion serving as a channel, and forming a semiconductor layer of the electric field relaxation region. Forming a field insulating film by oxidizing a semiconductor surface in a state where a portion to be contacted is masked with an oxidation-resistant film; and forming a gate electrode, a low-concentration drain region and a high-concentration drain region on the semiconductor substrate. Forming a source region on the surface of the semiconductor substrate by ion-implanting impurities using the resist film covering the gate electrode and the low-concentration drain region as a mask. 2. A high withstand voltage M according to claim 1, further comprising a step of increasing the impurity concentration in a portion to be a concentration drain region. Method for manufacturing OS transistor