KR100190003B1 - Semiconductor device for high voltage use - Google Patents
Semiconductor device for high voltage use Download PDFInfo
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- KR100190003B1 KR100190003B1 KR1019950066840A KR19950066840A KR100190003B1 KR 100190003 B1 KR100190003 B1 KR 100190003B1 KR 1019950066840 A KR1019950066840 A KR 1019950066840A KR 19950066840 A KR19950066840 A KR 19950066840A KR 100190003 B1 KR100190003 B1 KR 100190003B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
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- 238000002955 isolation Methods 0.000 claims description 3
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- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
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Abstract
본 발명은 고전압용 반도체 소자에 관한 것으로서, 더 상세하게는 레터럴(Lateral) PNP의 베이스 폭(Wb)을 증가시키지 않고 내압(BVceo) 및 전류 구동능력을 향상시키며, N웰(Well)의 확산(Diffusion) 시간없이 게이트 폴리, 에미터/컬렉터를 이용하여 레터럴 PNP 및 PMOS 반도체 소자의 전류구동능력 및 내압을 증가시킬 수 있도록 한 고전압용 반도체 소자에 관한 것이다. 이를 위한 본 발명은, LPNP 트랜지스터와 PMOS 트랜지스터 및 NPN 트랜지스터가 동시에 존재하는 반도체 소자에 있어서, 상기 LPNP 트랜지스터의 에미터/컬렉터 부분과 상기 NPN 트랜지스터의 베이스 부분 및 상기 PMOS 트랜지스터의 소오스/드레인 부분의 접합영역이 P 및 P-로 형성되어 있기 때문에 LPNP의 베이스 폭(Wb)을 증가시키지 않고 내압 및 전류 구동능력을 증진시킬 수 있는 이점을 제공한다.The present invention relates to a high voltage semiconductor device, and more particularly, to improve the breakdown voltage (BVceo) and the current driving capability without increasing the base width (Wb) of the lateral PNP, and the diffusion of the N well. (Diffusion) The present invention relates to a high voltage semiconductor device capable of increasing current driving capability and breakdown voltage of lateral PNP and PMOS semiconductor devices using a gate poly and an emitter / collector without time. In the semiconductor device in which the LPNP transistor, the PMOS transistor and the NPN transistor exist simultaneously, the present invention provides a junction between the emitter / collector portion of the LPNP transistor, the base portion of the NPN transistor, and the source / drain portion of the PMOS transistor. Since the regions are formed of P and P − , they provide the advantage of improving the breakdown voltage and current driving capability without increasing the base width Wb of the LPNP.
Description
제1a, b도는 일반적인 NPN 트랜지스터 및 PMOS 트랜지스터의 구조를 개략적으로 도시한 단면도.1A and 1B are cross-sectional views schematically showing structures of a general NPN transistor and a PMOS transistor.
제2도는 본 발명에 따른 고전압용 반도체 소자의 구조를 도시한 단면도.2 is a cross-sectional view showing the structure of a semiconductor device for high voltage according to the present invention.
제3도 내지 제7도는 본 발명에 따른 고전압용 반도체 소자의 제조공정을 설명하기 위한 공정 단면도.3 to 7 are process cross-sectional views for explaining a manufacturing process of a high voltage semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
110 : P 저부층(P Bottom) 115 : P 절연층(P Isolation)110: P Bottom 115: P Insulation
120 : N웰(NTUB) 130 : P-베이스120: N well (NTUB) 130: P - base
135 : P 베이스 140 : 게이트 폴리135: P base 140: gate pulley
150 : LOCOS 산화층150 LOCOS oxide layer
본 발명은 고전압용 반도체 소자에 관한 것으로서, 더 상세하게는 레터럴(Laterla) PNP의 베이스 폭(Wb)을 증가시키지 않고 내압(BVceo) 및 전류 구동능력을 향상시키며, N웰(Well)의 확산(Diffusion) 시간없이 게이트 폴리, 에미터/컬렉터를 이용하여 레터럴 PNP 및 PMOS 반도체 소자의 전류구동능력 및 내압을 증가시킬 수 있도록 한 고전압용 반도체 소자에 관한 것이다.The present invention relates to a semiconductor device for high voltage, and more particularly, to improve the breakdown voltage (BVceo) and the current driving capability without increasing the base width (Wb) of the lateral PNP, and the diffusion of the N well (Well). (Diffusion) The present invention relates to a high voltage semiconductor device capable of increasing current driving capability and breakdown voltage of lateral PNP and PMOS semiconductor devices using a gate poly and an emitter / collector without time.
일반적인 고전압용 반도체 소자에 있어서, 레터럴(Lateral) PNP(이하, "LPNP"라 약칭한다) 트랜지스터는 NPN 트랜지스터 보다 상대적으로 낮은 전류 구동능력을 가지고 있을 뿐만 아니라 파워용으로 사용되는 IC에서는 LPNP의 내압(BVceo)이 NPN 트랜지스터보다 크게 사용되는 경우가 있다. 예를 들면, 텔레비젼, 모니터의 수직 편향회로 설계시 사용되는 고전압 프로세스에서 NPN 트랜지스터는 50볼트 정도를 필요로 하지만, LPNP 트랜지스터는 70-80볼트 정도를 필요로 한다.In general high voltage semiconductor devices, the lateral PNP (hereinafter referred to as "LPNP") transistor has a relatively lower current driving capability than the NPN transistor, and the breakdown voltage of the LPNP in an IC used for power. (BVceo) is sometimes used larger than an NPN transistor. For example, in high-voltage processes used in the design of vertical deflection circuits for televisions and monitors, NPN transistors require around 50 volts, while LPNP transistors require around 70-80 volts.
또한, LPNP 트랜지스터는 베이스 폭(Wb)으로 내압을 결정하기 때문에 트랜지스터의 사이즈가 커지는 단점이 있다. 따라서, LPNP 트랜지스터에서 내압(BVceo)을 높이기 위해 N-에피턱셜(epitaxial) 비저항(LPNP 베이스 농도)을 크게 가져가야 한다. 그러나, 에피텍셜 비저항을 향상시키는 것은 LPNP 전류구동능력 문제 및 NPN 특성변화 때문에 에피텍셜 비저항을 크게 할 수 없게 되는 문제점이 있다.In addition, since the LPNP transistor determines the breakdown voltage by the base width Wb, the size of the transistor is increased. Therefore, in order to increase the breakdown voltage (BVceo) in the LPNP transistor, it is necessary to have a large N-epitaxial resistivity (LPNP base concentration). However, improving the epitaxial resistivity has a problem in that the epitaxial resistivity cannot be increased due to the LPNP current driving capability problem and the NPN characteristic change.
본 발명은 상기와 같은 문제점을 해결하기 위하여 창출된 것으로서, LPNP 내압을 향상시키기 위해 MOS 방법처럼 LPNP LDD(lightly doped drain)을 만들어 바이폴라 및 MOS를 동시에 사용할 수 있는 트랜지스터로 이루어진 고전압용 반도체 소자를 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, to provide a high voltage semiconductor device consisting of a transistor that can be used simultaneously bipolar and MOS by making LPNP LDD (lightly doped drain) like the MOS method to improve the LPNP withstand voltage Has its purpose.
본 발명의 다른 목적은 에피택셜 비저항의 변화없이 LPNP 에미터/컬렉터 하부 및 PMOS 소오스/드레인 하부에 에피택셜 농도를 증가시키는 N웰(NWell)을 사용하여 고내압/고전류 바이폴라 LPNP 트랜지스터 및 고내압 PMOS를 형성한 고전압용 반도체 소자를 제공하는데 있다.Another object of the present invention is a high breakdown voltage / high current bipolar LPNP transistor and a high breakdown voltage PMOS using NWell which increases the epitaxial concentration under the LPNP emitter / collector and the PMOS source / drain without changing the epitaxial resistivity. It is to provide a high-voltage semiconductor device formed with a.
본 발명의 또 다른 목적은 LPNP의 베이스 폭(Wb)을 증가시키지 않고 내압 및 전류 구동능력을 증진시킬 수 있는 고전압용 반도체 소자를 제공하는데 있다.Still another object of the present invention is to provide a high voltage semiconductor device capable of improving breakdown voltage and current driving capability without increasing the base width (Wb) of the LPNP.
본 발명의 또 다른 목적은 N웰의 확산(diffusion) 시간을 없이하고 종래의 게이트 폴리(gate polly), 에미터/컬렉터를 이용하여 LPNP, PMOS의 전류구동능력 및 내압을 향상시킨 고전압용 반도체 소자를 제공하는데 있다.It is still another object of the present invention to improve the current driving capability and the breakdown voltage of LPNP and PMOS without using a diffusion time of N well and using a conventional gate polly and emitter / collector. To provide.
상기 목적을 달성하기 위하여 본 발명에 따른 고전압용 반도체 소자는, LPNP 트랜지스터와 PMOS 트랜지스터 및 NPN 트랜지스터가 동시에 존재하는 반도체 소자에 있어서, 상기 LPNP 트랜지스터의 에미터/컬렉터 부분과 상기 NPN 트랜지스터의 베이스 부분 및 상기 PMOS 트랜지스터의 소오스/드레인 부분의 접합영역이 P 및 P-로 형성되어 있는 점에 그 특징이 있다.In order to achieve the above object, a high voltage semiconductor device according to the present invention is a semiconductor device in which an LPNP transistor, a PMOS transistor, and an NPN transistor exist simultaneously, wherein an emitter / collector portion of the LPNP transistor, a base portion of the NPN transistor, and The feature is that the junction regions of the source / drain portions of the PMOS transistor are formed of P and P − .
본 발명의 실시예에 있어서, 상기 LPNP 트랜지스터의 베이스 및 상기 NPN 트랜지스터의 컬렉터가 N웰 및 베이스를 셀프 얼라인(Self-Align)으로 형성되며, 소정의 스페이서를 조정하여 P-와 P의 오버랩(Overlap)을 통해 바람직하게 고내압화할 수 있다.In an embodiment of the present invention, the base of the LPNP transistor and the collector of the NPN transistor are N-well and the base are formed in self-alignment (Self-Align), and a predetermined spacer is adjusted to overlap P − and P ( Overlap) can be preferably high withstand pressure.
본 발명의 실시예에 있어서, 상기 LPNP 트랜지스터는 N웰과 P 및 P-를 사용하며, 상기 N웰의 공정순서가 아이솔레이션(Isolation) 공정 또는 베이스(Base) 공정에 앞서서 바람직하게 행하여질 수 있다.In an embodiment of the present invention, the LPNP transistor uses N wells and P and P − , and the process order of the N wells may be preferably performed before an isolation process or a base process.
이하, 첨부된 도면을 참조하면서 본 발명에 따른 고전압용 반도체 소자의 바람직한 일실시예를 상세하게 설명한다.Hereinafter, a preferred embodiment of a high voltage semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
본 발명에 따른 고전압용 반도체 소자는 NPN 트랜지스터와 LPNP 트랜지스터 및 PMOS 트랜지스터를 동시에 구비함으로써 전류구동능력 및 내압이 향상된 것이다.The semiconductor device for high voltage according to the present invention includes an NPN transistor, an LPNP transistor, and a PMOS transistor simultaneously, thereby improving current driving capability and breakdown voltage.
먼저, 본 발명에 이용되는 NPN 트랜지스터와 PMOS 트랜지스터의 일반적인 구조에 대해 설명한다. 제1a도는 NPN 트랜지스터의 단면구조를 도시한 것으로서, P형 기판(1)상에 N형 매몰층(Buried layer; 3), P 저부층(Bottom; 5), P 절연층(7), N형 에피택셜 성장층(15)이 형성되어 있고, 상기 N형 에피택셜 성장층(15)에 P형 베이스(11)와 N+형 주입 에미터(9) 및 N+형 주입 컬렉터(13)가 형성되어 있다.First, the general structure of the NPN transistor and PMOS transistor used in the present invention will be described. FIG. 1A shows a cross-sectional structure of an NPN transistor, in which an N-type buried layer 3, a P bottom 5, a P insulating layer 7, and an N-type are formed on a P-type substrate 1 An epitaxial growth layer 15 is formed, and a P type base 11, an N + type implantation emitter 9, and an N + type implant collector 13 are formed on the N type epitaxial growth layer 15. It is.
제1b도는 PMOS 트랜지스터의 단면구조를 도시한 것으로서, 기판(21)상에 소오스 영역(23), 드레인 영역(27), 및 LOCOS 산화막 영역(29)이 형성되어 있으며, 게이트 폴리영역(25)이 그 상부에 형성되어 있다.FIG. 1B illustrates a cross-sectional structure of the PMOS transistor, in which a source region 23, a drain region 27, and a LOCOS oxide region 29 are formed on the substrate 21, and the gate poly region 25 is formed. It is formed in the upper part.
상기와 같은 NPN 트랜지스터의 구조와 PMOS 트랜지스터의 구조를 이용한 본 발명에 따른 고전압용 반도체 소자의 구조를 제2도에 나타내 보였다.The structure of the high voltage semiconductor device according to the present invention using the structure of the NPN transistor and the structure of the PMOS transistor as described above is shown in FIG.
제2도를 참조하면, 본 발명에 따른 고전압용 반도체 소자는 LPNP 트랜지스터와 PMOS 트랜지스터 및 NPN 트랜지스터가 동시에 존재한다. 여기서, 상기 LPNP 트랜지스터의 에미터/컬렉터 부분과 상기 NPN 트랜지스터의 베이스 부분 및 상기 PMOS 트랜지스터의 소오스/드레인 부분의 접합영역이 제2도에 도시되어 있는 바와 같이 P-및 P형의 불순물 영역(130,135)으로 형성되어 있다. 상기 P-및 P형의 불순물 영역(130,135)은 N형의 웰(120)에 의해 둘러싸여 있으며, 상기 N형의 웰(120)은 P형의 기판(100) 상에 형성된 N-에피택셜층(170) 내에 형성되어 있다.Referring to FIG. 2, in the high voltage semiconductor device according to the present invention, an LPNP transistor, a PMOS transistor, and an NPN transistor exist simultaneously. Here, the LPNP emitter / collector portion and the base portion and the source / drain junction regions of the second degree P as shown in the portion of the PMOS transistor of the NPN transistor of the transistor and an impurity region of the P-type (130 135 ) The P − and P type impurity regions 130 and 135 are surrounded by the N type well 120, and the N type well 120 is formed on the N type epitaxial layer formed on the P type substrate 100. 170).
상기 N형의 웰(120)과 N-에피택셜층(170)은 상기 LPNP 트랜지스터의 베이스가 되고, 상기 P-및 P형의 불순물 영역(130,135)은 상기 NPN 트랜지스터의 베이스가 된다. 그리고, 본 발명 고전압용 반도체 소자에 의하면, 고내압화를 달성하기 위해 P-와 P형의 불순물 영역(130,135)이 오버랩(Overlap)되어 있다. 더욱이, 본 발명의 LPNP 트랜지스터는 n형의 웰(120)과 P-및 P형의 불순물 영역(130,135)을 바람직하게 이용하며, 상기 N형의 웰(120)은 상기 LPNP 트랜지스터와 PMOS 트랜지스터 및 NPN 트랜지스터들을 전기적으로 격리시키기 위한 아이솔레이션(Isolation) 공정 또는 상기 NPN 트랜지스터의 베이스(Base) 형성 공정에 앞서서 바람직하게 행하여질 수 있다.The N type well 120 and the N-epitaxial layer 170 serve as the base of the LPNP transistor, and the P − and P type impurity regions 130 and 135 serve as the base of the NPN transistor. In the high voltage semiconductor device of the present invention, the P − and P type impurity regions 130 and 135 are overlapped to achieve high breakdown voltage. Furthermore, the present invention LPNP transistor is well 120 and P of n type - and preferably using the impurity region (130 135) of, and the P-type, and the well 120 of the N type is the LPNP transistor and a PMOS transistor and an NPN It may be preferably performed prior to an isolation process for electrically isolating transistors or a base forming process of the NPN transistor.
상기 구조를 갖는 본 발명에 따른 고전압용 반도체 소자의 제조공정을 제3도 내지 제7도를 참조하면서 설명한다.A manufacturing process of the high voltage semiconductor device according to the present invention having the above structure will be described with reference to FIGS. 3 to 7.
제3도를 참조하면, P형 기판(100) 내에 일반적인 바이폴라 공정에서와 같이 매몰층(Buried layer; BL,160) 및 P저부층(110)을 형성하고 N-에피택셜층(170)을 성장시킨다. 여기서, 상기 N-에피택셜층(170)의 성장두께는 필요에 따라 조절될 수 있다.Referring to FIG. 3, the buried layer BL 160 and the P bottom layer 110 are formed in the P-type substrate 100, and the N-epitaxial layer 170 is grown. Let's do it. Here, the growth thickness of the N-epitaxial layer 170 may be adjusted as needed.
제4도를 참조하면, 소정의 마스크를 사용하여 N형의 웰을 형성하기 위한 불순물(126)을 이온주입한다. 이때, 버퍼 산화막은 요구되지 않는다. 상기 결과물 상에 산화층(도시되지 않음)을 약 6000Å정도 형성하고, P 절연층(115)을 사진작업을 통해 P+증착하거나 이온주입하여 형성한다. 상기 산화층을 제거한 후, 버퍼 산화층(122)을 약 380Å 정도 성장시킨 후, 나이트라이드막(Nitride layer,124)을 증착한다. 그 다음, 소정의 마스크를 이용하여 상기 나이트라이드막(124) 사진작업으로 활성층 영역을 설정한다.Referring to FIG. 4, an impurity 126 is implanted to form an N-type well using a predetermined mask. At this time, no buffer oxide film is required. An oxide layer (not shown) is formed on the resultant at about 6000 mV, and the P insulating layer 115 is formed by P + deposition or ion implantation through photographic work. After removing the oxide layer, the buffer oxide layer 122 is grown to about 380 Å, and then a nitride layer 124 is deposited. Next, an active layer region is set by photolithography of the nitride film 124 using a predetermined mask.
제5도를 참조하면, 열산화 공정으로 LOCOS(Local Oxidation of Silicon) 산화막(150)을 형성하면서, P 절연층(115)과 N형의 웰(120)을 동시에 확산(Diffusion)시켜 형성한다.Referring to FIG. 5, the P insulating layer 115 and the N-type well 120 are simultaneously diffused while forming a LOCOS oxide film 150 by a thermal oxidation process.
제6도를 참조하면, 게이트 폴리를 증착하여 게이트(140)를 형성하고, P-불순물 영역(130) 형성을 위한 불순물을 이온주입한다. 여기서, 제4도의 N형 웰(120) 이온주입을 상기 P-불순물 영역(130) 이온주입 후에 할 수도 있으며, 부재번호 143은 포토레지스트(PR)를 나타낸다.Referring to FIG. 6, the gate poly is deposited to form the gate 140, and impurities are implanted to form the P − impurity region 130. Here, ion implantation of the N-type well 120 of FIG. 4 may be performed after ion implantation of the P − impurity region 130, and reference numeral 143 denotes a photoresist PR.
제7도를 참조하면, 제6도의 공정후에, 다시 LTO(Low Temperature Oxide)을 약 2000Å-5000Å 정도 증착하고, RIE(Reactive Ion Etching)를 진행하여 상기 게이트(140) 측벽에 스페이서(Spacer,145)를 형성하고, P형 불순물 영역(135) 형성을 위한 불순물을 이온주입한다. 그 다음, 드라이브 인 공정을 통해 P형 불순물 영역(135)을 형성하고, 에미터 마스크를 이용하여 에미터를 형성한다. 그리고, 통상의 바이폴러 제조방법과 동일한 제조방법을 실행하면 제2도에 도시된 바와 같은 본 발명의 고전압용 반도체 소자가 만들어진다.Referring to FIG. 7, after the process of FIG. 6, Low Temperature Oxide (LTO) is again deposited about 2000 kPa-5000 kPa, and reactive ion etching (RIE) is performed on the sidewalls of the gate 140. ), And an ion is implanted with impurities for forming the P-type impurity region 135. Next, a P-type impurity region 135 is formed through a drive-in process, and an emitter is formed using an emitter mask. Then, the same manufacturing method as that of the conventional bipolar manufacturing method produces the high voltage semiconductor device of the present invention as shown in FIG.
상술한 바와 같이 본 발명에 따른 고전압용 반도체 소자는, LPNP 내압을 향상시키기 위해 MOS 방법처럼 LPNP LDD(lightly doped drain)을 만들어 바이폴라 및 MOS를 동시에 사용할 수 있는 트랜지스터로 이루어지고, 에피택셜층 비저항의 변화없이 LPNP 에미터/컬렉터 하부 및 PMOS 소오스/드레인 하부에 에피택셜층의 농도를 증가시키는 N형의 웰(NWell)을 사용하여 고내압/고전류 바이폴라 LPNP 트랜지스터 및 고내압 PMOS를 형성한 것으로서, LPNP의 베이스 폭(Wb)을 증가시키지 않고 내압 및 전류 구동능력을 증진시킬 수 있는 이점을 제공한다. 또한, 본 발명은 N웰의 확산(diffusion) 시간을 없이하고 종래의 게이트 폴리(gate polly), 에미터/컬렉터를 이용하여 LPNP, PMOS의 전류구동능력 및 내압을 향상시키는 이점을 제공한다.As described above, the high voltage semiconductor device according to the present invention is made of a transistor capable of simultaneously using bipolar and MOS by making an LPNP LDD (lightly doped drain) like the MOS method in order to improve the LPNP withstand voltage. A high breakdown voltage / high current bipolar LPNP transistor and a high breakdown voltage PMOS were formed using an N-type well that increases the concentration of the epitaxial layer under the LPNP emitter / collector and the PMOS source / drain without change. It provides an advantage that can increase the breakdown voltage and current driving capability without increasing the base width (Wb) of the. In addition, the present invention provides an advantage of improving the current driving capability and the breakdown voltage of LPNP and PMOS by using a conventional gate polly and an emitter / collector without the diffusion time of N wells.
본 발명은 상기 실시예에 한정되지 않으며, 많은 변형이 본 발명의 기술적 사상내에서 당 분야에서 통상의 지식을 가진 자에 의하여 가능함은 물론이다.The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the technical idea of the present invention.
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