JP2013074146A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2013074146A
JP2013074146A JP2011212483A JP2011212483A JP2013074146A JP 2013074146 A JP2013074146 A JP 2013074146A JP 2011212483 A JP2011212483 A JP 2011212483A JP 2011212483 A JP2011212483 A JP 2011212483A JP 2013074146 A JP2013074146 A JP 2013074146A
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conductive layer
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element isolation
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JP5742631B2 (en
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Eiji Yoshida
英司 吉田
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Fujitsu Semiconductor Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

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Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving operation speed and reducing power consumption, and a manufacturing method thereof.SOLUTION: A semiconductor device comprises: a first element isolation insulating film for defining a first region on a semiconductor substrate; a first conductive layer of a first conductivity type formed on the first region of the semiconductor substrate; a semiconductor layer formed on the semiconductor substrate and having a second conductive layer of the first conductivity type formed by connecting the first conductive layer to a second region which is a part of the first region and a third conductive layer of the first conductivity type formed by connecting the first conductive layer to a third region which is the other part of the first region; a second element isolation insulating film provided in the semiconductor layer and isolating the second conductive layer and the third conductive layer; a gate insulating film formed on the second conductive layer; and a gate electrode electrically connected to the first conductive layer via the third conductive layer.

Description

本発明は、半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

半導体装置の消費電力を低減するためのトランジスタ構造として、ＤＴＭＯＳ（Dynamic Threshold Voltage MOSFET）と呼ばれる構造が提案されている。ＤＴＭＯＳは、ＳＯＩ基板を用いて個々のトランジスタのボディ電極を分離し、ゲート電極とボディ電極とを短絡したトランジスタ構造である。ＤＴＭＯＳによれば、トランジスタがオンの時には大きな駆動電流が得られる一方、オフの時には相対的にオン状態と比べて閾値電圧が高くなりリーク電流を抑制することができ、低消費電力化を図ることができる。   As a transistor structure for reducing power consumption of a semiconductor device, a structure called DTMOS (Dynamic Threshold Voltage MOSFET) has been proposed. DTMOS has a transistor structure in which body electrodes of individual transistors are separated using an SOI substrate, and a gate electrode and a body electrode are short-circuited. According to DTMOS, a large drive current can be obtained when the transistor is turned on, while a threshold voltage becomes relatively higher than the on state when the transistor is turned off, so that leakage current can be suppressed, and low power consumption can be achieved. Can do.

特開平０９−０７４１８９号公報JP 09-074189 A 特開平１１−０７４５２２号公報JP-A-11-074522 特開２００２−２０８６９６号公報JP 2002-208696 A 特開２００４−０８７６７１号公報JP 2004-087671 A 特表２００６−５０２５７３号公報JP 2006-502573 A

トランジスタの更なる高速化及び低消費電力化のために、寄生容量をより低減しうる半導体装置の構造及び製造方法が待望されている。   In order to further increase the speed and lower power consumption of transistors, a structure and manufacturing method of a semiconductor device that can further reduce parasitic capacitance are desired.

本発明の目的は、動作速度を向上し消費電力を低減しうる半導体装置及びその製造方法を提供することにある。   An object of the present invention is to provide a semiconductor device capable of improving the operation speed and reducing power consumption and a method for manufacturing the same.

実施形態の一観点によれば、半導体基板に第１の領域を画定する第１の素子分離絶縁膜と、前記半導体基板の前記第１の領域に形成された第１導電型の第１の導電層と、前記半導体基板上に形成され、前記第１の領域の一部である第２の領域に前記第１の導電層に接続して形成された前記第１導電型の第２の導電層と、前記第１の領域の他の一部である第３の領域に前記第１の導電層に接続して形成された前記第１導電型の第３の導電層とを有する半導体層と、前記半導体層内に設けられ、前記第２の導電層と前記第３の導電層とを分離する第２の素子分離絶縁膜と、前記第２の導電層上に形成されたゲート絶縁膜と、前記ゲート絶縁膜上に形成され、前記第３の導電層を介して前記第１の導電層に電気的に接続されたゲート電極とを有する半導体装置が提供される。   According to one aspect of the embodiment, a first element isolation insulating film that defines a first region in a semiconductor substrate, and a first conductivity type first conductor formed in the first region of the semiconductor substrate. And a second conductive layer of the first conductivity type formed on the semiconductor substrate and connected to the first conductive layer in a second region which is a part of the first region. A semiconductor layer having a third conductive layer of the first conductivity type formed in a third region that is another part of the first region and connected to the first conductive layer; A second element isolation insulating film provided in the semiconductor layer and separating the second conductive layer and the third conductive layer; a gate insulating film formed on the second conductive layer; A gate electrode formed on the gate insulating film and electrically connected to the first conductive layer through the third conductive layer; Conductor device is provided.

また、実施形態の他の観点によれば、半導体基板に第１の領域及び第２の領域を画定する第１の素子分離絶縁膜と、前記半導体基板の前記第１の領域に形成され、前記第１の素子分離絶縁膜の底部よりも浅い第１導電型の第１の導電層と、前記半導体基板の前記第２の領域に形成され、前記第１の素子分離絶縁膜の底部よりも浅い前記第１導電型の第２の導電層と、前記第１の導電層及び前記第２の導電層下の前記半導体基板内に形成され、前記第１の素子分離絶縁膜の底部よりも深い第２導電型の第３の導電層と、前記半導体基板上に形成され、前記第１の領域の一部である第３の領域に前記第１の導電層に接続して形成された前記第１導電型の第４の導電層と、前記第２の領域の一部である第４の領域に前記第１の導電層に接続して形成された前記第１導電型の第５の導電層と、前記第１の領域の他の一部である第５の領域に前記第１の導電層に接続して形成された前記第１導電型の第６の導電層と、前記第２の領域の他の一部である第６の領域に前記第１の導電層に接続して形成された前記第１導電型の第７の導電層と、前記第３の領域と前記第４の領域との間の第７の領域に前記第１の素子分離絶縁膜に接して形成された前記第２導電型の第８の導電層とを有する半導体層と、前記半導体層内に形成され、前記第２の導電層、前記第３導電層及び前記第６の導電層と前記４の導電層とを分離し、前記第２の導電層、前記第３導電層及び前記第６の導電層と前記第５の導電層とを分離する第２の素子分離絶縁膜と、前記第２の導電層上に形成された第１のゲート絶縁膜と、前記第３の導電層上に形成された第２のゲート絶縁膜と、前記第１のゲート絶縁膜上に形成され、前記第４の導電層を介して前記第１の導電層に電気的に接続された第１のゲート電極と、前記第２のゲート絶縁膜上に形成され、前記第５の導電層を介して前記第２の導電層に電気的に接続された第２のゲート電極とを有する半導体装置が提供される。   Further, according to another aspect of the embodiment, the first element isolation insulating film defining the first region and the second region in the semiconductor substrate, and the first region of the semiconductor substrate are formed, A first conductive layer of the first conductivity type shallower than the bottom of the first element isolation insulating film and the second region of the semiconductor substrate are shallower than the bottom of the first element isolation insulating film. A second conductive layer of the first conductivity type, formed in the semiconductor substrate under the first conductive layer and the second conductive layer, and deeper than a bottom of the first element isolation insulating film; A second conductive type third conductive layer; and the first conductive layer formed on the semiconductor substrate and connected to the first conductive layer in a third region that is a part of the first region. A conductive type fourth conductive layer and a fourth region that is a part of the second region are connected to the first conductive layer. The first conductivity type formed on the fifth conductive layer of the first conductivity type and the fifth region which is another part of the first region connected to the first conductive layer. A sixth conductive layer, and a seventh conductive layer of the first conductivity type formed by being connected to the first conductive layer in a sixth region which is another part of the second region. A second conductive type eighth conductive layer formed in contact with the first element isolation insulating film in a seventh region between the third region and the fourth region; And the second conductive layer, the third conductive layer, the sixth conductive layer, and the fourth conductive layer are formed in the semiconductor layer, and the second conductive layer, the second conductive layer, A third element isolation insulating film that separates the three conductive layers and the sixth conductive layer from the fifth conductive layer; a first gate insulating film formed on the second conductive layer; A second gate insulating film formed on a third conductive layer; and a second gate insulating film formed on the first gate insulating film and electrically connected to the first conductive layer through the fourth conductive layer And a second gate electrode formed on the second gate insulating film and electrically connected to the second conductive layer through the fifth conductive layer. A semiconductor device is provided.

また、実施形態の更に他の観点によれば、半導体基板に、第１の領域を画定する第１の素子分離絶縁膜を形成する工程と、前記第１の素子分離絶縁膜が形成された前記半導体基板上に、半導体層を形成する工程と、前記半導体層に、前記第１の領域の一部の領域を含む第２の領域と、前記第１の領域の他の一部の領域を含む第３の領域を画定する第２の素子分離絶縁膜を形成する工程と、前記半導体基板及び前記半導体層に、前記第２の素子絶縁膜の底部よりも深く、前記第１の素子分離絶縁膜の底部よりも浅い第１導電型の第１のウェルを形成する工程と、前記半導体層の前記第２の領域上に、ゲート絶縁膜を形成する工程と、前記ゲート絶縁膜上に、前記半導体層の前記第３の領域を介して前記第１のウェルに電気的に接続されたゲート電極を形成する工程とを有する半導体装置の製造方法が提供される。   According to still another aspect of the embodiment, a step of forming a first element isolation insulating film that defines a first region on a semiconductor substrate, and the step of forming the first element isolation insulating film Forming a semiconductor layer over the semiconductor substrate; and including a second region including a partial region of the first region and another partial region of the first region in the semiconductor layer. Forming a second element isolation insulating film defining a third region; and forming the first element isolation insulating film deeper than a bottom of the second element insulating film in the semiconductor substrate and the semiconductor layer. Forming a first well of a first conductivity type shallower than the bottom of the semiconductor layer, forming a gate insulating film on the second region of the semiconductor layer, and forming the semiconductor on the gate insulating film A gate electrically connected to the first well through the third region of the layer The method of manufacturing a semiconductor device having a step of forming a pole is provided.

開示の半導体装置及びその製造方法によれば、寄生容量を大幅に低減することができる。これにより、トランジスタの高速化及び低消費電力化を図ることができる。   According to the disclosed semiconductor device and the manufacturing method thereof, the parasitic capacitance can be significantly reduced. Accordingly, the transistor can be increased in speed and power consumption can be reduced.

図１は、一実施形態による半導体装置の構造を示す平面図である。FIG. 1 is a plan view illustrating a structure of a semiconductor device according to an embodiment. 図２は、一実施形態による半導体装置の構造を示す概略断面図である。FIG. 2 is a schematic cross-sectional view illustrating the structure of the semiconductor device according to the embodiment. 図３は、一実施形態による半導体装置の製造方法を示す平面図（その１）である。FIG. 3 is a plan view (part 1) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図４は、一実施形態による半導体装置の製造方法を示す工程断面図（その１）である。FIG. 4 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the embodiment. 図５は、一実施形態による半導体装置の製造方法を示す平面図（その２）である。FIG. 5 is a plan view (part 2) illustrating the semiconductor device manufacturing method according to the embodiment. 図６は、一実施形態による半導体装置の製造方法を示す工程断面図（その２）である。FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図７は、一実施形態による半導体装置の製造方法を示す平面図（その３）である。FIG. 7 is a plan view (part 3) illustrating the method for manufacturing a semiconductor device according to the embodiment. 図８は、一実施形態による半導体装置の製造方法を示す工程断面図（その３）である。FIG. 8 is a process cross-sectional view (Part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図９は、一実施形態による半導体装置の製造方法を示す工程断面図（その４）である。FIG. 9 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図１０は、一実施形態による半導体装置の製造方法を示す平面図（その４）である。FIG. 10 is a plan view (part 4) illustrating the method for fabricating the semiconductor device according to the embodiment. 図１１は、一実施形態による半導体装置の製造方法を示す工程断面図（その５）である。FIG. 11 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図１２は、一実施形態による半導体装置の製造方法を示す平面図（その５）である。FIG. 12 is a plan view (part 5) illustrating the method for fabricating a semiconductor device according to the embodiment. 図１３は、一実施形態による半導体装置の製造方法を示す工程断面図（その６）である。FIG. 13 is a process cross-sectional view (Part 6) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図１４は、一実施形態による半導体装置の製造方法を示す平面図（その６）である。FIG. 14 is a plan view (No. 6) illustrating the method for manufacturing a semiconductor device according to the embodiment. 図１５は、一実施形態による半導体装置の製造方法を示す工程断面図（その７）である。FIG. 15 is a process cross-sectional view (part 7) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図１６は、一実施形態による半導体装置の製造方法を示す平面図（その７）である。FIG. 16 is a plan view (part 7) illustrating the method for fabricating a semiconductor device according to the embodiment. 図１７は、一実施形態による半導体装置の製造方法を示す工程断面図（その８）である。FIG. 17 is a process cross-sectional view (Part 8) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図１８は、一実施形態による半導体装置の製造方法を示す平面図（その８）である。FIG. 18 is a plan view (No. 8) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図１９は、一実施形態による半導体装置の製造方法を示す工程断面図（その９）である。FIG. 19 is a process cross-sectional view (No. 9) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図２０は、一実施形態による半導体装置の製造方法を示す平面図（その９）である。FIG. 20 is a plan view (No. 9) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図２１は、一実施形態による半導体装置の製造方法を示す工程断面図（その１０）である。FIG. 21 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図２２は、一実施形態による半導体装置の製造方法を示す工程断面図（その１１）である。FIG. 22 is a process cross-sectional view (Part 11) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図２３は、一実施形態による半導体装置の製造方法を示す平面図（その１０）である。FIG. 23 is a plan view (No. 10) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図２４は、一実施形態による半導体装置の製造方法を示す工程断面図（その１２）である。FIG. 24 is a process cross-sectional view (Part 12) illustrating the method for manufacturing the semiconductor device according to the embodiment. 図２５は、一実施形態の変形例による半導体装置の構造を示す概略断面図である。FIG. 25 is a schematic cross-sectional view showing the structure of a semiconductor device according to a modification of one embodiment.

一実施形態による半導体装置及びその製造方法について図１乃至図２４を用いて説明する。   A semiconductor device and a manufacturing method thereof according to an embodiment will be described with reference to FIGS.

図１は、本実施形態による半導体装置の構造を示す平面図である。図２は、本実施形態による半導体装置の構造を示す概略断面図である。図３乃至図２４は、本実施形態による半導体装置の製造方法を示す工程図である。   FIG. 1 is a plan view showing the structure of the semiconductor device according to the present embodiment. FIG. 2 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 3 to 24 are process diagrams showing the method of manufacturing the semiconductor device according to the present embodiment.

はじめに、本実施形態による半導体装置の構造について図１及び図２を用いて説明する。なお、図２（ａ）は図１のＡ−Ａ′線断面図であり、図２（ｂ）は図１のＢ−Ｂ′線断面図である。   First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. 2A is a cross-sectional view taken along the line AA ′ in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line BB ′ in FIG.

シリコン基板１０には、活性領域２０を画定する素子分離絶縁膜１８が形成されている。活性領域２０は、トランジスタのチャネル領域下からボディコンタクト領域に至るボディ領域が形成される領域である。   An element isolation insulating film 18 that defines the active region 20 is formed on the silicon substrate 10. The active region 20 is a region where a body region extending from under the channel region of the transistor to the body contact region is formed.

素子分離絶縁膜１８が形成されたシリコン基板１０上には、シリコン膜２２，２４が形成されている。このシリコン膜２２，２４は、シリコン基板１０上にエピタキシャル成長された単結晶シリコン膜２２と、素子分離絶縁膜１８上に成長された多結晶シリコン膜２４とを含む。シリコン膜２２，２４内には、活性領域３２ａ，３２ｂを画定する素子分離絶縁膜３２が設けられている。活性領域３２ａは、トランジスタのチャネル領域及びソース／ドレイン領域４８が形成される領域であり、チャネル領域部分が活性領域２０の一部の領域に接続して形成されている。活性領域３２ｂは、ボディコンタクト領域が形成される領域であり、活性領域２０の他の一部の領域に接続して形成されている。   Silicon films 22 and 24 are formed on the silicon substrate 10 on which the element isolation insulating film 18 is formed. The silicon films 22 and 24 include a single crystal silicon film 22 epitaxially grown on the silicon substrate 10 and a polycrystalline silicon film 24 grown on the element isolation insulating film 18. In the silicon films 22 and 24, an element isolation insulating film 32 that defines active regions 32a and 32b is provided. The active region 32 a is a region where the channel region and the source / drain region 48 of the transistor are formed, and the channel region portion is formed so as to be connected to a part of the active region 20. The active region 32b is a region where a body contact region is formed, and is formed so as to be connected to another part of the active region 20.

シリコン基板１０内には、素子分離絶縁膜１８の底部よりも深いＮウェル３４が形成されている。また、シリコン基板１０及びシリコン膜２２，２４の、素子分離絶縁膜３２の底部よりも深く、素子分離絶縁膜１８の底部よりも浅い領域には、Ｐウェル３６が形成されている。これにより、Ｐウェル３６は、Ｎウェル３４によってシリコン基板１０の他の領域から分離されている。   An N well 34 deeper than the bottom of the element isolation insulating film 18 is formed in the silicon substrate 10. A P well 36 is formed in a region of the silicon substrate 10 and the silicon films 22 and 24 that is deeper than the bottom of the element isolation insulating film 32 and shallower than the bottom of the element isolation insulating film 18. As a result, the P well 36 is separated from other regions of the silicon substrate 10 by the N well 34.

なお、本願明細書では、二重ウェルの中のウェル（Ｐウェル３６）を、シリコン基板１０の表面部に形成された導電層と、活性領域３２ａに形成された導電層と、活性領域３２ｂに形成された導電層とに分けて説明することがある。また、二重ウェルの外のウェル（Ｎウェル３４）についても、導電層と表現することがある。   In the present specification, the well (P well 36) in the double well is divided into a conductive layer formed on the surface portion of the silicon substrate 10, a conductive layer formed in the active region 32a, and an active region 32b. The description may be divided into the formed conductive layer. Further, a well (N well 34) outside the double well may be expressed as a conductive layer.

活性領域３２ａ上には、ゲート絶縁膜３８を介してゲート電極４０が形成されている。ゲート電極４０の両側の活性領域３２ａ内には、ソース／ドレイン領域４８が形成されている。なお、本願明細書では、ソース／ドレイン領域を導電層と呼ぶこともある。   A gate electrode 40 is formed on the active region 32a via a gate insulating film 38. Source / drain regions 48 are formed in the active regions 32 a on both sides of the gate electrode 40. In the present specification, the source / drain regions may be referred to as conductive layers.

こうして、活性領域３２ａには、ゲート電極４０及びソース／ドレイン領域４８を有するＮ型トランジスタが形成されている。   Thus, an N-type transistor having the gate electrode 40 and the source / drain region 48 is formed in the active region 32a.

本実施形態による半導体装置は、一の活性領域３２ａ内に、ソース／ドレイン領域４８の一方を共用する２つのＮ型トランジスタを有している。これらＮ型トランジスタのソース／ドレイン領域４８の底面は、素子分離絶縁膜１８に達しており、各トランジスタのボディ領域（Ｐウェル３６）は、Ｎウェル３４、素子分離絶縁膜１８及びソース／ドレイン領域４８によって互いに分離されている。   The semiconductor device according to the present embodiment has two N-type transistors sharing one of the source / drain regions 48 in one active region 32a. The bottom surfaces of the source / drain regions 48 of these N-type transistors reach the element isolation insulating film 18, and the body region (P well 36) of each transistor includes the N well 34, the element isolation insulating film 18, and the source / drain regions. 48 separated from each other.

活性領域３２ｂ内には、Ｐウェル３６へのコンタクト層としてのＰ型不純物層５０が形成されている。これにより、Ｐ型不純物層５０は、Ｐウェル３６を介してＮ型トランジスタのボディ領域に電気的に接続されている。   A P-type impurity layer 50 as a contact layer to the P well 36 is formed in the active region 32b. Thereby, the P-type impurity layer 50 is electrically connected to the body region of the N-type transistor via the P-well 36.

Ｎ型トランジスタのゲート電極４０上、ソース／ドレイン領域４８上、Ｐ型不純物層５０上には、金属シリサイド膜５２が形成されている。   A metal silicide film 52 is formed on the gate electrode 40, the source / drain region 48, and the P-type impurity layer 50 of the N-type transistor.

Ｎ型トランジスタが形成されたシリコン基板１０上には、層間絶縁膜５４が形成されている。層間絶縁膜５４には、ソース／ドレイン領域４８上の金属シリサイド膜５２に接続されたコンタクトプラグ６０と、ゲート電極４０及びＰ型不純物層５０上の金属シリサイド膜５２に接続されたコンタクトプラグ６２とが埋め込まれている。コンタクトプラグ６２は、ゲート電極４０とＰ型不純物層５０とを接続するシェアードコンタクトである。   An interlayer insulating film 54 is formed on the silicon substrate 10 on which the N-type transistor is formed. The interlayer insulating film 54 includes a contact plug 60 connected to the metal silicide film 52 on the source / drain region 48, and a contact plug 62 connected to the metal silicide film 52 on the gate electrode 40 and the P-type impurity layer 50. Is embedded. The contact plug 62 is a shared contact that connects the gate electrode 40 and the P-type impurity layer 50.

このように、本実施形態による半導体装置では、ソース／ドレイン領域４８の底部が素子分離絶縁膜１８に接している。また、トランジスタのチャネル領域（活性領域３２ａ）とボディコンタクト領域（活性領域３２ｂ）とは素子分離絶縁膜３２により分離されており、Ｐ型不純物層５０とソース／ドレイン領域４８とは直に接していない。これにより、ソース／ドレイン領域４８とＰウェル３６及びＰ型不純物層５０との間の接合容量を大幅に低減することができ、トランジスタの高速化及び低消費電力化を図ることができる。   Thus, in the semiconductor device according to the present embodiment, the bottom of the source / drain region 48 is in contact with the element isolation insulating film 18. Further, the channel region (active region 32a) and the body contact region (active region 32b) of the transistor are separated by the element isolation insulating film 32, and the P-type impurity layer 50 and the source / drain region 48 are in direct contact with each other. Absent. As a result, the junction capacitance between the source / drain region 48 and the P well 36 and the P-type impurity layer 50 can be greatly reduced, and the speed and power consumption of the transistor can be increased.

また、一の活性領域３２ａ内に、ソース／ドレイン領域４８の一方を共用する２つのＮ型トランジスタが形成されている。この２つのＮ型トランジスタのボディ領域は、ソース／ドレイン領域４８及び素子分離絶縁膜１８によって分離することができ、素子分離絶縁膜３２によって分離することを要しない。これにより、素子の配置間隔を狭めることができ、集積度を向上することができる。   Further, two N-type transistors sharing one of the source / drain regions 48 are formed in one active region 32a. The body regions of the two N-type transistors can be separated by the source / drain regions 48 and the element isolation insulating film 18, and need not be separated by the element isolation insulating film 32. Thereby, the arrangement | positioning space | interval of an element can be narrowed and an integration degree can be improved.

なお、ソース／ドレイン領域の一方同士が接続された２つのＮ型トランジスタを含む回路の一例としては、例えば、ＣＭＯＳ ＮＡＮＤ回路が挙げられる。   An example of a circuit including two N-type transistors in which one of the source / drain regions is connected is a CMOS NAND circuit.

次に、本実施形態による半導体装置の製造方法について図３乃至図２４を用いて説明する。なお、図３，５，７，１０，１２，１４，１６，１８，２０，２３は、本実施形態による半導体装置の製造方法を示す平面図である。図４、６，８，９，１１，１３，１５，１７，１９，２１，２２，２４は、本実施形態による半導体装置の製造方法を示す工程断面図である。図４、６，８，９，１１，１３，１５，１７，１９，２１，２２，２４において（ａ）図及び（ｂ）図は、それぞれ、図１のＡ−Ａ′線断面図及びＢ−Ｂ′線断面図に対応している。   Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3, 5, 7, 10, 12, 14, 16, 18, 20, and 23 are plan views showing the method for manufacturing the semiconductor device according to the present embodiment. 4, 6, 8, 9, 11, 13, 15, 17, 19, 21, 22, and 24 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment. 4, 6, 8, 9, 11, 13, 15, 17, 19, 21, 22, and 24, (a) and (b) are respectively a cross-sectional view along line AA ′ and B in FIG. 1. This corresponds to a cross-sectional view taken along line -B '.

まず、シリコン基板１０上に、例えば熱酸化法により、例えば膜厚３〜１０ｎｍ程度のシリコン酸化膜１２を形成する。   First, a silicon oxide film 12 having a film thickness of, eg, about 3 to 10 nm is formed on the silicon substrate 10 by, eg, thermal oxidation.

次いで、シリコン酸化膜１２上に、例えばＬＰＣＶＤ法により、例えば膜厚７０〜１００ｎｍ程度のシリコン窒化膜１４を形成する。   Next, a silicon nitride film 14 having a thickness of, for example, about 70 to 100 nm is formed on the silicon oxide film 12 by, eg, LPCVD.

次いで、フォトリソグラフィ及びドライエッチングにより、シリコン窒化膜１４及びシリコン酸化膜１２をパターニングし、深い素子分離絶縁膜１８の形成予定領域のシリコン窒化膜１４及びシリコン酸化膜１２を除去する。   Next, the silicon nitride film 14 and the silicon oxide film 12 are patterned by photolithography and dry etching, and the silicon nitride film 14 and the silicon oxide film 12 in the region where the deep element isolation insulating film 18 is to be formed are removed.

次いで、シリコン窒化膜１４をマスクとしてシリコン基板１０をドライエッチングし、シリコン基板１０に、深さが例えば３００ｎｍ程度の素子分離溝１６を形成する（図３、図４（ａ）、（ｂ））。   Next, the silicon substrate 10 is dry-etched using the silicon nitride film 14 as a mask to form element isolation grooves 16 having a depth of, for example, about 300 nm in the silicon substrate 10 (FIGS. 3, 4A, and 4B). .

次いで、例えば熱酸化法により、素子分離溝１６の側壁及び底面に、膜厚５ｎｍ程度のシリコン酸化膜（図示せず）を形成する。   Next, a silicon oxide film (not shown) having a film thickness of about 5 nm is formed on the side wall and the bottom surface of the element isolation trench 16 by, eg, thermal oxidation.

次いで、全面に、例えば高密度プラズマＣＶＤ法により、例えば膜厚４５０ｎｍ程度のシリコン酸化膜を堆積する。   Next, a silicon oxide film having a thickness of, eg, about 450 nm is deposited on the entire surface by, eg, high density plasma CVD.

次いで、例えばＣＭＰ（Chemical Mechanical Polishing：化学的機械的研磨）法により、シリコン窒化膜１４上のシリコン酸化膜を除去する。こうして、いわゆるＳＴＩ（Shallow Trench Isolation）法により、素子分離溝１６に埋め込まれたシリコン酸化膜により、活性領域２０を画定する素子分離絶縁膜１８を形成する。   Next, the silicon oxide film on the silicon nitride film 14 is removed by, for example, a CMP (Chemical Mechanical Polishing) method. Thus, the element isolation insulating film 18 that defines the active region 20 is formed by the silicon oxide film embedded in the element isolation trench 16 by a so-called STI (Shallow Trench Isolation) method.

活性領域２０は、トランジスタのチャネル領域下からボディコンタクト領域に至るボディ領域を画定するためのものである。ここでは、例えば、幅１００ｎｍのストライプ状の活性領域２０を、１００ｎｍ間隔で形成するものとする。   The active region 20 is for defining a body region from the bottom of the channel region of the transistor to the body contact region. Here, for example, stripe-like active regions 20 having a width of 100 nm are formed at intervals of 100 nm.

次いで、例えばホットリン酸を用いたウェットエッチングにより、シリコン窒化膜１４を除去する。   Next, the silicon nitride film 14 is removed by wet etching using, for example, hot phosphoric acid.

次いで、例えば弗酸水溶液を用いたウェットエッチングにより、シリコン酸化膜１２を除去するとともに、シリコン基板１０の表面と素子分離絶縁膜１８の表面とが平坦になるように、素子分離絶縁膜１８をエッチングする（図５、図６（ａ）、（ｂ））。   Next, the silicon oxide film 12 is removed by wet etching using, for example, an aqueous hydrofluoric acid solution, and the element isolation insulating film 18 is etched so that the surface of the silicon substrate 10 and the surface of the element isolation insulating film 18 become flat. (FIG. 5, FIG. 6 (a), (b)).

次いで、全面に、例えばＬＰＣＶＤ法により、シリコン膜を成長する。この際、シリコン基板１０が露出している活性領域２０上には単結晶シリコン膜２２がエピタキシャル成長し、素子分離絶縁膜１８上には多結晶シリコン膜２４が成長する（図７、図８（ａ）、（ｂ））。   Next, a silicon film is grown on the entire surface by, eg, LPCVD. At this time, the single crystal silicon film 22 is epitaxially grown on the active region 20 where the silicon substrate 10 is exposed, and the polycrystalline silicon film 24 is grown on the element isolation insulating film 18 (FIG. 7, FIG. 8A). ), (B)).

単結晶シリコン膜２２及び多結晶シリコン膜２４は、例えば、原料ガスにＳｉ２Ｈ６又はＳｉＨ４ガスを用い、成長温度を５８０℃〜７００℃、好ましくは６５０℃〜７００℃、圧力を２０Ｐａ〜１００Ｐａとしてシリコン膜を成長する。これにより、活性領域２０上に単結晶シリコン膜２２を選択的にエピタキシャル成長し、素子分離絶縁膜１８上に多結晶シリコン膜２４を選択的に成長することができる。また、単結晶シリコン膜２２及び多結晶シリコン膜２４の膜厚を、ほぼ均一にすることができる。 The single crystal silicon film 22 and the polycrystalline silicon film 24 are formed using, for example, Si 2 H 6 or SiH 4 gas as a source gas, a growth temperature of 580 ° C. to 700 ° C., preferably 650 ° C. to 700 ° C., and a pressure of 20 Pa to A silicon film is grown at 100 Pa. Thereby, the single crystal silicon film 22 can be selectively epitaxially grown on the active region 20, and the polycrystalline silicon film 24 can be selectively grown on the element isolation insulating film 18. Further, the film thicknesses of the single crystal silicon film 22 and the polycrystalline silicon film 24 can be made substantially uniform.

次いで、全面に、例えばＬＰＣＶＤ法により、例えば膜厚５０ｎｍ程度のシリコン窒化膜２６を形成する（図９）。なお、シリコン窒化膜２６とシリコン膜２２，２４との間にシリコン酸化膜を形成するようにしてもよい。   Next, a silicon nitride film 26 of, eg, a thickness of about 50 nm is formed on the entire surface by, eg, LPCVD (FIG. 9). A silicon oxide film may be formed between the silicon nitride film 26 and the silicon films 22 and 24.

次いで、フォトリソグラフィにより、シリコン窒化膜２６上に、活性領域３２ａ，３２ｂの形成領域を覆い、素子分離絶縁膜３２の形成領域を露出するフォトレジスト膜２８を形成する（図１０、図１１（ａ）、（ｂ））。   Next, by photolithography, a photoresist film 28 is formed on the silicon nitride film 26 so as to cover the formation regions of the active regions 32a and 32b and expose the formation region of the element isolation insulating film 32 (FIGS. 10 and 11A). ), (B)).

次いで、フォトレジスト膜２８をマスクとしてシリコン窒化膜２６ドライエッチングし、フォトレジスト膜２８のパターンをシリコン窒化膜２６に転写する。   Next, the silicon nitride film 26 is dry-etched using the photoresist film 28 as a mask, and the pattern of the photoresist film 28 is transferred to the silicon nitride film 26.

次いで、例えばアッシングにより、フォトレジスト膜２８を除去する（図１２、図１３（ａ）、（ｂ））。   Next, the photoresist film 28 is removed by, for example, ashing (FIGS. 12, 13A, and 13B).

次いで、シリコン窒化膜２６をマスクとして単結晶シリコン膜２２及び多結晶シリコン膜２４をドライエッチングし、素子分離絶縁膜３２の形成領域の単結晶シリコン膜２２及び多結晶シリコン膜２４を除去する。これにより、単結晶シリコン膜２２及び多結晶シリコン膜２４に、素子分離絶縁膜３２を埋め込むための素子分離溝３０を形成する（図１４、図１５（ａ）、（ｂ））。   Next, the single crystal silicon film 22 and the polycrystalline silicon film 24 are dry-etched using the silicon nitride film 26 as a mask, and the single crystal silicon film 22 and the polycrystalline silicon film 24 in the formation region of the element isolation insulating film 32 are removed. Thereby, an element isolation trench 30 for embedding the element isolation insulating film 32 is formed in the single crystal silicon film 22 and the polycrystalline silicon film 24 (FIGS. 14, 15A, and 15B).

次いで、例えば熱酸化法により、素子分離溝３０の側壁及び底面に、膜厚５ｎｍ程度のシリコン酸化膜（図示せず）を形成する。   Next, a silicon oxide film (not shown) having a film thickness of about 5 nm is formed on the side wall and the bottom surface of the element isolation trench 30 by, eg, thermal oxidation.

次いで、全面に、例えば高密度プラズマＣＶＤ法により、例えば膜厚１２０ｎｍ程度のシリコン酸化膜を堆積する。   Next, a silicon oxide film having a thickness of, for example, about 120 nm is deposited on the entire surface by, eg, high density plasma CVD.

次いで、例えばＣＭＰ法により、シリコン窒化膜２６上のシリコン酸化膜を除去する。こうして、ＳＴＩ法により、素子分離溝３０に埋め込まれたシリコン酸化膜により素子分離絶縁膜３２を形成する。これにより、単結晶シリコン膜２２及び多結晶シリコン膜２４に、活性領域３２ａと活性領域３２ｂとを画定する。   Next, the silicon oxide film on the silicon nitride film 26 is removed by, eg, CMP. Thus, the element isolation insulating film 32 is formed by the silicon oxide film embedded in the element isolation trench 30 by the STI method. Thus, an active region 32a and an active region 32b are defined in the single crystal silicon film 22 and the polycrystalline silicon film 24.

活性領域３２ａは、トランジスタのチャネル領域及びソース／ドレイン領域４８を形成するための領域である。なお、本願明細書では、トランジスタのチャネル領域及びソース／ドレイン領域４８を形成するためのこの領域を、トランジスタ形成領域と呼ぶこともある。活性領域３２ｂは、トランジスタのボディ領域から電極を引き出すためのボディコンタクト領域を形成するための領域である。ここでは、例えば、活性領域３２ａから１００ｎｍ離間して１００ｎｍ幅の活性領域３２ｂを形成するものとする。   The active region 32a is a region for forming a channel region and a source / drain region 48 of the transistor. In this specification, this region for forming the channel region and the source / drain region 48 of the transistor may be referred to as a transistor formation region. The active region 32b is a region for forming a body contact region for extracting an electrode from the body region of the transistor. Here, for example, the active region 32b having a width of 100 nm is formed 100 nm away from the active region 32a.

次いで、例えばホットリン酸を用いたウェットエッチングにより、シリコン窒化膜２６を除去する。   Next, the silicon nitride film 26 is removed by wet etching using, for example, hot phosphoric acid.

次いで、例えば弗酸水溶液を用いたウェットエッチングにより、単結晶シリコン膜２２及び多結晶シリコン膜２４の表面と素子分離絶縁膜３２の表面とが平坦になるように、素子分離絶縁膜３２をエッチングする。   Next, the element isolation insulating film 32 is etched so that the surfaces of the single crystal silicon film 22 and the polycrystalline silicon film 24 and the surface of the element isolation insulating film 32 become flat by wet etching using, for example, a hydrofluoric acid aqueous solution. .

次いで、フォトリソグラフィ及びイオン注入により、シリコン基板１０内に、素子分離絶縁膜１８の底部よりも深いＮウェル３４を形成する。また、シリコン基板１０内及びシリコン膜２２，２４内に、素子分離絶縁膜３２の底部よりも深く、素子分離絶縁膜１８の底部よりも浅いＰウェル３６を形成する（図１６、図１７（ａ）、（ｂ））。Ｐウェル３６を形成する際のイオン注入には、所定のチャネルイオン注入も含まれる。なお、Ｎウェル３４及びＰウェルの形成は、シリコン膜２２，２４の形成後、素子分離絶縁膜３２の形成前に行ってもよい。   Next, an N well 34 deeper than the bottom of the element isolation insulating film 18 is formed in the silicon substrate 10 by photolithography and ion implantation. Further, a P well 36 deeper than the bottom of the element isolation insulating film 32 and shallower than the bottom of the element isolation insulating film 18 is formed in the silicon substrate 10 and the silicon films 22 and 24 (FIGS. 16 and 17A). ), (B)). The ion implantation for forming the P well 36 includes predetermined channel ion implantation. The N well 34 and the P well may be formed after the silicon films 22 and 24 are formed and before the element isolation insulating film 32 is formed.

次いで、単結晶シリコン膜２２及び多結晶シリコン膜２４の表面を熱酸化し、シリコン酸化膜のゲート絶縁膜３８を形成する。   Next, the surfaces of the single crystal silicon film 22 and the polycrystalline silicon film 24 are thermally oxidized to form a silicon oxide gate insulating film 38.

次いで、ゲート絶縁膜３８上に、例えばＬＰＣＶＤ法により、例えば膜厚１００ｎｍの多結晶シリコン膜を堆積する。   Next, a polycrystalline silicon film of, eg, a 100 nm-thickness is deposited on the gate insulating film 38 by, eg, LPCVD.

次いで、フォトリソグラフィ及びドライエッチングにより、この多結晶シリコン膜をパターニングし、多結晶シリコンのゲート電極４０を形成する（図１８、図１９（ａ）、（ｂ））。ここでは、例えばゲート長が５０ｎｍのゲート電極４０を形成するものとする。   Next, the polycrystalline silicon film is patterned by photolithography and dry etching to form a polycrystalline silicon gate electrode 40 (FIGS. 18, 19A and 19B). Here, for example, the gate electrode 40 having a gate length of 50 nm is formed.

なお、本実施形態では、単結晶シリコン膜２２及び多結晶シリコン膜２４の表面と素子分離絶縁膜３２の表面とが平坦化されており、ゲート電極４０となる多結晶シリコン膜の形成面が略平坦であるため、ゲート電極４０のパターニングが容易である。   In the present embodiment, the surfaces of the single crystal silicon film 22 and the polycrystalline silicon film 24 and the surface of the element isolation insulating film 32 are flattened, and the formation surface of the polycrystalline silicon film to be the gate electrode 40 is substantially the same. Since it is flat, the patterning of the gate electrode 40 is easy.

次いで、ゲート電極４０をマスクとしてイオン注入を行い、ゲート電極４０の両側の活性領域３２ａ内に、エクステンション領域となるＮ型不純物層４２を形成する。必要に応じて、Ｎ型不純物層４２とともにＰ型ポケット領域を形成するようにしてもよい。   Next, ion implantation is performed using the gate electrode 40 as a mask, and an N-type impurity layer 42 serving as an extension region is formed in the active regions 32 a on both sides of the gate electrode 40. A P-type pocket region may be formed together with the N-type impurity layer 42 as necessary.

次いで、例えばＣＶＤ法によりシリコン酸化膜を堆積した後、このシリコン酸化膜を異方性エッチングし、ゲート電極４０の側壁部分に、シリコン酸化膜のサイドウォールスペーサ４４を形成する。サイドウォールスペーサ４４は、シリコン窒化膜などの他の絶縁膜により形成してもよい。   Next, after a silicon oxide film is deposited by, for example, the CVD method, the silicon oxide film is anisotropically etched to form a side wall spacer 44 of the silicon oxide film on the side wall portion of the gate electrode 40. The sidewall spacers 44 may be formed of other insulating films such as a silicon nitride film.

次いで、ゲート電極４０及びサイドウォールスペーサ４４をマスクとしてイオン注入を行い、ゲート電極４０の両側の活性領域３２a内に、Ｎ型不純物層４２とともにＮ型トランジスタのソース／ドレイン領域４８を形成するＮ型不純物層４６を形成する。この際、ソース／ドレイン領域４８の底部が素子分離絶縁膜１８に接するように形成することで、２つのＮ型トランジスタのボディ領域を分離しつつ、ソース／ドレイン領域４８の一方を短絡することができる。   Next, ion implantation is performed using the gate electrode 40 and the side wall spacer 44 as a mask to form an N-type transistor source / drain region 48 together with the N-type impurity layer 42 in the active region 32a on both sides of the gate electrode 40. Impurity layer 46 is formed. At this time, by forming the bottom of the source / drain region 48 in contact with the element isolation insulating film 18, one of the source / drain regions 48 can be short-circuited while separating the body regions of the two N-type transistors. it can.

こうして、シリコン基板１０上に、ゲート電極４０及びソース／ドレイン領域４８を有するＮ型トランジスタを形成する。   Thus, an N-type transistor having the gate electrode 40 and the source / drain region 48 is formed on the silicon substrate 10.

次いで、イオン注入により、活性領域３２ｂ内に、ボディコンタクト領域となるＰ型不純物層５０を形成する（図２０、図２１（ａ）、（ｂ））。   Next, a P-type impurity layer 50 serving as a body contact region is formed in the active region 32b by ion implantation (FIGS. 20, 21A, and 21B).

次いで、サリサイドプロセスにより、ソース／ドレイン領域４８上、ゲート電極４８上、及びＰ型不純物層５０上に、金属シリサイド膜５２を選択的に形成する（図２２（ａ）、（ｂ））。金属シリサイド膜５２の形成用の金属材料としては、例えば、チタン（Ｔｉ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）等を用いることができる。   Next, a metal silicide film 52 is selectively formed on the source / drain regions 48, the gate electrode 48, and the P-type impurity layer 50 by a salicide process (FIGS. 22A and 22B). As a metal material for forming the metal silicide film 52, for example, titanium (Ti), cobalt (Co), nickel (Ni), or the like can be used.

次いで、Ｎ型トランジスタが形成されたシリコン基板１０上に、例えばＣＶＤ法により、シリコン酸化膜等の絶縁膜を堆積し、層間絶縁膜５４を形成する。   Next, an insulating film such as a silicon oxide film is deposited on the silicon substrate 10 on which the N-type transistor is formed by, for example, a CVD method to form an interlayer insulating film 54.

次いで、例えばＣＭＰ法により、層間絶縁膜５４の表面を平坦化する。   Next, the surface of the interlayer insulating film 54 is planarized by, eg, CMP.

次いで、フォトリソグラフィ及びドライエッチングにより、層間絶縁膜５４に、コンタクトホール５６，５８を形成する。コンタクトホール５６は、ソース／ドレイン領域４８上の金属シリサイド膜５２に達するように形成される。コンタクトホール５８は、ゲート電極４８の端部からＰ型不純物層５０に至る領域に、ゲート電極４８及びＰ型不純物層５０上の金属シリサイド膜５２に達するように形成される。   Next, contact holes 56 and 58 are formed in the interlayer insulating film 54 by photolithography and dry etching. The contact hole 56 is formed so as to reach the metal silicide film 52 on the source / drain region 48. The contact hole 58 is formed in a region extending from the end of the gate electrode 48 to the P-type impurity layer 50 so as to reach the metal silicide film 52 on the gate electrode 48 and the P-type impurity layer 50.

次いで、バリアメタル及びタングステン膜を堆積後、これら導電膜をエッチバックし、コンタクトホール５６内に埋め込まれたコンタクトプラグ６０と、コンタクトホール５８内に埋め込まれたコンタクトプラグ６２とを形成する（図２３、図２４（ａ）、（ｂ））。コンタクトプラグ６２は、ゲート電極４８とＰウェル３６（ボディ領域）とを接続するためのシェアードコンタクトである。   Next, after depositing a barrier metal and a tungsten film, these conductive films are etched back to form a contact plug 60 embedded in the contact hole 56 and a contact plug 62 embedded in the contact hole 58 (FIG. 23). FIG. 24 (a), (b)). The contact plug 62 is a shared contact for connecting the gate electrode 48 and the P well 36 (body region).

この後、コンタクトプラグ６０，６２が埋め込まれた層間絶縁膜５４上に、所望の配線層を形成し、本実施形態による半導体装置を完成する。   Thereafter, a desired wiring layer is formed on the interlayer insulating film 54 in which the contact plugs 60 and 62 are embedded, and the semiconductor device according to the present embodiment is completed.

このように、本実施形態によれば、チャネル領域とボディコンタクト領域とを浅い素子分離絶縁膜によって分離するので、ソース／ドレイン領域とボディコンタクト領域のコンタクト層とが直に接することを防止することができる。また、ソース／ドレイン領域４８の底部が素子分離絶縁膜に接するようにしている。これにより、ソース／ドレイン領域とウェル及びコンタクト層との間の接合容量を大幅に低減することができ、トランジスタの高速化及び低消費電力化を図ることができる。   Thus, according to the present embodiment, the channel region and the body contact region are separated by the shallow element isolation insulating film, so that the source / drain region and the contact layer of the body contact region are prevented from being in direct contact with each other. Can do. The bottom of the source / drain region 48 is in contact with the element isolation insulating film. As a result, the junction capacitance between the source / drain region and the well and contact layer can be greatly reduced, and the speed and power consumption of the transistor can be increased.

また、ソース／ドレイン領域の一方を共用する２つのＮ型トランジスタを一の活性領域内に形成し、これらトランジスタのボディ領域をソース／ドレイン領域によって分離するので、素子の配置間隔を狭めることができ、集積度を向上することができる。   In addition, two N-type transistors sharing one of the source / drain regions are formed in one active region, and the body regions of these transistors are separated by the source / drain regions, so that the element arrangement interval can be reduced. The degree of integration can be improved.

［変形実施形態］
上記実施形態に限らず種々の変形が可能である。 [Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

例えば、上記実施形態では、Ｎ型のＤＴＭＯＳを有する半導体装置について示したが、Ｐ型のＤＴＭＯＳを有する半導体装置の場合も同様である。Ｐ型のＤＴＭＯＳでは、各層の導電型がＮ型のＤＴＭＯＳとは逆になる。   For example, in the above embodiment, a semiconductor device having an N-type DTMOS is shown, but the same applies to a semiconductor device having a P-type DTMOS. In the P-type DTMOS, the conductivity type of each layer is opposite to that of the N-type DTMOS.

また、上記実施形態では、ソース／ドレイン領域４８の一方を共用する２つのＮ型トランジスタを活性領域３２ａ内に形成したが、必ずしもソース／ドレイン領域４８を共用する必要はない。各トランジスタを、別々の活性領域３２ａ内に形成するようにしてもよい。   In the above embodiment, two N-type transistors sharing one of the source / drain regions 48 are formed in the active region 32a. However, the source / drain regions 48 are not necessarily shared. Each transistor may be formed in a separate active region 32a.

この場合、２つのトランジスタ形成領域は、例えば図２５に示すように、素子分離絶縁膜３２によって分離する。ソース／ドレイン領域４８は、必ずしも素子分離絶縁膜１８に接している必要はない。   In this case, the two transistor formation regions are separated by an element isolation insulating film 32, for example, as shown in FIG. The source / drain region 48 is not necessarily in contact with the element isolation insulating film 18.

なお、図２５は、Ｎ型ＤＴＭＯＳとＰ型ＤＴＭＯＳとを隣接して形成した場合の例である。Ｐ型ＤＴＭＯＳは、例えば、Ｐウェル７０と、Ｎウェル７２と、Ｐ型のソース／ドレイン領域７４により形成する。Ｐ型ＤＴＭＯＳのゲート電極４８は、例えばＰ＋型の多結晶シリコンにより形成する。   FIG. 25 shows an example in which an N-type DTMOS and a P-type DTMOS are formed adjacent to each other. The P type DTMOS is formed by, for example, a P well 70, an N well 72, and a P type source / drain region 74. The gate electrode 48 of the P-type DTMOS is formed of, for example, P + type polycrystalline silicon.

また、上記実施形態では、２つのトランジスタを隣接して形成したが、必ずしも２つのトランジスタを隣接して形成する必要はない。１つのトランジスタだけを形成するようにしてもよいし、３つ以上のトランジスタを隣接して形成するようにしてもよい。   In the above embodiment, two transistors are formed adjacent to each other. However, the two transistors are not necessarily formed adjacent to each other. Only one transistor may be formed, or three or more transistors may be formed adjacent to each other.

また、上記実施形態では、ソース／ドレイン領域４８の表面部に金属シリサイド膜５２を形成したが、ソース／ドレイン領域４８の素子分離絶縁膜１８に接する領域までをシリサイド化するようにしてもよい。   In the above embodiment, the metal silicide film 52 is formed on the surface portion of the source / drain region 48. However, the region of the source / drain region 48 in contact with the element isolation insulating film 18 may be silicided.

本実施形態による半導体装置では、ソース／ドレイン領域４８を多結晶シリコン膜２４内に形成するため、単結晶シリコン内に形成する場合と比較して抵抗値が高くなる。ソース／ドレイン領域４８を底部までシリサイド化することにより、多結晶シリコン膜２４を用いることによる抵抗増加を補償することができる。   In the semiconductor device according to the present embodiment, since the source / drain region 48 is formed in the polycrystalline silicon film 24, the resistance value is higher than that in the case of forming it in single crystal silicon. By siliciding the source / drain region 48 to the bottom, an increase in resistance due to the use of the polycrystalline silicon film 24 can be compensated.

また、上記実施形態では、二重ウェルを形成して各トランジスタのボディ領域を分離したが、ＳＯＩ基板上に形成する場合など、他の分離手段を有している場合には必ずしも二重ウェル内に形成する必要はない。   Further, in the above embodiment, the double well is formed to separate the body regions of the transistors. However, in the case of having another separation means such as when formed on the SOI substrate, the double well is not necessarily within the double well. There is no need to form.

また、上記実施形態に記載した半導体装置の構造、構成材料、製造条件等は、一例を示したものにすぎず、当業者の技術常識等に応じて適宜修正や変更が可能である。   In addition, the structure, constituent materials, manufacturing conditions, and the like of the semiconductor device described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

以上の実施形態に関し、更に以下の付記を開示する。   Regarding the above embodiment, the following additional notes are disclosed.

（付記１） 半導体基板に第１の領域を画定する第１の素子分離絶縁膜と、
前記半導体基板の前記第１の領域に形成された第１導電型の第１の導電層と、
前記半導体基板上に形成され、前記第１の領域の一部である第２の領域に前記第１の導電層に接続して形成された前記第１導電型の第２の導電層と、前記第１の領域の他の一部である第３の領域に前記第１の導電層に接続して形成された前記第１導電型の第３の導電層とを有する半導体層と、
前記半導体層内に設けられ、前記第２の導電層と前記第３の導電層とを分離する第２の素子分離絶縁膜と、
前記第２の導電層上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成され、前記第３の導電層を介して前記第１の導電層に電気的に接続されたゲート電極と
を有することを特徴とする半導体装置。 (Supplementary note 1) a first element isolation insulating film that defines a first region in a semiconductor substrate;
A first conductive layer of a first conductivity type formed in the first region of the semiconductor substrate;
A second conductive layer of the first conductivity type formed on the semiconductor substrate and connected to the first conductive layer in a second region which is a part of the first region; A semiconductor layer having a third conductive layer of the first conductivity type formed in a third region that is another part of the first region and connected to the first conductive layer;
A second element isolation insulating film provided in the semiconductor layer and separating the second conductive layer and the third conductive layer;
A gate insulating film formed on the second conductive layer;
A semiconductor device comprising: a gate electrode formed on the gate insulating film and electrically connected to the first conductive layer through the third conductive layer.

（付記２） 付記１記載の半導体装置において、
前記半導体層は、前記第２の導電層を挟むように配置され、底部が前記第１の素子分離絶縁膜に接する第２導電型のソース／ドレイン領域を更に有する
ことを特徴とする半導体装置。 (Appendix 2) In the semiconductor device according to Appendix 1,
The semiconductor device further includes a second conductivity type source / drain region disposed so as to sandwich the second conductive layer and having a bottom portion in contact with the first element isolation insulating film.

（付記３） 付記２記載の半導体装置において、
前記半導体層は、単結晶半導体領域と、多結晶半導体領域とを有し、前記ソース／ドレイン領域は、多結晶半導体領域に形成されている
ことを特徴とする半導体装置。 (Appendix 3) In the semiconductor device described in Appendix 2,
The semiconductor layer includes a single crystal semiconductor region and a polycrystalline semiconductor region, and the source / drain regions are formed in the polycrystalline semiconductor region.

（付記４） 付記１乃至３のいずれか１項に記載の半導体装置において、
前記半導体層及び前記第２の素子分離絶縁膜の表面は、平坦化されている
ことを特徴とする半導体装置。 (Appendix 4) In the semiconductor device according to any one of appendices 1 to 3,
Surfaces of the semiconductor layer and the second element isolation insulating film are planarized. A semiconductor device, wherein:

（付記５） 付記１乃至４のいずれか１項に記載の半導体装置において、
前記第１の導電層は、前記第１の素子分離絶縁膜の底部より浅い
ことを特徴とする半導体装置。 (Appendix 5) In the semiconductor device according to any one of appendices 1 to 4,
The semiconductor device, wherein the first conductive layer is shallower than a bottom of the first element isolation insulating film.

（付記６） 付記１乃至５のいずれか１項に記載の半導体装置において、
前記第１の導電層下の前記半導体基板内に形成され、前記第１の素子分離絶縁膜の底部よりも深い第４の導電層を更に有する
ことを特徴とする半導体装置。 (Appendix 6) In the semiconductor device according to any one of appendices 1 to 5,
A semiconductor device, further comprising a fourth conductive layer formed in the semiconductor substrate under the first conductive layer and deeper than a bottom of the first element isolation insulating film.

（付記７） 半導体基板に第１の領域及び第２の領域を画定する第１の素子分離絶縁膜と、
前記半導体基板の前記第１の領域に形成され、前記第１の素子分離絶縁膜の底部よりも浅い第１導電型の第１の導電層と、
前記半導体基板の前記第２の領域に形成され、前記第１の素子分離絶縁膜の底部よりも浅い前記第１導電型の第２の導電層と、
前記第１の導電層及び前記第２の導電層下の前記半導体基板内に形成され、前記第１の素子分離絶縁膜の底部よりも深い第２導電型の第３の導電層と、
前記半導体基板上に形成され、前記第１の領域の一部である第３の領域に前記第１の導電層に接続して形成された前記第１導電型の第４の導電層と、前記第２の領域の一部である第４の領域に前記第１の導電層に接続して形成された前記第１導電型の第５の導電層と、前記第１の領域の他の一部である第５の領域に前記第１の導電層に接続して形成された前記第１導電型の第６の導電層と、前記第２の領域の他の一部である第６の領域に前記第１の導電層に接続して形成された前記第１導電型の第７の導電層と、前記第３の領域と前記第４の領域との間の第７の領域に前記第１の素子分離絶縁膜に接して形成された前記第２導電型の第８の導電層とを有する半導体層と、
前記半導体層内に形成され、前記第２の導電層、前記第３導電層及び前記第６の導電層と前記４の導電層とを分離し、前記第２の導電層、前記第３導電層及び前記第６の導電層と前記第５の導電層とを分離する第２の素子分離絶縁膜と、
前記第２の導電層上に形成された第１のゲート絶縁膜と、
前記第３の導電層上に形成された第２のゲート絶縁膜と、
前記第１のゲート絶縁膜上に形成され、前記第４の導電層を介して前記第１の導電層に電気的に接続された第１のゲート電極と、
前記第２のゲート絶縁膜上に形成され、前記第５の導電層を介して前記第２の導電層に電気的に接続された第２のゲート電極と
を有することを特徴とする半導体装置。 (Supplementary note 7) a first element isolation insulating film that defines a first region and a second region in a semiconductor substrate;
A first conductive layer of a first conductivity type formed in the first region of the semiconductor substrate and shallower than a bottom of the first element isolation insulating film;
A second conductive layer of the first conductivity type formed in the second region of the semiconductor substrate and shallower than a bottom of the first element isolation insulating film;
A third conductive layer of a second conductivity type formed in the semiconductor substrate under the first conductive layer and the second conductive layer and deeper than a bottom of the first element isolation insulating film;
A fourth conductive layer of the first conductivity type formed on the semiconductor substrate and connected to the first conductive layer in a third region which is a part of the first region; A fifth conductive layer of the first conductivity type formed in a fourth region which is a part of the second region and connected to the first conductive layer; and another part of the first region A sixth conductive layer of the first conductivity type formed in a fifth region connected to the first conductive layer and a sixth region which is another part of the second region. A first conductive type seventh conductive layer formed in connection with the first conductive layer; and a seventh region between the third region and the fourth region. A semiconductor layer having the second conductive type eighth conductive layer formed in contact with the element isolation insulating film;
Formed in the semiconductor layer, separating the second conductive layer, the third conductive layer, the sixth conductive layer, and the fourth conductive layer; and the second conductive layer and the third conductive layer. And a second element isolation insulating film that separates the sixth conductive layer and the fifth conductive layer;
A first gate insulating film formed on the second conductive layer;
A second gate insulating film formed on the third conductive layer;
A first gate electrode formed on the first gate insulating film and electrically connected to the first conductive layer via the fourth conductive layer;
And a second gate electrode formed on the second gate insulating film and electrically connected to the second conductive layer through the fifth conductive layer.

（付記８） 付記７記載の半導体装置において、
前記半導体層は、単結晶半導体領域と、多結晶半導体領域とを有し、前記第８の導電層は、多結晶半導体領域に形成されている
ことを特徴とする半導体装置。 (Supplementary note 8) In the semiconductor device according to supplementary note 7,
The semiconductor device has a single crystal semiconductor region and a polycrystalline semiconductor region, and the eighth conductive layer is formed in the polycrystalline semiconductor region.

（付記９） 付記７又は８記載の半導体装置において、
前記半導体層及び前記第２の素子分離絶縁膜の表面は、平坦化されている
ことを特徴とする半導体装置。 (Appendix 9) In the semiconductor device according to Appendix 7 or 8,
Surfaces of the semiconductor layer and the second element isolation insulating film are planarized. A semiconductor device, wherein:

（付記１０） 半導体基板に、第１の領域を画定する第１の素子分離絶縁膜を形成する工程と、
前記第１の素子分離絶縁膜が形成された前記半導体基板上に、半導体層を形成する工程と、
前記半導体層に、前記第１の領域の一部の領域を含む第２の領域と、前記第１の領域の他の一部の領域を含む第３の領域を画定する第２の素子分離絶縁膜を形成する工程と、
前記半導体基板及び前記半導体層に、前記第２の素子絶縁膜の底部よりも深く、前記第１の素子分離絶縁膜の底部よりも浅い第１導電型の第１のウェルを形成する工程と、
前記半導体層の前記第２の領域上に、ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に、前記半導体層の前記第３の領域を介して前記第１のウェルに電気的に接続されたゲート電極を形成する工程と
を有することを特徴とする半導体装置の製造方法。 (Additional remark 10) The process of forming the 1st element isolation insulating film which defines a 1st area | region in a semiconductor substrate,
Forming a semiconductor layer on the semiconductor substrate on which the first element isolation insulating film is formed;
A second element isolation insulation that defines a second region including a partial region of the first region and a third region including another partial region of the first region in the semiconductor layer. Forming a film;
Forming a first well of the first conductivity type in the semiconductor substrate and the semiconductor layer, which is deeper than the bottom of the second element insulating film and shallower than the bottom of the first element isolation insulating film;
Forming a gate insulating film on the second region of the semiconductor layer;
Forming a gate electrode electrically connected to the first well through the third region of the semiconductor layer on the gate insulating film. .

（付記１１） 付記１０記載の半導体装置の製造方法において、
前記第２の素子分離絶縁膜を形成する工程の後、前記半導体基板に、前記第１の素子分離絶縁膜の底部よりも深い第２導電型の第２のウェルを形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。 (Additional remark 11) In the manufacturing method of the semiconductor device of Additional remark 10,
After the step of forming the second element isolation insulating film, the method further includes the step of forming a second well of the second conductivity type deeper than the bottom of the first element isolation insulating film on the semiconductor substrate. A method of manufacturing a semiconductor device.

（付記１２） 付記１０又は１１記載の半導体装置の製造方法において、
前記ゲート電極を形成する工程の後、前記半導体層の前記第２の領域に、底部が前記第１の素子分離絶縁膜に接する前記第２導電型のソース／ドレイン領域を形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。 (Additional remark 12) In the manufacturing method of the semiconductor device of Additional remark 10 or 11,
After the step of forming the gate electrode, the method further includes the step of forming the second conductivity type source / drain region whose bottom is in contact with the first element isolation insulating film in the second region of the semiconductor layer. A method for manufacturing a semiconductor device.

（付記１３） 付記１２記載の半導体装置の製造方法において、
前記第２の領域は、前記第１の素子分離絶縁膜上に位置し、前記第１の領域の前記一部の領域を挟むように配置された第４の領域及び第５の領域を含み、
前記ソース／ドレイン領域を形成する領域では、前記第４の領域及び前記第５の領域に前記ソース／ドレイン領域を形成する
ことを特徴とする半導体装置の製造方法。 (Additional remark 13) In the manufacturing method of the semiconductor device of Additional remark 12,
The second region includes a fourth region and a fifth region that are located on the first element isolation insulating film and are disposed so as to sandwich the partial region of the first region,
In the region for forming the source / drain region, the source / drain region is formed in the fourth region and the fifth region.

（付記１４） 付記１０乃至１３のいずれか１項に記載の半導体装置の製造方法において、
前記半導体層を形成する工程では、前記第１の領域上に単結晶半導体層を成長し、前記第１の素子分離絶縁膜上に多結晶半導体層を成長する
ことを特徴とする半導体装置の製造方法。 (Appendix 14) In the method for manufacturing a semiconductor device according to any one of appendices 10 to 13,
In the step of forming the semiconductor layer, a single crystal semiconductor layer is grown on the first region, and a polycrystalline semiconductor layer is grown on the first element isolation insulating film. Method.

（付記１５） 付記１０乃至１４のいずれか１項に記載の半導体装置の製造方法において、
前記第２の素子分離絶縁膜を形成する工程では、前記半導体層及び前記第２の素子分離絶縁膜の表面が平坦になるように、前記第２の素子分離絶縁膜を形成する
ことを特徴とする半導体装置の製造方法。 (Supplementary note 15) In the method for manufacturing a semiconductor device according to any one of supplementary notes 10 to 14,
In the step of forming the second element isolation insulating film, the second element isolation insulating film is formed so that the surfaces of the semiconductor layer and the second element isolation insulating film become flat. A method for manufacturing a semiconductor device.

１０…シリコン基板
１２…シリコン酸化膜
１４，２６…シリコン窒化膜
１６，３０…素子分離溝
１８，３２…素子分離絶縁膜
２０，３２ａ，３２ｂ…活性領域
２２…単結晶シリコン膜
２４…多結晶シリコン膜
２８…フォトレジスト膜
３４…Ｎウェル
３６…Ｐウェル
３８…ゲート絶縁膜
４０…ゲート電極
４２，４６…Ｎ型不純物層
４４…サイドウォールスペーサ
４８…ソース／ドレイン領域
５０…Ｐ型不純物層
５２…金属シリサイド膜
５４…層間絶縁膜
５６，５８…コンタクトホール
６０，６２…コンタクトプラグ DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12 ... Silicon oxide film 14, 26 ... Silicon nitride film 16, 30 ... Element isolation groove 18, 32 ... Element isolation insulating film 20, 32a, 32b ... Active region 22 ... Single crystal silicon film 24 ... Polycrystalline silicon Film 28 ... Photoresist film 34 ... N well 36 ... P well 38 ... Gate insulating film 40 ... Gate electrodes 42, 46 ... N-type impurity layer 44 ... Side wall spacer 48 ... Source / drain region 50 ... P-type impurity layer 52 ... Metal silicide film 54 ... interlayer insulating films 56 and 58 ... contact holes 60 and 62 ... contact plugs

Claims (10)

半導体基板に第１の領域を画定する第１の素子分離絶縁膜と、
前記半導体基板の前記第１の領域に形成された第１導電型の第１の導電層と、
前記半導体基板上に形成され、前記第１の領域の一部である第２の領域に前記第１の導電層に接続して形成された前記第１導電型の第２の導電層と、前記第１の領域の他の一部である第３の領域に前記第１の導電層に接続して形成された前記第１導電型の第３の導電層とを有する半導体層と、
前記半導体層内に設けられ、前記第２の導電層と前記第３の導電層とを分離する第２の素子分離絶縁膜と、
前記第２の導電層上に形成されたゲート絶縁膜と、
前記ゲート絶縁膜上に形成され、前記第３の導電層を介して前記第１の導電層に電気的に接続されたゲート電極と
を有することを特徴とする半導体装置。 A first element isolation insulating film defining a first region in the semiconductor substrate;
A first conductive layer of a first conductivity type formed in the first region of the semiconductor substrate;
A second conductive layer of the first conductivity type formed on the semiconductor substrate and connected to the first conductive layer in a second region which is a part of the first region; A semiconductor layer having a third conductive layer of the first conductivity type formed in a third region that is another part of the first region and connected to the first conductive layer;
A second element isolation insulating film provided in the semiconductor layer and separating the second conductive layer and the third conductive layer;
A gate insulating film formed on the second conductive layer;
A semiconductor device comprising: a gate electrode formed on the gate insulating film and electrically connected to the first conductive layer through the third conductive layer. 請求項１記載の半導体装置において、
前記半導体層は、前記第２の導電層を挟むように配置され、底部が前記第１の素子分離絶縁膜に接する第２導電型のソース／ドレイン領域を更に有する
ことを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device further includes a second conductivity type source / drain region disposed so as to sandwich the second conductive layer and having a bottom portion in contact with the first element isolation insulating film. 請求項１又は２記載の半導体装置において、
前記半導体層及び前記第２の素子分離絶縁膜の表面は、平坦化されている
ことを特徴とする半導体装置。 The semiconductor device according to claim 1 or 2,
Surfaces of the semiconductor layer and the second element isolation insulating film are planarized. A semiconductor device, wherein: 請求項１乃至３のいずれか１項に記載の半導体装置において、
前記第１の導電層は、前記第１の素子分離絶縁膜の底部より浅い
ことを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the first conductive layer is shallower than a bottom of the first element isolation insulating film. 請求項１乃至４のいずれか１項に記載の半導体装置において、
前記第１の導電層下の前記半導体基板内に形成され、前記第１の素子分離絶縁膜の底部よりも深い第４の導電層を更に有する
ことを特徴とする半導体装置。 The semiconductor device according to any one of claims 1 to 4,
A semiconductor device, further comprising a fourth conductive layer formed in the semiconductor substrate under the first conductive layer and deeper than a bottom of the first element isolation insulating film. 半導体基板に第１の領域及び第２の領域を画定する第１の素子分離絶縁膜と、
前記半導体基板の前記第１の領域に形成され、前記第１の素子分離絶縁膜の底部よりも浅い第１導電型の第１の導電層と、
前記半導体基板の前記第２の領域に形成され、前記第１の素子分離絶縁膜の底部よりも浅い前記第１導電型の第２の導電層と、
前記第１の導電層及び前記第２の導電層下の前記半導体基板内に形成され、前記第１の素子分離絶縁膜の底部よりも深い第２導電型の第３の導電層と、
前記半導体基板上に形成され、前記第１の領域の一部である第３の領域に前記第１の導電層に接続して形成された前記第１導電型の第４の導電層と、前記第２の領域の一部である第４の領域に前記第１の導電層に接続して形成された前記第１導電型の第５の導電層と、前記第１の領域の他の一部である第５の領域に前記第１の導電層に接続して形成された前記第１導電型の第６の導電層と、前記第２の領域の他の一部である第６の領域に前記第１の導電層に接続して形成された前記第１導電型の第７の導電層と、前記第３の領域と前記第４の領域との間の第７の領域に前記第１の素子分離絶縁膜に接して形成された前記第２導電型の第８の導電層とを有する半導体層と、
前記半導体層内に形成され、前記第２の導電層、前記第３導電層及び前記第６の導電層と前記４の導電層とを分離し、前記第２の導電層、前記第３導電層及び前記第６の導電層と前記第５の導電層とを分離する第２の素子分離絶縁膜と、
前記第２の導電層上に形成された第１のゲート絶縁膜と、
前記第３の導電層上に形成された第２のゲート絶縁膜と、
前記第１のゲート絶縁膜上に形成され、前記第４の導電層を介して前記第１の導電層に電気的に接続された第１のゲート電極と、
前記第２のゲート絶縁膜上に形成され、前記第５の導電層を介して前記第２の導電層に電気的に接続された第２のゲート電極と
を有することを特徴とする半導体装置。 A first element isolation insulating film defining a first region and a second region in a semiconductor substrate;
A first conductive layer of a first conductivity type formed in the first region of the semiconductor substrate and shallower than a bottom of the first element isolation insulating film;
A second conductive layer of the first conductivity type formed in the second region of the semiconductor substrate and shallower than a bottom of the first element isolation insulating film;
A third conductive layer of a second conductivity type formed in the semiconductor substrate under the first conductive layer and the second conductive layer and deeper than a bottom of the first element isolation insulating film;
A fourth conductive layer of the first conductivity type formed on the semiconductor substrate and connected to the first conductive layer in a third region which is a part of the first region; A fifth conductive layer of the first conductivity type formed in a fourth region which is a part of the second region and connected to the first conductive layer; and another part of the first region A sixth conductive layer of the first conductivity type formed in a fifth region connected to the first conductive layer and a sixth region which is another part of the second region. A first conductive type seventh conductive layer formed in connection with the first conductive layer; and a seventh region between the third region and the fourth region. A semiconductor layer having the second conductive type eighth conductive layer formed in contact with the element isolation insulating film;
Formed in the semiconductor layer, separating the second conductive layer, the third conductive layer, the sixth conductive layer, and the fourth conductive layer; and the second conductive layer and the third conductive layer. And a second element isolation insulating film that separates the sixth conductive layer and the fifth conductive layer;
A first gate insulating film formed on the second conductive layer;
A second gate insulating film formed on the third conductive layer;
A first gate electrode formed on the first gate insulating film and electrically connected to the first conductive layer via the fourth conductive layer;
And a second gate electrode formed on the second gate insulating film and electrically connected to the second conductive layer through the fifth conductive layer. 半導体基板に、第１の領域を画定する第１の素子分離絶縁膜を形成する工程と、
前記第１の素子分離絶縁膜が形成された前記半導体基板上に、半導体層を形成する工程と、
前記半導体層に、前記第１の領域の一部の領域を含む第２の領域と、前記第１の領域の他の一部の領域を含む第３の領域を画定する第２の素子分離絶縁膜を形成する工程と、
前記半導体基板及び前記半導体層に、前記第２の素子絶縁膜の底部よりも深く、前記第１の素子分離絶縁膜の底部よりも浅い第１導電型の第１のウェルを形成する工程と、
前記半導体層の前記第２の領域上に、ゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜上に、前記半導体層の前記第３の領域を介して前記第１のウェルに電気的に接続されたゲート電極を形成する工程と
を有することを特徴とする半導体装置の製造方法。 Forming a first element isolation insulating film for defining a first region on a semiconductor substrate;
Forming a semiconductor layer on the semiconductor substrate on which the first element isolation insulating film is formed;
A second element isolation insulation that defines a second region including a partial region of the first region and a third region including another partial region of the first region in the semiconductor layer. Forming a film;
Forming a first well of the first conductivity type in the semiconductor substrate and the semiconductor layer, which is deeper than the bottom of the second element insulating film and shallower than the bottom of the first element isolation insulating film;
Forming a gate insulating film on the second region of the semiconductor layer;
Forming a gate electrode electrically connected to the first well through the third region of the semiconductor layer on the gate insulating film. . 請求項７記載の半導体装置の製造方法において、
前記第２の素子分離絶縁膜を形成する工程の後、前記半導体基板に、前記第１の素子分離絶縁膜の底部よりも深い第２導電型の第２のウェルを形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 7.
After the step of forming the second element isolation insulating film, the method further includes the step of forming a second well of the second conductivity type deeper than the bottom of the first element isolation insulating film on the semiconductor substrate. A method of manufacturing a semiconductor device. 請求項７又は８記載の半導体装置の製造方法において、
前記ゲート電極を形成する工程の後、前記半導体層の前記第２の領域に、底部が前記第１の素子分離絶縁膜に接する前記第２導電型のソース／ドレイン領域を形成する工程を更に有する
ことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 7 or 8,
After the step of forming the gate electrode, the method further includes the step of forming the second conductivity type source / drain region whose bottom is in contact with the first element isolation insulating film in the second region of the semiconductor layer. A method for manufacturing a semiconductor device. 請求項７乃至９のいずれか１項に記載の半導体装置の製造方法において、
前記第２の素子分離絶縁膜を形成する工程では、前記半導体層及び前記第２の素子分離絶縁膜の表面が平坦になるように、前記第２の素子分離絶縁膜を形成する
ことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to any one of claims 7 to 9,
In the step of forming the second element isolation insulating film, the second element isolation insulating film is formed so that the surfaces of the semiconductor layer and the second element isolation insulating film become flat. A method for manufacturing a semiconductor device.
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