JPH11260829A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent lowering of operation velocity due to low impurity concentration of an emitter, by implanting ion to a proper region of a low impurity concentration layer in a lower side of a p-type single crystalline SiGe base layer, and adding n-type impurities to make n-type impurity concentration there specified times that in a p-type single crystalline SiGe base layer. SOLUTION: An n-type single crystalline Si layer 11b is an intrinsic collector formed by ion implantation. N-type single crystalline and single crystalline SiGe layer is an intrinsic emitter formed by ion implantation. A p-type single crystalline SiGe layer 13 is a base layer. N-type impurities are added so that n-type impurity concentration in an interface of an n-type single crystalline Si layer/a single crystalline SiGe layer near an emitter base junction is at least one and half times that in an interface of the n type single crystalline Si layer 11b/the single crystalline SiGe layer 13 at a base-collector junction side. Implantation of hole from a base to an emitter is restrained by raising impurity concentration of an emitter in this way. As a result, operation velocity can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device including a bipolar transistor having a SiGe base layer and a method of manufacturing the same, and more particularly to a semiconductor device suitable for a microwave or millimeter wave IC.

[0002]

2. Description of the Related Art To increase the gain of a microwave or millimeter wave amplifier, a collector-top type bipolar transistor which is less affected by parasitic elements is effective. When integrating a high-gain amplifier and other high-speed operation circuits, it is necessary to form a collector-top bipolar transistor for the high-gain amplifier and an emitter-top bipolar transistor for the high-speed operation circuit on the same substrate. Here, the collector top type bipolar transistor refers to a transistor in which a collector region, a base region, and an emitter region are sequentially arranged from a surface side of a substrate toward a depth direction thereof. In addition, the emitter top type bipolar transistor is, from the surface side of the substrate to the depth direction,
It means that an emitter region, a base region, and a collector region are sequentially arranged.

[0003] Regarding the prior art related to the present invention, see IE Electron Device Letter Vol. 19, No. 9 (1994) (IEEE Electron).
Device Letter Vol.19, No.9 pp.360-
362 (1994)).
An iGe (silicon-germanium) base bipolar transistor will be described with reference to FIGS.

FIG. 17 shows a longitudinal sectional structure of a main part of a conventional SiGe-based bipolar transistor. In this figure, reference numeral 2 denotes an n + type Si layer, and 3 denotes a low concentration n layer.
Type silicon (Si) layer, 5 is a SiO ₂ film as an insulating film, 6 is a Si ₃ N ₄ film as an insulating film, 8 is a p-type polycrystalline Si film, 10
Is a SiO ₂ film, 12 is a non-doped single crystal SiGe film, 13
Is a p-type single crystal SiGe film, and 14a is a non-doped single crystal S
i layer, 14b a non-doped single crystal SiGe layer, 17 an n +
Type Si layer, 18 is a SiO ₂ film, 19 is a Si ₃ N ₄ film, 20 is an n-type polycrystalline Si film, 25a is an n-type Si layer formed by ion implantation, and 25b is an n-type SiGe layer formed by ion implantation. And 26 are n-type Si layers formed by ion implantation. This transistor can be operated in both a collector top type and an emitter top type. The n-type Si layer 26 is an intrinsic emitter or intrinsic collector, the p-type single crystal SiGe film 13 is a base, and the n-type Si layer 2 is
5a and the n-type SiGe layer 25b are an intrinsic collector or an intrinsic emitter.

FIG. 18 shows an intrinsic region of the transistor shown in FIG.
The vertical distribution of the impurity concentration in (broken line A portion in the figure) is shown. The n-type impurity concentration at the SiGe layer / single-crystal Si layer interface (points Y and X in FIG. 18) on both sides (upper and lower sides) of the SiGe base layer is about 4 × 10 ¹⁷ [atoms].
/ Cm ³ ].

[0006]

Normally, the n-type impurity concentration of the collector at the base-collector junction of a bipolar transistor is 5 × 10 ¹⁷ [atoms] in order to secure the breakdown voltage between the base and the collector and between the emitter and the collector.
/ Cm ³ ] or less. The conventional bipolar transistors shown in FIGS. 17 and 18 can operate in both the collector-top type and the emitter-top type. In this case, the interface between the SiGe layer / single-crystal Si layer on both sides (upper and lower sides) of the p-type SiGe base layer is ensured so that the breakdown voltage between the base and the collector and between the emitter and the collector can be ensured in both operation directions. The n-type impurity concentration is approximately the same as about 4 × 10 ¹⁷ [atoms / cm ³ ] and low.

However, in this conventional bipolar transistor, the n-type impurity concentration at the emitter-base junction is about 4 × 10 ¹⁷ [atoms / c] in either operation direction.
m ³ ]. As a result, there is a problem that the amount of holes injected from the base into the emitter increases in both operation directions, and the operation speed decreases.

In particular, in the collector top type, the emitter-base junction area is several times larger than the intrinsic region area (operating region surface) of the transistor, and the area other than the intrinsic region of the emitter-base junction (other than the operating region). Since the emitter is non-doped in the portion, the amount of holes injected from the base to the emitter becomes very large, and there is a problem that the operation speed is greatly reduced.

That is, the maximum cutoff frequency of the conventional transistor is 64 [GHz] for the emitter top type, and 14 [GHz] for the collector top type.

An object of the present invention is to reduce the operating speed of a collector-top type and emitter-top type SiGe base bipolar transistor formed on the same substrate due to a low concentration of an emitter by reducing the number of steps and the process time. To prevent without significantly increasing.
It is another object of the present invention to prevent the side effect of lowering the withstand voltage from being caused by improving the operation speed.

In the conventional bipolar transistor shown in FIG. 17, the boundary between the p-type polycrystalline Si film 8 and the non-doped single-crystal Si layer 14a has a low impurity concentration.
Therefore, when used as a collector top type, when a reverse bias is applied between the base and the collector, the boundary is depleted, and as a result, there is a problem that a leak current occurs between the base and the collector. It is also an object of the present invention to suppress this leakage current.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In the collector top type transistor and the emitter top type transistor, each of the emitter
Except for the step of adjusting the n-type impurity concentration of the base junction, transistors having a common structure are formed in common steps. That is, the p-type single-crystal SiGe base layers in the collector-top transistor and the emitter-top transistor and the low impurity concentration layers on both sides (upper and lower sides) are formed in the same process by the epitaxial growth method.

In order to increase the concentration of the n-type impurity at the emitter-base junction, the n-type impurity is separately implanted into the collector-top transistor and the emitter-top transistor by ion implantation so that both sides (upper and lower) of the p-type single-crystal SiGe base layer are formed. This is performed by implanting into the lower impurity concentration layer (lower side). That is, in the collector top type transistor, p
An n-type impurity is added to an appropriate region of the low-impurity-concentration layer below the single-crystal SiGe base layer by ion implantation so as to be at least 1.5 times as high as the upper side of the p-type single-crystal SiGe base layer. However, this ion implantation may be performed before the formation of the p-type single crystal SiGe base layer by epitaxial growth. In the emitter top type transistor, an n-type impurity is implanted into an appropriate region of the low impurity concentration layer above the p-type single crystal SiGe base layer by at least 1.5 times the lower side of the p-type single crystal SiGe base layer. Add so that

According to the above method, the n-type impurity concentration at the emitter-base junction can be 1.5 times or more the concentration at the base-collector junction for both the collector-top transistor and the emitter-top transistor.
As a result, in both the collector-top transistor and the emitter-top transistor, the injection of holes from the base to the emitter can be reduced, and the operation speed can be greatly improved. According to this method, the n-type impurity concentration of the collector is kept low in both the emitter top type and the collector top type, so that there is no problem of reduction in the withstand voltage of the transistor. Further, according to this method, only the number of steps of selective ion implantation is increased as compared with the conventional transistor, so that the number of steps and the processing time are not significantly increased.

The leakage current between the base and the collector when a conventional bipolar transistor is used as a collector top type is suppressed by the following means. That is, the structure is such that the p-type polycrystalline Si film and the non-doped single-crystal Si layer are separated by the insulating film and the p-type single-crystal SiGe film and are not in direct contact with each other.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention, showing a longitudinal sectional structure of a collector top type and emitter top type SiGe base bipolar transistor formed on the same substrate.

In this figure, reference numeral 1 denotes a p-type Si substrate, 2
Is an n + type Si layer, 3 is a low concentration n-type silicon (Si) layer, 4 is
n + type Si layer, 5 is an SiO ₂ film as an insulating film, 6 is a Si ₃ N ₄ film as an insulating film, 7 is a SiO ₂ film as an insulating film, 8 is a p-type polycrystalline Si film, 9 is an n-type Polycrystalline Si film, 10 is SiO
₂ films, 11a and 11b are n-type Si layers formed by ion implantation, 12 is a non-doped single crystal SiGe layer, 13
Is a p-type single crystal SiGe layer, 14 is a non-doped single crystal Si
/ Single-crystal SiGe layer, 15 is an n-type single-crystal Si / single-crystal SiGe layer formed by ion implantation, 16, 16a
Is an n-type single-crystal Si / single-crystal SiGe layer formed by ion implantation, 17 is an n + -type Si layer, 18 is a SiO ₂ film, 1
9 is an Si ₃ N ₄ film, 20 is an n + type polycrystalline Si film, 21 is Si
The O ₂ films 22, 23 and 24 are metal films.

Of the two transistors, the left side is a collector top type and the right side is an emitter top type. In both transistors, 22 is an emitter electrode, 23 is a base electrode, and 24 is a collector electrode. N + type Si layer 2 and n + type Si for extracting the emitter of the collector top type transistor or the emitter top type collector
Layer 4, n + type S for extracting collector or emitter top type emitter of collector top type transistor
The i-layer 17 and the n + -type polycrystalline Si film 20, the p-type single-crystal SiGe layer 13, which is the base layer of both types of transistors, and most of the parasitic regions of the transistors are formed in a process common to both types of transistors. .

FIG. 2 shows a detailed longitudinal sectional structure of a main part of the collector top type bipolar transistor in FIG. The reference numerals in FIG. 1 included in FIG. 1 indicate the same components as those in FIG. 14a is a non-doped single-crystal Si layer, and 14b is a non-doped single-crystal Si layer.
A Ge layer, 15a is an n-type single-crystal Si layer formed by ion implantation, and 15b and 16c are n-type single-crystal SiGe layers formed by ion implantation. 15a and 15b
-Type single-crystal Si / single-crystal SiG by ion implantation
The e layer is an intrinsic emitter, the n-type single-crystal Si / single-crystal SiGe layer by ion implantation of 16a and 16c is an intrinsic collector, and the p-type single-crystal SiGe layer 13 is a base layer. 2 is an n + type Si layer for extracting an emitter, 8 is a p-type polycrystalline Si film for extracting a base, 17 is an n + type Si layer for extracting an emitter, and 20 is an n-type polycrystalline Si for extracting a collector. It is a membrane.

FIG. 3 shows the vertical distribution of the n-type impurity concentration, the p-type impurity concentration and the Ge concentration in the portion indicated by the broken line A which is the intrinsic region of the collector top type bipolar transistor in FIG. 5 is a graph showing a vertical distribution of a mold impurity concentration. In the intrinsic portion of the broken line A, the n-type impurity concentration near the emitter-base junction, that is, at the interface between the n-type single-crystal Si layer and the single-crystal SiGe layer (point X in FIG. 3) is 1 × 10 ¹⁸ atoms / cm ³ ], and an n-type single-crystal Si layer / single-crystal SiG on the base-collector junction side.
1 × 10 ¹⁷ [atoms / cm ³ ] at the interface of the e-layer (point Y in FIG. 3)
It is one order of magnitude larger than. The n-type impurity concentration in the vicinity of the emitter-base junction in the portion indicated by the broken line B, that is, at the interface between the n-type single-crystal Si layer and the single-crystal SiGe layer is 1 × 10
¹⁷ [atoms / cm ³ ].

FIG. 4 shows a detailed longitudinal sectional structure of a main part of the emitter top type bipolar transistor in FIG. Each reference numeral in the figure indicates the same one as in FIGS. N by ion implantation of 11b
The type single-crystal Si layer is an intrinsic collector, the n-type single-crystal Si / single-crystal SiGe layer by ion implantation of 16b and 16d is an intrinsic emitter, and the p-type single-crystal SiGe layer 13 is a base layer. 2 is n + type Si for pulling out the collector
Layer 8 is a p-type polycrystalline Si film for drawing out the base, 1
Reference numeral 7 denotes an n + type Si layer for extracting an emitter, and reference numeral 20 denotes an n + type polycrystalline Si film for extracting an emitter.

In this transistor, the p-type polycrystalline Si film 8
And the non-doped single-crystal Si layer 14a are separated by the SiO ₂ film 18 and the p-type single-crystal SiGe film 13 and are not in direct contact with each other.

FIG. 5 is a graph showing the vertical distribution of the n-type impurity concentration, the p-type impurity concentration, and the Ge concentration in a portion indicated by a broken line A which is the intrinsic region of the transistor in FIG. In the portion indicated by the broken line A, the vicinity of the emitter-base junction, that is, the interface between the n-type single crystal Si layer and the single crystal SiGe layer (Y in FIG. 5)
The n-type impurity concentration at (point) is 1 × 10 ¹⁸ [atoms / cm ³ ], and the n-type impurity concentration at the n-type single-crystal Si layer / single-crystal SiGe layer interface (point X in FIG. 5) on the base-collector junction side. 1 × 10
¹⁷ One digit larger than [atoms / cm ³ ].

Next, the manufacturing method according to the first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIGS. First, a method of manufacturing the collector-top type SiGe base bipolar transistor in FIG. 1, that is, the transistor in FIG. 2 will be described with reference to FIGS. FIG. 11 and FIG. 12 show a vertical cross-sectional structure of a main part in a main step of manufacturing the collector top type transistor.

First, a low-concentration n-type silicon layer 3 is formed on the n-type Si layer 2 by a normal epitaxial growth method.

Next, a film thickness of 20 [nm] is obtained by oxidation of Si.
The SiO ₂ film 5 is formed, then, conventional chemical vapor deposition (CVD: C hemical V apor D eposition) process the Si ₃ N ₄ film 6 having a thickness of 30 [nm], the thickness 150 of [nm] p-type polycrystalline Si film 8, SiO ₂ film 1 having a thickness of 200 [nm]
Deposit 0.

Next, openings are formed in the SiO ₂ film 10 and the p-type polycrystalline Si film 8 by ordinary photolithography and dry etching.

Next, P (phosphorus) is ion-implanted as an impurity with an acceleration energy of 30 [keV].
The n-type Si layer 11 is heated at 0 [° C.] for 20 minutes.
a is formed. The implantation amount is adjusted so that the peak concentration of P (phosphorus) in the n-type Si layer 11a is 1 × 10 ¹⁷ [atoms / cm ³ ]. FIG. 11A shows the steps up to this point.

Next, a film thickness of 50 [n] is obtained by a normal CVD method.
After depositing the SiO ₂ film 27 m], to remove the SiO ₂ film 27 other than the opening portion side walls by anisotropic dry etching.

Next, the bottom surface of the opening and the surrounding Si ₃ N ₄ film 6 are removed by etching by dipping in hot phosphoric acid. Further, the bottom surface of the opening and the SiO ₂ film 5 around the opening are removed by immersion in a hydrofluoric acid aqueous solution. FIG. 11B shows the steps up to this point.

Next, a non-doped single-crystal SiGe layer 12 having a thickness of 10 [nm], a p-type single-crystal SiGe layer 13 having a thickness of 20 [nm], and a thickness of 10 [nm] are obtained by selective epitaxial growth by a normal low-pressure CVD method. Is formed, and a non-doped single-crystal Si layer 14a having a thickness of 40 [nm] is formed. The steps so far are shown in FIG.
It is shown in (d).

Next, a film thickness of 30 is formed by a normal CVD method.
[Nm] SiO ₂ film 18 and 100 [nm] thick Si ₃ film
An N ₄ film 19 is deposited, and the Si ₃ N ₄ film 19 other than the side wall of the opening is removed by anisotropic dry etching. Thereafter, P (phosphorus) is ion-implanted as an impurity with an acceleration energy of 130 [keV] and 60 [keV], and the n-type Si layer 15 is formed.
The b and n-type SiGe layers 15a are formed. n-type Si layer 1
The implantation amount is adjusted such that the peak concentration of P (phosphorus) at the interface of the 5a / SiGe layer 15b is 1 × 10 ¹⁸ [atoms / cm ³ ]. FIG. 12D shows the steps up to this step.

Next, P (phosphorus) is ion-implanted as an impurity with an acceleration energy of 50 [keV], and n-type SiGe is implanted.
The layer 16c and the n-type Si layer 16a are formed. The implantation amount is adjusted such that the peak concentration of P (phosphorus) at the interface between the n-type Si layer 16a / SiGe layer 16b is 1 × 10 ¹⁷ [atoms / cm ³ ]. FIG. 12 (e) shows the steps so far.

Next, the SiO ₂ film 18 on the bottom surface of the opening is etched off by immersion in a hydrofluoric acid aqueous solution, and then a 150 nm thick n + -type polycrystalline S
An i film 20 is deposited. Next, after selectively removing the n + -type polycrystalline Si film 20 by ordinary photolithography and dry etching, heating is performed at 900 [° C.] for 10 seconds to activate the impurity in the ion-implanted portion. At the same time, impurities are diffused from the n + -type polycrystalline Si film 20 to form the n + -type Si layer 17. By this step, a collector top type SiGe base bipolar transistor is formed. The steps up to this point are shown in FIG.

Next, the emitter top type Si shown in FIG.
A method of manufacturing the Ge-based bipolar transistor, that is, the transistor of FIG. 4 will be described with reference to FIGS. FIG. 13 and FIG. 14 show a longitudinal sectional structure of a main part in a main manufacturing step of an emitter top type transistor. The method of manufacturing the transistor is the same as that of the collector-top transistor described with reference to FIGS. 11 and 12 except for the step of adjusting the n-type impurity concentration of the emitter and the collector by ion implantation. These common steps are performed simultaneously with the formation of the collector-top transistor.

First, a low-concentration n-type silicon layer 3 is formed on the n + -type Si layer 2 by a normal epitaxial growth method.

Next, after forming a SiO ₂ film 5 having a thickness of 20 [nm] by oxidizing Si, ordinary chemical vapor deposition (CVD) is performed.
30 nm thick Si ₃ N ₄ film 6 with a thickness of 150
A [nm] p-type polycrystalline Si film 8 and a 200 [nm] -thick SiO ₂ film 10 are deposited.

Next, openings are formed in the SiO ₂ film 10 and the p-type polycrystalline Si film 8 by ordinary photolithography and dry etching. The above steps are performed simultaneously with the step of forming the collector top type transistor.

Next, P (phosphorus) is ion-implanted as an impurity with an acceleration energy of 100 [keV].
N-type Si layer 1 by heating at 00 [° C.] for 20 minutes.
1b is formed. The amount of implantation is adjusted so that the P (phosphorus) concentration at the interface between 11b and the single crystal SiGe layer 14 is 1 × 10 ¹⁷ [atoms / cm ³ ]. This ion implantation step is performed independently of the formation of the collector top type transistor. FIG. 13A shows the steps up to this point.

Next, the steps shown in FIGS. 13 (b) and 13 (c) are the same and are performed simultaneously with the case of the collector-top type transistor shown in FIG. 11, and a description thereof will be omitted.

Next, a film thickness of 30
[Nm] SiO ₂ film 18 and 100 [nm] thick Si ₃ film
An N ₄ film 19 is deposited, and the Si ₃ N ₄ film 19 other than the side wall of the opening is removed by anisotropic dry etching. These steps are performed simultaneously with the step of forming the collector top type transistor. Thereafter, P (phosphorus) is ion-implanted as an impurity with an acceleration energy of 50 keV, and n-type SiG
An e layer 16d and an n-type Si layer 16b are formed. n-type Si
The implantation amount is adjusted so that the peak concentration of P (phosphorus) at the interface between the layer 16b and the SiGe layer 16d is 1 × 10 ¹⁸ [atoms / cm ³ ]. This ion implantation step is performed independently of the formation of the collector top type transistor. FIG. 14D shows the steps up to this step.

Next, the SiO ₂ film 18 on the bottom surface of the opening is etched off by immersion in a hydrofluoric acid aqueous solution, and then a 150 nm thick n + -type polycrystalline S
An i film 20 is deposited.

Next, after the n + -type polycrystalline Si film 20 is selectively removed by ordinary photolithography and dry etching, heating is performed at 900 ° C. for 10 seconds to remove impurities in the ion-implanted portion. While being activated, impurities are diffused from the n + -type polycrystalline Si film 20 to form the n + -type Si layer 17.
To form These steps are performed simultaneously and simultaneously with the case of the collector top type transistor shown in FIG. By this step, an emitter top type SiGe base bipolar transistor is formed. FIG. 14 (e) shows the steps so far.

In this embodiment, in both the collector top type and the emitter top type, the n-type impurity concentration at the n-type Si / SiGe layer interface on the emitter side in the intrinsic region (operating region) is 1 × 10 ¹⁸ [atoms / cm ^3]. ], Which is 2.5 times higher than the conventional type, so that injection of holes from the base layer to the emitter layer is suppressed. In the collector-top transistor of the present embodiment, the n-type Si layers 11a and 11
The injection of holes from the base layer to the emitter layer is further suppressed by b. However, the n-type Si layers 11a, 11b
Since the n-type impurity concentration is 1 × 10 ¹⁷ [atoms / cm ³ ], which is one digit lower than that of the intrinsic region, the increase in the emitter junction capacitance due to these layers is negligible.

According to the present embodiment, the injection of holes from the base to the emitter is about 1/10 in the collector top type transistor and about 1/2 in the emitter top type transistor as compared with the conventional transistor. As a result, there is an effect that the maximum cutoff frequency is about 4 times for the collector top type transistor and about 1.2 times for the emitter top type transistor.

Further, in both the collector top type and the emitter top type, n-type Si / S on the collector side in the intrinsic region is used.
The n-type impurity concentration at the interface of the iGe layer is 1 × 10 ¹⁷ [atom
s / cm ³ ], which is 1/4 of the conventional type. Therefore, both the collector top type and the emitter top type have an effect that the breakdown voltage between the base and the collector and the breakdown voltage between the emitter and the collector are 1.5 times and 1.2 times, respectively, as compared with the conventional type.

According to this embodiment, the p-type polycrystalline S
i layer 8 and the non-doped single-crystal Si layer 14a is, SiO ₂ film 1
8 and the p-type single-crystal SiGe film 13 are separated from each other and are not in direct contact with each other, so that the base-collector leakage current of the collector-top type transistor is also reduced by one digit as compared with the conventional type.

(Embodiment 2) Next, Embodiment 2 of the present invention
Will be described with reference to FIGS. 6 and 7. FIG. 6 shows a detailed vertical cross-sectional structure of a main part of the collector-top transistor according to the second embodiment of the present invention. FIG.
In the second embodiment, the collector top type transistor in FIG. 1 and 2 in FIG. 6 indicate the same components as those in FIGS. 1 and 2. Reference numeral 11c denotes an n-type single-crystal Si / single-crystal SiGe layer formed by ion implantation. The n-type single-crystal Si / single-crystal SiGe layer formed by the ion implantation 11c serves as an intrinsic emitter. The operation of the other parts is the same as that of the first embodiment (FIG. 2).

FIG. 7 is a graph showing the vertical distribution of the n-type and p-type impurity concentrations and the Ge composition in the portion indicated by broken line A, which is the intrinsic region of the transistor in FIG. As in the case of FIG. 3 of the first embodiment, in the intrinsic portion of the broken line A, the n-type near the emitter-base junction, that is, at the interface between the n-type single-crystal Si layer / single-crystal SiGe layer (point X in FIG. 7). The impurity concentration is 1 × 10 ¹⁸ atoms / cm ³ , and the interface between the n-type single-crystal Si layer and the single-crystal SiGe layer on the base-collector junction side
This is one digit larger than 1 × 10 ¹⁷ [atoms / cm ³ ] at (point Y in FIG. 7).

The method of manufacturing the collector top type transistor of the present embodiment uses the n-type single crystal Si by ion implantation.
Except for the formation of the / single-crystal SiGe layer 11c, it is the same as the method of manufacturing the collector-top transistor of the first embodiment shown in FIG. In FIG. 11A, an n-type Si layer 11 is formed.
Instead of forming a, P (phosphorus) is ion-implanted as an impurity at an acceleration energy of 30 [keV] and 100 [keV], and then heated at 900 [° C.] for 20 minutes to form an n-type Si layer 11 c. I do. The amount of implantation is adjusted so that the P (phosphorus) concentration on the substrate surface is 1 × 10 ¹⁸ [atoms / cm ³ ]. Further, the formation of the n-type single-crystal Si / single-crystal SiGe layers 15a and 15b in FIG. 12D is unnecessary in this embodiment.

The difference between this embodiment and the first embodiment will be described below. Although the n-type impurity concentration of the emitter layer of the collector-top transistor of the first embodiment shown in FIG. 2 was set to 1 × 10 ¹⁸ [atoms / cm ³ ] by ion implantation only in the area immediately below the collector opening, In the form,
The concentration of the emitter layer immediately below the opening of the p-type polycrystalline Si film 8 for drawing out the base is increased to 1 × 10 ¹⁸ [atoms / cm ³ ]. According to the present embodiment, the ion implantation step required for increasing the concentration of the emitter layer of the collector top transistor can be reduced by one time as compared with the first embodiment. However, since the emitter region having a high concentration of 1 × 10 ¹⁸ [atoms / cm ³ ] is wider than that of the first embodiment, the parasitic capacitance of the emitter-base junction is increased. There is a side effect that the cutoff frequency of the transistor is reduced by about 20% compared to the first embodiment.

(Embodiment 3) Next, Embodiment 3 of the present invention.
Will be described with reference to FIG. FIG. 8 shows a detailed vertical cross-sectional structure of a main part of the collector-top transistor according to the third embodiment of the present invention. The entirety of the present embodiment is obtained by replacing the collector top type transistor in FIG. 1 with the transistor in FIG. 8 indicate the same components as those in FIGS. 1 and 2. The function of each part is the same as that of the first embodiment (FIG. 2).
The vertical distribution of impurities in the intrinsic portion of the transistor is the same as that of the first embodiment (FIG. 3). The method for manufacturing the collector-top transistor of the present embodiment is described in FIGS.
This is the same as the method of manufacturing the collector-top transistor of Embodiment 1 shown in FIG. 11 except that only the step of forming the n-type Si layer 11a in FIG. 11A is omitted.

The difference between this embodiment and the first embodiment will be described below. In the collector top type transistor of the first embodiment shown in FIG. 2, the n-type impurity concentration just below the collector opening in the emitter layer is set to 1 × by ion implantation.
10 ¹⁸ [atoms / cm ³ ] and p for pulling out the base
The n-type impurity concentration just below the opening of the polycrystalline Si film 8 is 1 ×
Although it was set to 10 ¹⁷ [atoms / cm ³ ], in Embodiment 3 of FIG. 8, the n-type impurity concentration immediately below the collector opening was 1 × 10 ^18.
[Atoms / cm ³ ] only.

According to the present embodiment, the ion implantation step required for increasing the concentration of the emitter layer of the collector top transistor can be reduced by one time as compared with the first embodiment. However, since the emitter layer around the intrinsic region is non-doped, the number of holes injected from the base into that portion increases, so that the cut-off frequency of the collector-top transistor is lower than that of the first embodiment. There is a side effect that is reduced by about 20%.

(Embodiment 4) Next, Embodiment 4 of the present invention.
Will be described with reference to FIGS. 9 and 10. FIG. 9 shows a detailed longitudinal sectional structure of a main part of an emitter top type transistor according to a fourth embodiment of the present invention. The whole of the present embodiment is obtained by replacing the emitter top type transistor in FIG. 1 with the transistor in FIG.
The reference numerals in FIG. 9 included in FIG. 1 and FIG.
Refers to the same thing. 17a is an n + type single crystal S
It is an iGe layer. The n + type single crystal Si / single crystal SiGe layers 17 and 17a are the intrinsic emitters. The operation of the other parts is the same as that of the first embodiment (FIG. 4).

FIG. 10 is a graph showing the n-type and p-type impurity concentrations and Ge at the portion indicated by broken line A, which is the intrinsic region of the transistor in FIG.
4 is a graph showing a longitudinal distribution of a composition. As in the case of FIG. 4 of the first embodiment, the n-type near the emitter-base junction, that is, at the interface between the n-type single crystal Si layer / single crystal SiGe layer (point Y in FIG. 10) in the intrinsic portion of the broken line A. impurity concentration is ^{1 × 10 19 [atoms / cm} 3], the base - (in FIG. 10, X point) collector junction side n-type single-crystal Si layer / single-crystal SiGe layer interface of 1 × 10 ¹⁷ in [ atoms / cm ³ ].

The method of manufacturing the emitter top type transistor of this embodiment is different from the step of cutting the non-doped single crystal Si layer 14a by 20 [nm] by dry etching before the deposition of the n + type polycrystalline Si film 20 in FIG. Figure 14
This is the same as the method of manufacturing the emitter-top transistor of the first embodiment shown in FIG.

The difference between this embodiment and the first embodiment will be described below. In the emitter-top transistor of the first embodiment shown in FIG. 4, the impurity concentration between the n + -type Si layer 17 and the p-type SiGe base layer 13 due to impurity diffusion from the n + -type polycrystalline Si film 20 is 10 ¹⁸ [atoms]. / Cm ³ ] n-type single-crystal Si layer 16b / single-crystal SiGe layer 16d were sandwiched.
6b / no single-crystal SiGe layer 16d layer, n + type polycrystalline S
n + type SiGe layer 17a by impurity diffusion from i film 20
Are in direct contact with the p-type SiGe base layer 13.

According to the present embodiment, the emitter layer near the base layer has a higher concentration, and the injection of holes from the base layer to the emitter layer can be further reduced. Cutoff frequency 1
There is an effect that can be improved relatively.

Further, since ion implantation is not used for forming the n-type layer of the emitter, there is also an effect that there is no crystal damage due to ion implantation and the leakage current of the transistor can be reduced.

Further, there is an effect that the number of ion implantation steps required for increasing the concentration of the emitter layer can be reduced by one time. However, there is a side effect that an extra process of shaving the non-doped single-crystal Si layer 14a by dry etching is required.

In the first to fourth embodiments of the present invention, the portion above the base layer of the transistor protrudes in a trapezoidal shape. This is because this portion is formed by selective epitaxial growth. According to this structure, as described above, there is an effect that the base-collector leakage current of the collector top type transistor is reduced by one digit as compared with the conventional type. However, this structure is not inevitable for effects other than the reduction of the base-collector leakage current. For example, Si ₃ in FIG. 2
When the film thickness of the N ₄ film 6 is increased to 50 [nm], a transistor having no such trapezoidal protrusions is obtained as shown in FIG. 15, but by using this transistor instead of the transistor of FIG. Needless to say, the same effect as the transistor of FIG. 2 can be obtained except for the leak current between the collectors.

Although it is possible to form the transistor shown in FIG. 16 by using the whole surface growth instead of using the selective epitaxial growth, in this case as well, except for the base-collector leakage current, the transistor shown in FIG. Needless to say, an effect similar to that of a transistor can be obtained.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0069]

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

In the conventional technique, the collector and emitter of the collector-top transistor and the emitter-top transistor formed on the same substrate have the same impurity concentration. According to the present invention, in the collector-top type transistor and the emitter-top type transistor formed on the same substrate, it is possible to increase the impurity concentration of the emitter while keeping the impurity concentration of the collector low. If the impurity concentration of the emitter is increased,
The injection of holes from the base to the emitter is suppressed, and the operation speed can be improved.

Also, keeping the collector impurity concentration low keeps the base-collector breakdown voltage and the emitter-collector breakdown voltage high, lowers the base-collector parasitic capacitance,
This has the effect of improving the operation speed. The quantitative improvement effect depends on the ratio between the impurity concentration of the emitter and the impurity concentration of the collector. In order to make the effect of the present invention remarkable, the impurity concentration of the emitter must be at least about 1.5 times the impurity concentration of the collector. The impurity concentration of the emitter is 1 × 10 ¹⁸ [atoms / cm ³ ], which is 2.5 times that of the conventional transistor, and the impurity concentration of the collector is 1 × 10 ¹⁷ [atoms / cm ³ ].
/ Cm ³ ], 1/4 of the conventional transistor, and 10 times the ratio of the impurity concentration of the emitter to the impurity concentration of the collector, the maximum cutoff frequency of the collector-top type transistor is smaller than that of the conventional transistor. The effect is four times that of the emitter top type transistor and about 1.2 times that of the emitter top type transistor.

In both the collector-top type and the emitter-top type, the breakdown voltage between the base and the collector and the breakdown voltage between the emitter and the collector are each 1.5 times that of the conventional transistor.
There is also an effect of multiplying by 1.2 times.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a longitudinal sectional view of a main part of the collector top type bipolar transistor according to the first embodiment of the present invention.

3 is a graph showing vertical distributions of an n-type impurity concentration, a p-type impurity concentration, and a Ge concentration in an intrinsic region of the collector-top bipolar transistor of FIG. 2;

FIG. 4 is a longitudinal sectional view of a main part of the emitter top type bipolar transistor according to the first embodiment of the present invention.

5 is a graph showing a vertical distribution of an n-type impurity concentration, a p-type impurity concentration, and a Ge concentration in an intrinsic region of the emitter top type bipolar transistor of FIG.

FIG. 6 is a longitudinal sectional view of a main part of a collector top type bipolar transistor according to a second embodiment of the present invention.

7 is a graph showing a vertical distribution of an n-type impurity concentration, a p-type impurity concentration, and a Ge concentration in an intrinsic region of the collector-top bipolar transistor of FIG.

FIG. 8 is a longitudinal sectional view of a main part of a collector top type bipolar transistor according to a third embodiment of the present invention.

FIG. 9 is a longitudinal sectional view of a main part of an emitter top type bipolar transistor according to a fourth embodiment of the present invention.

10 is a graph showing vertical distributions of an n-type impurity concentration, a p-type impurity concentration, and a Ge concentration in an intrinsic region of the emitter-top bipolar transistor of FIG.

FIG. 11 is a longitudinal sectional view of a main part in a main step in the method of manufacturing the collector top type bipolar transistor according to the first embodiment of the present invention.

FIG. 12 is a longitudinal sectional view of a main part in a main step in the method of manufacturing the collector top bipolar transistor in the first embodiment of the present invention.

FIG. 13 is a longitudinal sectional view of a main part in a main step in the method of manufacturing the emitter top bipolar transistor according to the first embodiment of the present invention.

FIG. 14 is a longitudinal sectional view of a main part in a main step in a method of manufacturing the emitter top bipolar transistor according to the first embodiment of the present invention.

FIG. 15 is a longitudinal sectional view of a main part of a collector-top bipolar transistor according to a fifth embodiment of the present invention.

FIG. 16 is a longitudinal sectional view of a main part of a collector top type bipolar transistor according to a sixth embodiment of the present invention.

FIG. 17 is a longitudinal sectional view of a main part of a bipolar transistor which performs a collector-top type and an emitter-top type bidirectional operation in the prior art.

18 is a graph showing a vertical distribution of an n-type impurity concentration, a p-type impurity concentration, and a Ge concentration in an intrinsic region of the bipolar transistor of FIG.

[Explanation of symbols]

1 ... p-type Si substrate, 2 ... n ₊ -type Si layer, 3 ... low concentration n-type silicon layer, 4 ... n + -type Si layer, 5 ... SiO ₂ film, 6 ... Si
₃ N ₄ film, 7 ... SiO ₂ film, 8 ... p-type polycrystalline Si film, 9 ... n
Type polycrystalline Si film, 10 ... SiO ₂ film, 11a ... n type Si
Layers, 11b ... n-type Si layer, 11c ... n-type Si layer, 12 ...
Non-doped single crystal SiGe layer, 13 ... p-type single crystal SiG
e layer, 14 ... non-doped single-crystal Si / single-crystal SiGe
Layers, 14a: non-doped single-crystal SiGe layer, 14b: non-doped single-crystal Si layer, 15: n-type single-crystal Si / single-crystal SiGe layer, 15a: n-type single-crystal Si layer, 15b: n-type single-crystal SiGe layer, 16 ... n-type single crystal Si / single crystal Si
Ge layer, 16a ... n-type single crystal Si layer, 16b ... n-type single crystal Si layer, 16c ... n-type single crystal SiGe layer, 16d ... n
Type single crystal SiGe layer, 17 ... n + -type Si layer, 17a ... n + -type SiGe layer, 18 ... SiO ₂ film, 19 ... Si ₃ N ₄ film, 20
... n + -type polycrystalline Si film, 21 ... SiO ₂ film, 22 ... metal film,
23 ... metal film, 24 ... metal film, 25a ... n-type single crystal Si
Layers, 25b: n-type single-crystal SiGe layer, 26: n-type single-crystal Si layer, 27: SiO ₂ film.

Claims (11)

[Claims] 1. A bipolar transistor having a collector top type and an intrinsic base composed of a mixed crystal (SiGe) layer of Si and Ge of the second conductivity type, and an emitter top type having an intrinsic base composed of a second conductivity type SiGe layer. A semiconductor device having a bipolar transistor on the same substrate, comprising: a first type impurity concentration at a SiGe layer / Si layer interface below a base layer; and a first type impurity concentration at a SiGe layer / Si layer interface above the base layer. A semiconductor device, wherein the magnitude relation of the conductivity type impurity concentration is opposite between the collector top type and the base top type. 2. A multi-layered film including at least a polycrystalline Si film for drawing a base of a second conductivity type having an opening formed thereon and an insulating film on a first emitter of the first conductivity type, and an opening formed in the opening. On both sides of non-doped or low impurity concentration S
A collector-top bipolar transistor having a second-conductivity-type SiGe base layer sandwiched between iGe layers and having a collector layer made of at least a first-conductivity-type single-crystal Si layer on the SiGe base layer, An upper surface of the Si emitter layer directly below the collector opening region has a higher impurity concentration than an upper surface of the Si emitter layer in a region outside the opening of the polycrystalline Si film for leading out the second conductivity type base; At least immediately below the collector opening region, the concentration of the first conductivity type impurity at the interface between the SiGe layer and the single-crystal Si layer at the emitter-base junction is 1 compared with the concentration at the interface between the SiGe layer and the single-crystal Si layer at the base-collector junction. A bipolar transistor characterized by being at least five times as high. 3. The bipolar transistor according to claim 2, wherein the upper surface of the Si emitter layer immediately below the opening region of the polycrystalline Si film for leading out the second type conductivity base is directly below the outer region of the main opening. A bipolar transistor having a higher impurity concentration than an upper surface. 4. The bipolar transistor according to claim 3, wherein the upper surface of the Si emitter layer immediately below the collector opening region is outside the collector opening and the second opening.
A bipolar transistor having a higher impurity concentration than the upper surface of a Si emitter layer immediately below an opening region of a polycrystalline Si film for drawing a base of a seed conductivity type. 5. A multi-layered film including at least a polycrystalline Si film for extracting a base of a second conductivity type having an opening formed thereon and an insulating film on a first conductivity type Si collector layer, and the opening On both sides of non-doped or low impurity concentration S
a second conductivity type SiGe base layer sandwiched between a mixed crystal (SiGe) layer of i and Ge, and a first conductivity type single crystal Si layer on the single crystal SiGe base layer and an impurity concentration of a lower layer emitter top having an emitter layer but having a laminated between ^{5 × 10 19 [atoms / cm} 3] or less of the low impurity concentration layer and the impurity concentration of the upper layer is ^{5 × 10 19 [atoms / cm} 3] or more high impurity concentration layer -Type bipolar transistor, wherein the low impurity concentration emitter layer immediately below the emitter opening region has a higher impurity concentration than the low impurity concentration emitter layer outside the emitter opening region, and at least the emitter opening Immediately below the partial region, the first-conductivity-type impurity concentration at the interface between the SiGe layer and the single-crystal Si layer at the emitter-base junction is 1 compared to the concentration at the interface between the SiGe layer and the single-crystal Si layer at the base-collector junction. Bipolar transistor, characterized in that it has increased more than five times. 6. A multi-layer film including an insulating film and at least a second-conductivity-type base-leading polycrystalline Si film having an opening formed on the first-conductivity-type Si emitter layer, and the opening A second-conductivity-type base-extracting polycrystalline Si film having an insulating film on the side wall thereof, and a non-doped or low-impurity-concentration mixed crystal of Si and Ge (SiG
e) a second conductivity type SiGe base layer sandwiched between the layers;
A collector top type bipolar transistor having at least a collector layer of a first-type single-crystal Si layer on the SiGe base layer, wherein an upper surface of the first-type single-crystal Si collector layer has a base-outgoing multi-layer. A bipolar transistor, which is located above a lower end of an insulating film on a side wall of a crystalline Si film. 7. A multi-layered film including an insulating film and at least a second-conductivity-type base drawing polycrystalline Si film having an opening formed on the first-conductivity-type Si collector layer. A second-conductivity-type base-extracting polycrystalline Si film having an insulating film on the side wall thereof, and a non-doped or low-impurity-concentration mixed crystal of Si and Ge (SiG
e) a second conductivity type SiGe base layer sandwiched between the layers;
An emitter-top type bipolar transistor having at least an emitter layer of a first-conductivity-type single-crystal Si layer on the SiGe base layer, wherein an upper surface of the first-conductivity-type single-crystal Si emitter layer has a base leading-out polycrystalline silicon layer. A bipolar transistor, which is located above a lower end of an insulating film on a side wall of a crystalline Si film. 8. The emitter top type bipolar transistor according to claim 7, wherein said second type conductivity type Si transistor
A bipolar transistor, wherein an emitter opening region of a Si layer on a Ge base layer is thinner than other regions. 9. The semiconductor device according to claim 1, wherein:
7. The collector top type bipolar transistor according to claim 2, 3 or 4, or 6.
9. The semiconductor device according to claim 5, wherein the emitter-top transistor is the bipolar transistor according to claim 5, 7, or 8. 10. The semiconductor device according to claim 1, wherein said collector top type bipolar transistor is the bipolar transistor according to claim 2, claim 3, claim 4, claim 4, or claim 6. Semiconductor device. 11. A method for manufacturing a semiconductor device according to claim 1, wherein the step of simultaneously forming the SiGe base layers of both the collector top type transistor and the emitter top type transistor, A method for manufacturing a semiconductor device, comprising: introducing a first conductivity type impurity by ion implantation into respective emitter portions of an intrinsic region of a collector top transistor and an intrinsic region of an emitter top transistor.