JPH02152240A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate a need to estimate various margins such as an overlap of a polycrystalline silicon layer with an oxide film and the like and to make an element fine by a method wherein the oxide film is formed between emitter and graft base and an emitter polycrystalline silicon layer is grown selectively. CONSTITUTION:A P<-> type silicon substrate 101 is prepared; an N<+> type buried layer 102, an N<-> type epitaxial layer 103, an oxide film 104 for insulating and isolation use, an oxide film 105 and an N-type collector region 106 are formed one after another. A P-type base region 108 and a P<+> type graft base region 109 are formed continuously by making use of a photoresist 107 as a mask by an ion implantation method. Then, a nitride film 110 is grown at about 1,000Angstrom ; a recessed part 112 used to form an emitter is formed by making use of a photoresist 111 as a mask by an anisotropic etching operation. The photoresist is stripped off; after that, an oxidation operation is excited; an oxide film 113 is formed at about 1,000Angstrom on side faces of the recessed part; in addition, the oxide film at the bottom of the recessed part is removed by executing the anisotropic etching operation. Lastly, a polycrystalline silicon layer 114 is grown selectively so as to fill the recessed part; N-type impurities are introduced; a heat treatment is executed; an N<+> type emitter region 115 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a bipolar transistor, and more particularly to a method for manufacturing a bipolar transistor in which a photolithography step for forming a heavily doped base region is omitted.

[Conventional technology]

Conventionally, bipolar transistors have been used in various logic ICs and near ICs because of their high speed and good linearity.

FIG. 3 shows a cross-sectional view of the structure of a conventional NPN type bipolar transistor. The manufacturing process will be explained below. first,
An N+ type buried layer 302 is formed on a P- type silicon substrate 301, and an N- type epitaxial layer 303 is further formed.

Next, a nitride film having a predetermined shape is formed, and this is used as an oxidation-resistant mask to form an oxide film 304 for insulation isolation. After forming the oxide film 305, N-type impurities are diffused into the collector portion to form an N-type collector region 306. Next, a P type base region 307 is formed using an ion implantation method or the like, and a P + type heavily doped base region (hereinafter referred to as a graft base) 308 is further formed in order to reduce the base contact resistance. After opening a diffusion window for emitter diffusion, polycrystalline silicon 309 is grown and formed into a predetermined shape by dry etching or the like. Furthermore, N-type impurities are introduced into the polycrystalline silicon layer, heat treatment is added, and the emitter region 31
form 0. Thereafter, an interlayer insulating film 311 is formed and aluminum wiring 312 is provided to complete the device.

[Problem to be solved by the invention]

In the conventional manufacturing method of bipolar transistors described above, a high concentration region (graft base) is formed by ion implantation to reduce the resistance of the base region and improve the characteristics of the transistor when drawing out the terminal from the base region using aluminum wiring. It must be formed by For this reason, a photolithography process must be performed to form the graft base, and when considering the breakdown voltage between the emitter and base, the lateral spread of emitter impurities and graft base impurities, and the formation of emitter and graft base. Various margins must be estimated, such as misregistration in the photolithography process, overlapping depletion layer growth between polycrystalline silicon and oxide film, etc., which increases device surface area and prevents miniaturization.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes the steps of: forming a buried layer and an epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type; forming an oxide film for insulation isolation and a collector diffusion region; forming a base layer of a first conductivity type having a two-stage impurity concentration profile with a high concentration near the surface and a low concentration near the base-collector junction;
A step of forming a recess reaching the low concentration region of the base layer, a step of oxidizing the side surfaces of the recess, and further removing an oxide film on the bottom of the recess by anisotropic etching, and forming a polycrystalline semiconductor layer to fill the recess. and a step of introducing impurities into the polycrystalline semiconductor layer and applying heat treatment to form an emitter region.

That is, the conventional method for manufacturing bipolar transistors described above uses a photolithography process to form a graft base to lower the resistance of the base region, and also overlaps the emitter polycrystalline semiconductor layer with an oxide film. In contrast, the present invention omits the photolithographic process for forming the graft base by forming an oxide film between the emitter graft bases, and also selectively grows the emitter polycrystalline silicon layer. This eliminates overlap with the oxide film.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(e) are longitudinal sectional views of an embodiment of the present invention.

First, as shown in FIG. 1(a), a P- type silicon substrate 101 is prepared, and an N+ type buried layer 102. N-type epitaxial layer 103
．． Insulating isolation oxide film 104. Oxide film 105. The N-type collector region 106 is sequentially formed. Next, as shown in FIG. 1(b), using the photoresist 107 as a mask, ion implantation is performed to form the P-type base region 108. A P+ type graft base region 109 is formed continuously. When the P-type base region is doped with boron, the acceleration energy is approximately 50 keV and the dose is 2 to 5 x 1013 cm.
When ion implantation is performed in step 2, and poron is used as the dopant in the P" type graft base region, the acceleration energy is about 30 keV and the dose is 4 to 6 x 10 "cm-".
It seems appropriate to perform ion implantation in Next, Figure 1 (
As shown in c), about 1000 nitride films 110 are grown,
A recess 112 for forming an emitter is provided by anisotropic etching using the photoresist 111 as a mask. After removing the photoresist, oxidation is performed to form about 1000 oxide films 113 on the side surfaces of the recess as shown in FIG. 1(d), and anisotropic etching is further performed to remove the oxide film on the bottom of the recess. Finally, a polycrystalline silicon layer 114 is selectively grown to fill the recess, and an N+ type emitter region 115 is formed by introducing N type impurities and performing heat treatment. Thereafter, an interlayer insulating film and a metal wiring layer are formed using conventional methods to complete the device.

FIG. 2 is a longitudinal sectional view of another embodiment of the invention.

As shown in FIG. 2(a), a P- type silicon substrate 201 is prepared, and as in the first embodiment, an N+ type buried layer 202, an N- type epitaxial layer 203. Insulating isolation oxide film 204. Oxide film 205. An N-type collector region 206 is formed. Next, using the photoresist 207 as a mask, a recess 208 is formed in the base formation region using anisotropic etching. Second
After removing the resist, a selective epitaxial layer is grown in the recessed portions as shown in FIG. 3(b). At this time, the dopant concentration is changed during the growth, and the P type base region 209 and P
A +-type graft base region 210 is formed. Furthermore, the surface of the selective epitaxial layer is oxidized to form an oxide film 211. Thereafter, in the same manner as in Example 1, an emitter portion is formed to complete the device. In this example, the base width W is W = (Base-Collector Junction Depth) - (Base-Emitter Junction Depth) - (Emitter Diffusion Depth) where the Base-Collector Junction Depth and Base-
Since the depth of the emitter junction is determined by the depth of the anisotropic etching of the base recess and the emitter recess, there is an advantage that a bipolar transistor with a very thin base width can be manufactured with high precision.

〔Effect of the invention〕

As explained above, the present invention does not require a photolithography process to form a graft base, and the emitter and high concentration base regions are insulated by an oxide film. There is no need to estimate various margins such as misalignment due to the graphic process and overlap between the polycrystalline silicon layer and the oxide film, and the device can be miniaturized. In addition, the depletion layer does not extend laterally, causing reach-through and reducing the breakdown voltage, and the breakdown voltage is determined only by the concentrations of the emitter and the P-type base. Furthermore, Example 2
If the base region is formed using a selective epitaxial layer as shown in FIG. 1, the base width is determined by the precision of anisotropic etching, and it becomes possible to form a bipolar transistor with a thin base width.

[Brief explanation of the drawing]

1(a) to 1(e) are longitudinal sectional views of Example 1 of the method for manufacturing a bipolar transistor of the present invention, FIG. 2(a),
(b) is a longitudinal cross-sectional view of another embodiment of the present invention, and FIG. 3 is a structural cross-sectional view of a conventional bipolar transistor. 101.201,301...P- type semiconductor substrate, 102.202,302...N+ type epitaxial layer, 103,203,303...N- type epitaxial layer, 104, 204, 304...
・Oxide film for insulation isolation, 105, 205, 211, 305
・Old... Oxide film, 106, 206, 306... River N-type collector region, 107, 207, 111... Photoresist, 108, 307... P-type base region, 109゜308...P+graft base region, 2o8...Base recess, 209...
・・P-type-<-s epitaxial layer, 210...
・P+ type graft base epitaxial 11.110・
...Nitride film, 112...River/emitter recess, 11
3...6.Side oxide film, 114,309...River...
Emitter polycrystalline semiconductor device, 115, 310... Group N
+ type emitter region, 311... interlayer insulating film, 3
12... Wiring metal layer. Agent Patent Attorney Susumu Uchihara Cry) (C) Cρ() ,'y7If5fFigure 7

Claims (1)

[Claims] A step of forming a buried layer and an epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type, a step of forming an oxide film for insulation isolation and a collector diffusion region, and a step of forming a base-collector junction with a high concentration near the surface. a step of forming a base layer of a first conductivity type having a two-stage impurity concentration profile with a low concentration in the vicinity, a step of forming a recess that reaches a low concentration region of the base layer, and oxidizing the side surface of the recess, Further, a step of removing the oxide film on the bottom surface of the recess by anisotropic etching, a step of selectively growing a polycrystalline semiconductor layer so as to fill the recess, and introducing an impurity into the polycrystalline semiconductor layer,
A method for manufacturing a semiconductor device, comprising the step of applying heat treatment to form an emitter region.