JPH0722433A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a bipolar transistor that allows higher speed. CONSTITUTION:A high concentration collector buried layer 8a is formed from a collector wall 22 to the bottom area beyond an emitter 29, with on formation at the bottom of an external base 24. With this, without change in withstand voltage between a base and a collector, an epitaxial layer can be thinner, so that collector resistance may be reduced and collector-substrate capacity can be less.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a semiconductor device, and more particularly to the structure of a bipolar semiconductor integrated circuit device.

[0002]

2. Description of the Related Art It is widely known that a bipolar transistor is one of semiconductor elements excellent in high speed and high drivability. In order to improve device performance of a bipolar LSI, miniaturization and device structure improvement are required. Ingenuity is being made.

FIG. 17 is a sectional view showing the structure of a conventional bipolar transistor. In the figure, 1 is a P-type silicon substrate, 7 is an N-type epitaxial layer, 8 is an N-type high concentration collector buried layer, 9 is a PN separation layer, 19 is a P ⁺ region which is a channel cut region, 20 is an oxide film, 22 is a collector wall, 24 is an external base region, 26 is an intrinsic base region, 27 is a CVD oxide film, 29 is an emitter region, 30 is a polysilicon emitter electrode, 31 is an interlayer oxide film, and 32 is an aluminum wiring.

Next, manufacturing steps of the bipolar transistor shown in FIG. 17 will be sequentially described with reference to FIGS. First, as shown in FIG. 18, an oxide film pattern 2 is formed on a P-type silicon substrate 1, Sb ion implantation 111 is performed using this oxide film pattern 2 as a mask, and high-temperature annealing is performed to perform high-concentration N-type region. 3 is formed.

Next, as shown in FIG. 19, after the oxide film pattern 2 is removed, a thin oxide film 4 is formed. Next, a resist pattern 5 serving as a mask for ion implantation is formed, and B
Ion implantation 222 is performed and then high temperature annealing is performed to form a P-type region 6 to be a PN separation layer.

Next, as shown in FIG. 20, after removing the resist pattern 5 and the oxide film 4, a silicon epitaxial layer 7 is formed. At this time, the high concentration of S in the N-type region 3
b and B of the P-type region 6 diffuse into the P-type silicon substrate 1 and the silicon epitaxial layer 7, and the high-concentration collector buried layer 8 and the PN isolation layer 9 are formed.

Next, as shown in FIG. 21, a thin oxide film 10 is formed.
Is formed and a nitride film (not shown) is deposited, and then the nitride film is patterned using a lithography technique. By implanting B (not shown) through the oxide film 10 using this nitride film as a mask, the P-type region 11 is formed only above the PN isolation layer 9. Further, oxidation is performed using this nitride film as a mask to form a thick oxide film 12 on a part of the oxide film 10.
After removing the nitride film, P implantation (not shown) is performed on the entire surface to leave N only on the surface of the active region except the P-type region 11.
The mold region 13 is formed.

Next, as shown in FIG. 22, by performing high temperature annealing, the silicon epitaxial layer 7 becomes the N type epitaxial layer 7 and the P type region 11 becomes the PN isolation layer 9. After that, the oxide film 10 and the thick oxide film 12 are removed,
After the thin oxide film 14, the polysilicon film 15, and the nitride film 16 are sequentially deposited, the nitride film 16 is patterned using the resist pattern 17 as a mask.

Next, as shown in FIG. 23, a resist pattern 18 is formed on the entire surface as an ion implantation mask, and B ion implantation 333 is performed to form a channel cut region P ^+.
Region 19 is formed in PN isolation layer 9.

Next, as shown in FIG. 24, after removing the resist patterns 17 and 18, the polysilicon film 15 is oxidized using the pattern of the nitride film 16 as a mask to form a thick oxide film 20. After removing the pattern of the nitride film 16 and the unoxidized polysilicon film 15, the nitride film 21 is deposited again and patterned to form a pattern of the nitride film 21. Further, phosphorus glass (not shown) is deposited and subjected to high temperature annealing to form the collector wall 22, and then the phosphorus glass is removed by etching.

Next, as shown in FIG. 25, after removing the nitride film 21 pattern by etching, a resist pattern 23 is formed. B using this resist pattern 23 as a mask
The extrinsic base 24 is formed by high-concentration ion implantation 444 of S ₂ .

Next, as shown in FIG. 26, the resist pattern 23 is removed and a resist pattern 25 is formed again. Using this resist pattern 25 as a mask, B is ion-implanted 555 to form a P-type intrinsic base 26.

Next, as shown in FIG. 27, after removing the resist pattern 25, a CVD oxide film 27 is deposited on the entire surface. After that, a resist pattern 28 is formed as a mask for forming an emitter, the oxide film is removed, and then arsenic is ion-implanted 666 to form an N-type emitter region 29.

Next, as shown in FIG. 28, after removing the resist pattern 28, a polysilicon film is deposited and the polysilicon film is patterned to form a polysilicon emitter electrode 30.

Finally, as shown in FIG. 17, an interlayer oxide film 31 is deposited on the entire surface. A bipolar transistor is completed by forming a contact hole in the interlayer oxide film 31 and forming an aluminum wiring 32 for electrically connecting the polysilicon emitter electrode 30, the external base 24, and the collector wall 22.

[0016]

The conventional bipolar transistor is constructed as described above, and as shown in FIG. 17, in order to reduce the collector resistance, a wide range of N from below the collector wall 22 to below the external base 24 is provided.
Since the high-concentration collector burying layer 8 is formed, the collector-substrate capacitance becomes large, which hinders the high speed operation of the bipolar transistor.

Since the base-collector breakdown voltage is determined by the distance L1 between the external base 24 and the N-type high-concentration collector buried layer 8, it is necessary to increase L1 to ensure the base-collector breakdown voltage sufficiently. The epitaxial layer 7 had to be formed sufficiently thick. Along with this, the intrinsic base 2
6 and the N-type high-concentration collector buried layer 8 also increase the distance L2, which increases the collector resistance and hinders the high speed operation of the bipolar transistor.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a bipolar semiconductor device capable of reducing collector resistance and operating at a higher speed.

[0019]

In the semiconductor device according to the first aspect of the present invention, the high-concentration collector burying layer is formed from under the collector wall to over the emitter and not under the external base. It is a thing.

In the semiconductor device according to the second aspect of the present invention, the upper surface of the high-concentration collector buried layer is formed in the epitaxial layer under the external base and in the vicinity of the interface between the semiconductor substrate and the epitaxial layer. It is the one.

Further, in the semiconductor device according to claim 3 of the present invention, the thickness of the high-concentration collector buried layer in the region from below the collector wall to below the emitter to the external base is smaller than that in the other regions. It is formed to be thick.

Further, in the method of manufacturing a semiconductor device according to a fourth aspect of the present invention, in forming the high-concentration collector burying layer, from under the collector wall of the high-concentration collector burying layer to under the emitter to the external base. Is formed by ion-implanting the diffusion coefficient of the impurities to be injected into the region (4) which is larger than the diffusion coefficient of the impurities to be injected into the other region of the high concentration collector buried layer.

[0023]

In the semiconductor device according to the present invention, the high-concentration collector burying layer is formed from under the collector wall to over the emitter and not under the external base.
An epitaxial layer can be formed thin under the same base-collector breakdown voltage, and collector resistance can be reduced. Further, since the high concentration collector buried layer region becomes small, the collector-substrate capacitance also decreases.

Further, since the upper surface of the high-concentration collector buried layer is formed in the epitaxial layer near the interface between the semiconductor substrate and the epitaxial layer under the external base, the same base-collector breakdown voltage is maintained. Thus, the epitaxial layer can be formed thin and the collector resistance can be reduced.

Further, the film thickness of the high-concentration collector buried layer from under the collector wall to over the region under the emitter is made thicker than that in other regions, so that the epitaxial layer has the same thickness. However, the distance between the intrinsic base and the high-concentration collector buried layer can be shortened, and the collector resistance can be reduced. Further, the cross-sectional area of the high-concentration collector burying layer becomes large, and the collector resistance in the burying layer can be reduced.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the description of the same parts as those of the conventional technique will be appropriately omitted.

Example 1. 1 is a sectional view showing the structure of a bipolar transistor according to a first embodiment of the present invention. In the figure, the same parts as those in the conventional example are designated by the same reference numerals, and detailed description thereof will be omitted. Reference numeral 8a denotes an N-type high-concentration collector burying layer, which is formed below the region beyond the collector wall 22 and the emitter 29, and an N-type high-concentration collector burying layer 8a is formed below the external base 24. Absent.

Next, a method of manufacturing the bipolar transistor shown in FIG. 1 will be described. As shown in FIG.
The oxide film 2 is patterned on the patterned silicon substrate 1. At this time, the oxide film 2 is opened from below the region where the collector wall 22 is to be formed to extend at least below the region where the emitter 29 is to be formed and does not reach below the region where the external base 24 is to be formed, in the horizontal direction of the silicon substrate 1. Then, Sb ion implantation 111 is performed to form the high concentration N-type region 3.

After that, the N-type high-concentration collector buried layer 8a and the PN separation layer 9 shown in FIG. 3 are formed through the same steps as those of the conventional example shown in FIG. Further, the bipolar transistor shown in FIG. 1 is completed through the steps of FIGS.

The bipolar transistor shown in FIG.
Immediately below the external base 24, the N-type high-concentration collector buried layer 8 is formed.
Since a does not exist, the distance L between the external base and the high-concentration buried layer is L
1 is an oblique distance, and the epitaxial layer 7 can be formed thin for the same base-collector breakdown voltage.
Therefore, the intrinsic base that depends on the thickness of the epitaxial layer 7
The distance L2 between the high-concentration collector-embedded interlayers is reduced and collector resistance can be reduced. In addition, the N type high concentration collector buried layer 8a
Since the area becomes smaller, the collector-substrate capacitance also decreases.
Therefore, the speed of the bipolar transistor is improved.

Example 2. FIG. 4 is a sectional view showing the structure of the bipolar transistor of the second embodiment of the present invention. In the figure, the N-type high-concentration collector burying layer is composed of 8a and 8b, and the N-type high-concentration collector burying layer 8a is the same as in the first embodiment.
The N-type high-concentration collector burying layer 8b is connected to the high-concentration collector burying layer 8a, and its upper surface is within the epitaxial layer and near the interface between the epitaxial layer 7 and the silicon substrate 1. It was formed in.

Next, a method of manufacturing the bipolar transistor shown in FIG. 4 will be described. Similar to the first embodiment, the steps of FIGS. 2, 19, and 3 and the conventional example of FIGS.
After completing the steps of FIG. 24 in that order, the external base 24 is formed by ion implantation 444 of BS ₂ using the resist pattern 23 for forming the external base as a mask as shown in FIG. Is used as a mask to inject N-type impurities at high energy 777 and perform high-temperature annealing to form an N-type high-concentration collector buried layer 8b. At this time, although the upper surface of the N-type high-concentration collector buried layer 8b is within the epitaxial layer 7 by controlling the ion implantation energy, the temperature and time of the high temperature annealing, the interface between the silicon epitaxial layer 7 and the silicon substrate is as close as possible. To form. For example, P is formed by ion implantation with an energy of 1.5 MeV and a dose amount of 4 × 10 ¹⁵ / cm ² .

Further, in the conventional example, the bipolar transistor shown in FIG. 4 is completed through the steps of FIGS.

The bipolar transistor shown in FIG. 4 has an N-type high-concentration collector buried layer 8b formed under the external base 24, but is formed sufficiently below the external base 24. Regarding the buried interlayer distance L1 and the intrinsic base / high concentration collector buried interlayer distance L2, L1 can be formed small without changing L1 as in the first embodiment. Further, the high-concentration collector buried layers 8a and 8b are formed on the entire surface under the transistor operating layer, and further reduction of collector resistance can be expected. From the above, the high speed of the bipolar transistor is improved.

Example 3. FIG. 6 is a sectional view showing the structure of the bipolar transistor according to the third embodiment of the present invention. In the figure, the N-type high-concentration collector burying layer is composed of 8c and 8d, and the N-type high-concentration collector burying layer 8c is formed to be thicker than that of the N-type high-concentration collector burying layer 8d. .

Next, a method of manufacturing the bipolar transistor shown in FIG. 6 will be described with reference to the drawings. First, as shown in FIG. 7, the oxide film 2 is patterned on the P-type silicon substrate 1. At this time, the oxide film 2 is opened from below the region where the collector wall 22 is to be formed to extend at least below the region where the emitter 29 is to be formed and does not reach below the region where the external base 24 is to be formed, in the horizontal direction of the silicon substrate 1. Then A
s is ion-implanted 888 to form a high concentration N-type impurity region 3c.

Next, as shown in FIG. 8, after the oxide film 2 is removed, the oxide film pattern 2a is formed so as to be continuous with the high-concentration N-type impurity region 3c formed first and open below the region where the external base 24 is to be formed. To form. This oxide film pattern 2a
Using Sb as a mask, Sb is ion-implanted 999 to form a high concentration N-type impurity region 3d. At this time, the impurities implanted into the high-concentration N-type impurity region 3d are the high-concentration N-type impurity region 3c.
A substance having a diffusion coefficient smaller than that of the impurity to be implanted is formed.

After that, through the same steps as those of the conventional example shown in FIG. 19, the N-type high-concentration collector buried layers 8c, 8d, P shown in FIG. 9 are formed.
The N separation layer 9 is formed. At this time, the N-type high-concentration collector buried layer 8c is formed thicker than the N-type high-concentration collector buried layer 8d due to the difference in diffusion coefficient of the implanted impurities.

Further, the bipolar transistor shown in FIG. 6 is completed through the steps of FIGS. 21 to 28 of the conventional example.

In the bipolar transistor shown in FIG. 6, the N-type high-concentration collector burying layers 8c and 8d are lower than the 8d in the N-type high-concentration collector burying layer 8c under the intrinsic base 26 due to the difference in diffusion coefficient of implanted ions. Since it is formed thick, the intrinsic base 2 can be formed without changing the thickness of the epitaxial layer 7.
6 and the N-type high-concentration collector buried layer 8c can be reduced in distance L2, the base-collector breakdown voltage can be sufficiently secured, and the base-collector resistance can be reduced. Further, since the cross-sectional area of the N-type high concentration collector burying layer 8c becomes large, the collector resistance in the N-type high concentration collector burying layer 8c can be further reduced. Therefore, the high speed of the bipolar transistor can be improved.

Example 4. Although the above-mentioned first, second, and third embodiments describe the bipolar transistor in which PN isolation is performed, trench isolation, oxide film isolation, PN isolation,
Any separating structure may be used.

FIG. 10 is a sectional view showing the structure of a bipolar transistor of the present invention having a trench isolation structure, and its manufacturing method will be described with reference to FIGS.

First, as shown in FIG. 11, N-type impurities such as Sb are ion-implanted (not shown) on the entire surface of the P-type silicon substrate 1 to form high-concentration impurity regions 3e. Further, as in the case of FIG. 2, two oxide film patterns for the ion implantation mask are formed, N-type impurities such as As are ion-implanted 1111 at a high concentration on the substrate surface, and high temperature annealing is performed. As the impurities to be implanted at this time, a substance having a diffusion coefficient larger than that of the impurities previously implanted to the entire surface of the silicon substrate 1 is selected.

Next, as shown in FIG. 12, after removing the oxide film pattern 2, an N-type silicon epitaxial layer 7 is formed on the surface of the silicon substrate 1. At this time, the N-type high-concentration collector burying layers 8e and 8f are formed such that the N-type high-concentration collector burying layer 8f projects from the N-type high-concentration collector burying layer 8e due to the difference in diffusion coefficient of the implanted ions. It

Next, as shown in FIG. 13, a thin oxide film 33, a polysilicon film 34, and a thin oxide film 33 are formed on the main surface of the epitaxial layer 7.
After the nitride film 35 is sequentially deposited, the resist film (not shown) is used as a mask to form the nitride film 35 and the polysilicon film 34.
Pattern.

Next, as shown in FIG. 14, a field oxide film 36 is formed by thermal oxidation using the LOCOS method with the polysilicon film 34 and the nitride film 35 as a mask. afterwards,
The polysilicon film 34 and the nitride film 35 are removed.

Next, as shown in FIG. 15, a polysilicon layer 37 and a CVD oxide film 38 are sequentially formed on the entire surface. After that, a resist pattern (not shown) for forming the trench isolation is formed, and using this as a mask, first the CVD oxide film 3 is formed.
Etch 8. Next, the polysilicon layer 37 is etched using the CVD oxide film 38 as a mask. Further, using the polysilicon layer 37 as a mask, the field oxide film 36 is etched to expose the epitaxial layer 7. Subsequently, the epitaxial layer 7, the N-type high concentration collector burying layer 8e and the silicon substrate 1 are removed by anisotropic etching. After that, B is ion-implanted 2222 into the trench isolation groove 39 formed by this etching and P
A mold region 40 is formed.

Next, as shown in FIG. 16, the CVD oxide film 4 is formed.
The trench isolation trench 39 is filled by depositing 1. Thereafter, unnecessary CVD oxide films 38 and 41 and polysilicon film 37 are removed.

Further, the bipolar transistor having the trench isolation structure shown in FIG. 10 is completed through the steps of FIGS.

In the bipolar transistor shown in FIG. 10, the collector wall 22 of the high-concentration collector buried layer 8e is included.
A high-concentration collector burying layer 8f is formed from below to above the lower region of the external base 24 beyond below the region of the emitter 29. Therefore, the intrinsic base-collector distance L2 can be reduced by the thickness of the high-concentration collector burying layer 8f to reduce the collector resistance, and the external base / high-concentration collector burying interlayer distance L1 does not change significantly. The collector breakdown voltage is also sufficient. That is, the speed of the bipolar transistor is improved.

Example 5. In addition, the above-mentioned first, second, third,
Although 4 has been described with respect to the NPN type bipolar transistor, the same effect as in each of the above embodiments can be obtained even in the case of the PNP type bipolar transistor.

[0052]

As described above, according to the present invention, the high-concentration collector burying layer is formed from below the collector wall to beyond the emitter and not below the external base. The epitaxial layer can be formed thin under a breakdown voltage, and the collector resistance can be reduced. Also, since the high concentration collector buried layer region becomes small,
Substrate capacity is also reduced. Therefore, there is an effect of improving the high speed of the bipolar transistor.

Further, since the upper surface of the high-concentration collector buried layer is formed under the external base in the epitaxial layer and in the vicinity of the interface between the semiconductor substrate and the epitaxial layer, under the same breakdown voltage between the base and the collector. The epitaxial layer can be formed thin, the collector resistance can be reduced, and the high speed operation of the bipolar transistor can be improved.

Further, since the film thickness of the high-concentration collector burying layer in the region from under the collector wall to under the emitter to the external base is made thicker than that in other regions, the same thickness is obtained. Even with an epitaxial layer, the distance between the intrinsic base and the high concentration collector buried layer can be shortened,
Since the cross-sectional area of the high-concentration collector buried layer also becomes large, the collector resistance can be reduced, and the high speed operation of the bipolar transistor can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 3 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 4 is a sectional view showing a structure of a bipolar transistor according to a second embodiment of the present invention.

FIG. 5 is a cross-sectional view showing the method of manufacturing the bipolar transistor of FIG.

FIG. 6 is a cross-sectional view showing the structure of a bipolar transistor of Example 3 of the present invention.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 8 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

9 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 10 is a sectional view showing a structure of a bipolar transistor according to a fourth embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

12 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 13 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

14 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 15 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

16 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 17 is a sectional view showing the structure of a conventional bipolar transistor.

FIG. 18 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 19 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

20 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

21 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

22 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

23 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

24 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

25 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

FIG. 26 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

27 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

28 is a cross-sectional view showing a step in the method of manufacturing the bipolar transistor of FIG.

[Explanation of symbols]

1 Silicon Substrate 7 Epitaxial Layer 8a, 8b, 8c, 8d, 8e, 8f High Concentration Collector Buried Layer 22 Collector Wall 24 External Base 26 Intrinsic Base 29 Emitter

[Procedure amendment]

[Submission date] November 16, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0005

[Correction method] Change

[Correction content]

Next, as shown in FIG. 19, after the oxide film pattern 2 is removed, a thin oxide film 4 is formed. Next, a resist pattern 5 serving as a mask for ion implantation is formed, and B
There line ion implantation 222, the resist pattern 5 is removed
Forming a P-type region 6 serving as the PN isolation layer by high-temperature annealing After.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

Next, as shown in FIG. 20, after removing the oxide film 4 , a silicon epitaxial layer 7 is formed. At this time, Sb of the high-concentration N-type region 3 and B of the P-type region 6 diffuse into the P-type silicon substrate 1 and the silicon epitaxial layer 7 to form the high-concentration collector buried layer 8 and the PN separation layer 9. To be done.

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction content]

Next, as shown in FIG. 22, the silicon epitaxial layer 7 is converted into an N-type wafer by high temperature annealing.
And the P-type region 11 becomes the PN separation layer 9. After that, the oxide film 10 and the thick oxide film 12 are removed, a thin oxide film 14, a polysilicon film 15 and a nitride film 16 are sequentially deposited, and then the nitride film 16 is used with the resist pattern 17 as a mask.
Patterning is performed.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

Next, as shown in FIG. 25, after removing the nitride film 21 pattern by etching, a resist pattern 23 is formed. B using this resist pattern 23 as a mask
The extrinsic base 24 is formed by high-concentration ion implantation 444 of F ₂ .

[Procedure Amendment 5]

[Document name to be amended] Statement

[Name of item to be corrected] 0032

[Correction method] Change

[Correction content]

Next, a method of manufacturing the bipolar transistor shown in FIG. 4 will be described. Similar to the first embodiment, the steps of FIGS. 2, 19, and 3 and the conventional example of FIGS.
After the steps of FIG. 24 are completed in that order, as shown in FIG. 5, BF ₂ is ion-implanted 444 by using the resist pattern 23 for forming the external base as a mask to form the external base 24. Is used as a mask to inject N-type impurities at high energy 777 and perform high-temperature annealing to form an N-type high-concentration collector buried layer 8b. At this time, although the upper surface of the N-type high-concentration collector buried layer 8b is within the epitaxial layer 7 by controlling the ion implantation energy, the temperature and time of the high temperature annealing, the interface between the silicon epitaxial layer 7 and the silicon substrate is as close as possible. To form. For example, P is formed by ion implantation with an energy of 1.5 MeV and a dose amount of 4 × 10 ¹⁵ / cm ² .

Claims (4)

[Claims] 1. A semiconductor substrate of a first conductivity type, a second conductivity type epitaxial layer formed on the substrate, a second conductivity type collector wall formed on a part of the epitaxial layer, and A first conductivity type extrinsic base and an intrinsic base formed in a partial surface region of the epitaxial layer, a second conductivity type emitter formed in a partial surface region of the intrinsic base, the semiconductor substrate, and the epitaxial layer In a bipolar semiconductor device having a second-conductivity-type high-concentration collector burying layer formed over the substrate, the high-concentration collector burying layer is formed below the collector wall and beyond the emitter. A semiconductor device, which is not formed under the external base. 2. A semiconductor substrate of a first conductivity type, a second conductivity type epitaxial layer formed on the substrate, a second conductivity type collector wall formed on a part of the epitaxial layer, and A first conductivity type extrinsic base and an intrinsic base formed in a partial surface region of the epitaxial layer, a second conductivity type emitter formed in a partial surface region of the intrinsic base, the semiconductor substrate, and the epitaxial layer In a bipolar semiconductor device having a second-conductivity-type high-concentration collector burying layer formed over the substrate, an upper surface of the high-concentration collector burying layer under the external base is in the epitaxial layer. And a semiconductor device formed near an interface between the semiconductor substrate and the epitaxial layer. 3. A first conductivity type semiconductor substrate, a second conductivity type epitaxial layer formed on the substrate, a second conductivity type collector wall formed on a part of the epitaxial layer, and A first conductivity type extrinsic base and an intrinsic base formed in a partial surface region of the epitaxial layer, a second conductivity type emitter formed in a partial surface region of the intrinsic base, the semiconductor substrate, and the epitaxial layer A high-concentration collector buried layer of the second conductivity type formed over the high-concentration collector region, the high-concentration region in the region from below the collector wall to below the emitter to the external base. A semiconductor device in which the thickness of the collector buried layer is formed thicker than that of other regions. 4. In the formation of the high-concentration collector burying layer, the diffusion coefficient of impurities to be injected into the region of the high-concentration collector burying layer from below the collector wall to below the emitter to the external base is set to the high-concentration collector. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the buried layer is formed by ion-implanting an impurity having a diffusion coefficient larger than that of the other region.