JP3068733B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for manufacturing a low noise NPN transistor.

[0002]

2. Description of the Related Art As the density and speed of semiconductors increase,
Miniaturization of transistors as constituent elements, miniaturization of emitter-base junction, and the like have been performed. As an example of such a conventional manufacturing method, there is a method shown in FIG. Hereinafter, a conventional manufacturing method will be briefly described with reference to FIG.

First, after a buried collector layer 2 is formed in a p-type substrate 1, an epitaxial layer 3 is grown. Subsequently, a high-concentration p-type diffusion region 4 as an isolation diffusion region and an n-type diffusion region 5 for connection to a collector are formed in the epitaxial layer 3.
To form Thereafter, an oxide film 6 is grown on the entire surface (FIG. 6).
(a)). Next, an opening is formed on the base region 7 by photoetching, and a p-type impurity is implanted using the resist and the oxide film as a mask (FIG. 6B).

Further, a resist 9 having an opening in an external base region 8 including a base contact portion is formed by photolithography. Using the resist 9 as a mask, a p-type impurity is implanted, and then the resist 9 is removed (FIG. 6C). Next, the emitter section is formed by photolithography.
A resist 11 having an opening in 10 is formed. This resist
An n-type impurity is implanted using 11 as a mask (FIG. 6D).

Next, a semiconductor device can be manufactured by performing wiring 16 by metallization after activating impurities by heat treatment (FIG. 6 (e)). Also, various methods for performing high-accuracy alignment using a self-alignment technique for miniaturization have been proposed. Such a conventional manufacturing method is described in, for example, Japanese Patent Application Laid-Open No. 2-10737, and the manufacturing method is, as shown in FIG.
The bases are formed in a self-aligned manner. Hereinafter, this manufacturing method will be briefly described.

First, after a buried collector layer 2 is formed in a p-type substrate 1, an epitaxial layer 3 is grown. Subsequently, a high-concentration p-type diffusion region 4 and an n-type diffusion region 5 for connection to the collector are formed as isolation diffusion regions. Thereafter, an oxide film 6 is grown on the entire surface (FIG. 7A). Next, openings for determining the graft base (external base) 17 and the active base (internal base) 18 are opened by photoetching (FIG. 7B).

Further, poly Si is deposited at 5000.degree., And poly Si 19 on the external base and poly Si 20 on the internal base are separated by photoetching (FIG. 7C). Next, the entire surface is oxidized at about 2500 °. Subsequently, the oxide film 21 on the poly-Si 19 in the outer base region is removed by leaving the oxide film 21 only in the inner base region by photolithography, and then the resist is removed.

Subsequently, a p-type impurity is implanted. At this time, since the oxide film 21 is on the internal base on the poly-Si 20, high-concentration impurities are implanted into the poly-Si 19 on the external base, and the poly-Si 20 on the internal base has a low concentration (FIG. 7D). ). Thereafter, heat treatment is performed in an oxidizing atmosphere. Here, an oxide film 22 is grown on the poly-Si 19 on the external base (FIG. 7E).

Next, the oxide film 21 on the poly-Si in the emitter region is removed by photoetching, and an n-type impurity is implanted. Subsequently, heat treatment is performed to activate the impurities (FIG. 7).
(f)). Furthermore, a semiconductor device can be manufactured by depositing an interlayer oxide film 23 and providing a wiring 27 by metallization (FIG. 7 (g)). In the manufacturing method shown in FIG. 6, since the internal base has an internal and external base structure, the characteristics such as the common emitter current gain (hFE) are determined in the internal base, and the external base can be in good contact with the metal. Therefore, the normal (no external base) N
An NPN transistor having a low base resistance and excellent high-frequency characteristics as compared with a PN transistor can be manufactured.

Further, since the emitter and the base can be formed only by photo-ion implantation, an NPN transistor excellent in reproducibility and cost can be formed. In the conventional example of FIG. 7, since the emitter and the external base can be formed in a self-aligned manner, the base resistance can be further reduced, and a high-performance NPN transistor can be formed.

[0011]

However, in the formation method shown in the conventional example of FIG. 6, even if activation for forming an emitter and a base by ion implantation and heat treatment for recovery from damage due to ion implantation are performed, As a result, the damage cannot be completely recovered, and in terms of characteristics, there are problems such as an increase in 1 / f noise and generation of burst noise.

In the conventional example shown in FIG. 7, the link region between the external base and the internal base is determined by the width of the oxide film and the lateral diffusion of impurities, and variations due to photo-etching of the oxide film are caused by the base resistance and the collector. -It has a structure that directly affects the leak characteristics between the emitters. In addition, the structure is such that polysilicon is separated by photo-etching on an oxide film (about 2 μm in width), and alignment accuracy is required.

If the alignment here deviates from above the oxide film, an unexpected impurity is introduced into the emitter region or the external base region, and it is unstable from the viewpoint of yield stability. Conceivable. Next, considering the number of photo steps for forming the emitter and the base, the conventional example of FIG. 6 is an NPN transistor having a structure having an internal and an external base, and has an internal base, an external base, and an emitter. Is required once each, and at least three photo steps are required.

In the conventional example shown in FIG. 7, at least four photo steps are required for forming the emitter and the base. As described above, in the conventional example, it was difficult to reduce the cost by reducing the number of photo steps. Generally, in the manufacture of semiconductor devices, this photo process is the most costly process since batch processing is impossible.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, that is, according to the present invention, an NPN transistor having a vertical emitter, base and collector. (I) laminating a first polysilicon layer on an epitaxial layer formed on a substrate, and forming a first polysilicon layer on the entire surface of the first polysilicon layer.
Implanting type impurity ions, (ii) laminating a second polysilicon layer on the entire surface of the first polysilicon layer, and implanting n-type impurity ions on the entire surface of the second polysilicon layer; (iii) forming a resist mask only on the region where the emitter is to be formed, and using the resist mask,
Etching the polysilicon layer, (iv) implanting p-type impurity ions over the entire surface of the substrate using the resist mask, (v) removing the resist mask, the first and second Oxidizing the polysilicon layer
Forming an oxide film and diffusing n-type and p-type impurity ions respectively into the epitaxial layer to form an emitter diffusion layer and a base diffusion layer; and (vi)
There is provided a method of manufacturing a semiconductor device, comprising a step of forming an emitter electrode, a base electrode, and a collector electrode.

The present invention employs two polysilicon layers as a diffusion source for introducing impurities into the emitter and the base, forms a photo step for forming the emitter and the base in a minimum of one time, and prevents damage due to ion implantation. An object of the present invention is to provide a method for manufacturing an NPN transistor which does not occur at all and has excellent reproducibility.

That is, the first polysilicon layer has a thickness of 400
Then, p-type impurity ions are implanted into the entire surface of the internal base impurity. In this case, examples of the impurity ions that can be used include boron and BF ₂ . As implantation conditions, an acceleration voltage of 5 to 30 KeV and 1 × 10 ¹³ to 1 × 1
0 ¹⁴ cm ^-3 is preferred.

Subsequently, n-type impurity ions are implanted into the second polysilicon layer to form an n ⁺ polysilicon layer. In this case, arsenic, phosphorus, and the like can be used as impurity ions. The implantation conditions are preferably 3 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻³ at an acceleration voltage of 30 to 80 KeV.

Subsequently, the second polysilicon layer is left only on the region where the emitter is to be formed by a known photo etching method. Next, using a resist mask used for the photo-etching method, impurity ions of an external base are implanted into the first polysilicon layer on which the second polysilicon layer is not stacked. In this case, examples of the impurity ions that can be used include boron and BF ₂ . The injection conditions are as follows: an acceleration voltage of 5 × 30 KeV, 3 × 10 ¹⁴ to 1 × 1
0 ¹⁵ cm ^-3 is preferred.

Thereafter, the resist mask is removed, and the first,
By thermally oxidizing the entire surface of the second polysilicon layer at about 900 ° C., an oxide film having a thickness of 2000 to 4000 ° is formed. At this time, the p ⁺ external base diffusion layer is thermally diffused from the first polysilicon layer on which the second polysilicon layer is not laminated to the external base region, and the second polysilicon layer is laminated. the internal base of the first polysilicon layer are, p ^- internal base diffusion layer are thermally diffused, and further, the second
Is formed by thermally diffusing an n ⁺ emitter diffusion layer from the first polysilicon layer through the first polysilicon layer. In this case, the n-type impurity diffuses from the second polysilicon layer to the first polysilicon layer, and the first polysilicon layer becomes an n ⁺ polysilicon layer, and then becomes the n ⁺ polysilicon layer. An n-type impurity is diffused from the one polysilicon layer into the silicon substrate.

In the impurity diffusion of the internal base portion, first, a p-type impurity diffuses from the first polysilicon film into the substrate. Subsequently, the n-type impurity is removed from the second polysilicon film to the first position.
To the polysilicon film. Thereafter, the n-type impurity diffuses into the substrate from the first polysilicon film. At this time, due to the time difference between the diffusion of the p-type impurity and the n-type impurity into the substrate, the diffusion of the n-type impurity removes the p-type impurity. Form emitter and base diffusion layers without overtaking.

Further, according to the present invention, an external base diffusion layer,
The impurities of the internal base diffusion layer and the emitter diffusion layer are not introduced into the substrate by ion implantation but are introduced into the substrate by diffusion from the polysilicon layer. As described above, since impurities are introduced into the substrate by diffusion from the polysilicon layer, there is no damage seen in ion implantation and a defect-free junction can be formed. An excellent NPN transistor can be manufactured.

FIG. 4 shows a graph of in-noise with respect to frequency. As can be seen from FIG.
The in-noise of the N transistor can be reduced by about 30%. Next, from the viewpoint of cost reduction, in the present invention, a photo step for forming an emitter and a base can be performed twice. That is, the first is for removing the oxide film from the base region, and the second is for patterning the polysilicon layer. This makes it possible to reduce the number of photo steps one time as compared with the related art.

Furthermore, according to the present invention, by leaving the first polysilicon layer only in the region where the emitter is to be formed,
It also provides for use as an emitter electrode. In order to leave the first polysilicon layer only under the region where the emitter is to be formed, the first polysilicon layer can be left by adjusting the thickness of the layer where the polysilicon layer is oxidized in the oxidation step. The thickness of the oxidized layer is preferably in the range of 1000 to 2000 °.

In the above method, a polysilicon emitter structure is employed. In the case of a polysilicon emitter structure, a photo step for patterning a polysilicon electrode is conventionally added in addition to the number of times of photo shown above. On the other hand, according to the present invention, a photo step for patterning the polysilicon electrode is not required, so that further cost reduction can be achieved.

However, in this method, the thickness of the polysilicon film of the emitter may be oxidized and thus may be reduced. Therefore, the present invention further provides a method for preventing oxidation of the polysilicon layer by laminating a nitride film having a thickness of 500 to 2,000 ° on the second polysilicon layer. According to this method, the polysilicon film of the emitter is not oxidized, so that a more flexible process can be designed. Further, since an NPN transistor can be formed without requiring alignment accuracy also from the viewpoint of process stability, an IC with excellent reproducibility can be manufactured.

[0027]

Embodiment 1 An embodiment of the present invention will be described with reference to FIG. First, the p-type silicon substrate 101 was exposed to an oxidizing atmosphere to form a silicon oxide film. The silicon oxide film in the region to be formed for forming the buried layer was removed. Next, the buried layer 102 was formed by thermally diffusing an n-type impurity into the region where the silicon oxide film was removed. Next, the silicon oxide film was removed, and an epitaxial layer 103 was formed by epitaxial growth using silane gas. Further, an oxide film was formed on the epitaxial layer 103 and patterned into a desired shape, and ap ⁺ diffusion layer as an isolation diffusion layer 104 and an n ⁺ diffusion layer as a collector diffusion layer 105 were formed. Further, an oxide film 106 was grown on the entire surface by about 2000 ° (FIG. 1A).

Next, the oxide film 106 on the region where the base diffusion layer was to be formed was removed using a well-known photo-etching technique (FIG. 1B). Subsequently, a first polysilicon film 107 is formed on the entire surface.
Were laminated for about 500 Å. Next, energy is applied to boron over the entire surface.
Ion implantation was performed under the conditions of 10 KeV and a dose of 4.0 × 10 ¹³ / cm ² (FIG. 1C).

Subsequently, a second polysilicon film 108 is formed on the entire surface.
Are laminated at about 1000 を, and As is applied to the entire surface at an energy of 30 KeV,
Ion implantation was performed under the conditions of a dose of 8.0 × 10 ¹⁵ / cm ² (FIG. 1D). Subsequently, the resist mask 109 was left over the region where the emitter is to be formed by a photo process, and the second polysilicon film 108 was etched using the resist mask 109. Subsequently, using this resist mask 109, boron is applied at an energy of 20 KeV and a dose of 5.0 × 10 5.
^The injection was performed under the condition of ¹⁴ / cm ² (FIG. 1 (e)).

After removing the resist mask 109, the entire polysilicon layer is oxidized (about 3000 ° oxidation) to form an oxide layer 115, and at the same time, impurities are diffused from the polysilicon layer. A diffusion layer 111 and an emitter diffusion layer 112 were formed (FIG. 1).
(F)). The collector compensation diffusion layer 10 is formed by a known technique.
5. External base diffusion layer 110 and emitter diffusion layer 112
Opened contact windows above to prepare a NPN transistor by this <br/> and forming a metal electrode 113 (FIG. 1
(G)).

Example 2 The same operation as in Example 1 was performed for FIGS. 1 (a) to 1 (e). Next, after removing the resist, it was oxidized by about 1000 ° C. to form an oxide film 115. At this time, the polysilicon layer on the external base diffusion layer 110 was entirely oxidized, and the polysilicon layer was present only on the emitter diffusion layer 112 (FIG. 2).
(a)). Next, in the same manner as in FIG.
113 and an NPN transistor was created (see FIG. 2).
(b)).

Example 3 The same operation as in Example 1 was performed for FIGS. 1 (a) to 1 (d). Next, a nitride film is laminated on the entire surface to a thickness of about 1000 mm, and a resist mask 109 is left over the region where the emitter is to be formed by a photolithography process. The nitride film 114 and the second polysilicon layer are formed using the resist mask 109. 108 was etched. Subsequently, using this resist mask 109, boron is applied at an energy of 20 KeV and a dose of 5.0 × 10
Ion implantation was performed under the condition of ¹⁴ / cm ² (FIG. 3A).

Next, the resist mask 109 is removed, and the nitride film 114 is used as an oxidation resistant mask for about 200 hours.
Oxidation of 0 ° is performed to form an oxide layer 115 ,
Impurities were diffused from the polysilicon layer into the epitaxial layer 103 to form an emitter diffusion layer 112 and base diffusion layers 110 and 111, respectively (FIG. 3B). Further, a metal electrode 113 was formed in the same manner as in FIG. 1 (g) of Example 1 to form an NPN transistor (FIG. 3 (c)).

FIG. 5 shows a density profile according to the present embodiment. According to this figure, the internal base portion has a high concentration of n.
It is shown that the ⁺ region does not overtake the p ^- region and the profile is surely formed.

[0035]

As has been described above, according to the present invention, an NP having good noise characteristics and excellent reproducibility with a simple and low cost process requiring less photo steps as compared with the conventional method.
N transistors can be formed.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a schematic sectional view of a method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a schematic sectional view of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a diagram illustrating a relationship between in-noise and frequency.

FIG. 5 is a diagram showing an impurity concentration distribution according to an example of the present invention.

FIG. 6 is a schematic explanatory view of a conventional method for manufacturing a semiconductor device.

FIG. 7 is a schematic explanatory view of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 101 p-type silicon substrate 102 buried layer 103 epitaxial layer 104 isolation diffusion layer 105 collector compensation diffusion layer 106 oxide film 107 first polysilicon layer 108 second polysilicon layer 109 resist mask 110 external base diffusion layer 111 internal base diffusion Layer 112 Emitter diffusion layer 113 Metal electrode 114 Nitride layer 115 Oxide layer

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-58-154267 (JP, A) JP-A-54-85680 (JP, A) JP-A-63-204648 (JP, A) JP-A-58-154 12358 (JP, A) JP-A-61-91961 (JP, A) JP-A-63-239856 (JP, A) JP-A-60-127760 (JP, A) JP-A-1-222480 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/331 H01L 29/73

Claims (3)

(57) [Claims] 1. A method of manufacturing an NPN transistor having an emitter, a base and a collector in a vertical type, comprising: (i) laminating a first polysilicon layer on an epitaxial layer formed on a substrate. Implanting p-type impurity ions into the entire surface of the first polysilicon layer; (ii) laminating a second polysilicon layer over the entire surface of the first polysilicon layer; Implanting n-type impurity ions over the entire surface of (iii), forming a resist mask only on the region where the emitter is to be formed, and etching the second polysilicon layer using the resist mask; (iv) Implanting p-type impurity ions over the entire surface of the substrate using the resist mask; (v) removing the resist mask and oxidizing the first and second polysilicon layers to form an oxide film.
Forming an emitter diffusion layer and a base diffusion layer by diffusing n-type and p-type impurity ions into the epitaxial layer, respectively; and (vi) forming an emitter electrode, a base electrode, and a collector electrode. Manufacturing method. 2. The method according to claim 1, wherein the step (v) is performed in a region where an emitter is to be formed.
First and second polysilicon layers other than the first polysilicon layer.
2. The method according to claim 1 , further comprising oxidizing a capacitor layer and using the first polysilicon layer as an emitter electrode. 3. After the step (ii), a nitride film is laminated on the entire surface of the second polysilicon film, and the nitride film is formed together with the second polysilicon film at the time of etching in the step (iii). 2. The method according to claim 1, further comprising etching the film and oxidizing the first polysilicon layer in the step (v) using the nitride film as an oxidation-resistant mask.