JP2830089B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOSFET are integrated on the same silicon substrate, and more particularly to a method in which the MOSFET has an LDD structure.

[Conventional technology]

In recent years, in semiconductor integrated circuits, bipolar transistors and MOSFETs have been integrated on the same silicon substrate due to demands for higher speed and higher integration. Also, MO
Regarding SFETs, sidewalls (sidewalls) made of an insulating film are provided on a gate electrode, and a sidewall transistor or an LDD transistor is used.

An example of this type of conventional manufacturing method is shown in FIGS.
It is shown in (c).

NPN bipolar transistor and N-channel of LDD structure
In the case of a MOSFET, the boundary between the P-type silicon substrate 1 and the N-type epitaxial layer 4 provided thereon is
An N ⁺ type buried layer 2 and a P type buried layer 3 are respectively formed. As shown in FIG. 3A, a field oxide film 6 for element isolation is provided on the wafer surface, and a gate oxide film 7 and a gate electrode 8 of the MOSFET are formed. Subsequently, ion implantation is performed on the MOS portion using the photoresist and the gate electrode as a mask, an n ⁻ -type low-concentration source / drain diffusion layer 9 is provided, and an oxide film deposited on the entire surface of the wafer is etched back to form a gate electrode 8. A side wall (side wall) 20 is formed.

Subsequently, as shown in FIG. 3B, after forming the base diffusion layer 11 by ion implantation, a graft base diffusion layer 23 is formed by ion implantation using an aluminum mask pattern 22.

Next, as shown in FIG. 3C, after forming an N ⁺ -type high-concentration source / drain diffusion layer 21 in the MOS portion, the oxide film 13 is formed.
Is formed on the entire surface of the wafer, and a contact hole is opened. Then, an arsenic-doped emitter electrode 15 is provided, and arsenic is diffused from the emitter electrode to form an emitter diffusion layer 17. After that, interlayer insulation film 24, aluminum wiring 25
Are sequentially formed.

[Problems to be solved by the invention]

In the conventional manufacturing method described in the previous section, when forming the sidewall of the MOSFET, the etch-back by RIE is performed in the bipolar transistor formation region (particularly, the emitter formation region).
Damages the silicon surface.

For this reason, in the etch-back process, a severe limitation that over-etching must be minimized has been imposed.

[Means for solving the problem]

In the manufacturing method of the present invention, in a method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOSFET are integrated on the same silicon substrate, first, a first insulating film serving as a side wall (sidewall) of the MOSFET is deposited on the entire surface of the wafer. After that, an opening is provided in the emitter formation region. Polycrystalline silicon is deposited on the entire surface of the wafer, and impurities are introduced therein. By diffusing this impurity into the silicon substrate by thermal diffusion, an emitter diffusion layer is formed.

After that, a second insulating film is deposited on the entire surface of the wafer, the second insulating film and the polycrystalline silicon film are etched using a photoresist pattern as a mask, and the polycrystalline silicon film covered with the second insulating film is etched. Is formed.
Subsequently, the first insulating film is etched back using the photoresist pattern as a mask to form a side wall (side wall) of the MOSFET. Further, ion implantation is performed in the MOS portion to form source and drain diffusion layers, and ion implantation is performed in the base region using the emitter electrode and the second insulating film thereon as a mask to form a graft base diffusion layer.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1A to 1I are cross-sectional views showing a semiconductor integrated circuit according to a first embodiment of the present invention in the order of manufacturing steps.
This semiconductor integrated circuit is an NPN type bipolar transistor and L
And an N-channel MOSFET having a DD structure.

First, as shown in FIG. 1 (a), a P-type silicon substrate 1
P by N ⁺ -type buried layer 2 and the boron by arsenic on the surface of
After each of the mold buried layers 3 are formed, N
A type epitaxial layer 4 is deposited.

Next, a P-well 5 is provided in a region where an N-channel MOSFET is formed and an isolation region. That is, after boron ions are implanted using the photoresist pattern as a mask, a high-temperature heat treatment is performed to form a deep P well 5.

Next, after a field oxide film 6 is provided in the element isolation region, a gate oxide film 7 is formed, and a gate electrode 8 made of phosphorus-doped polycrystalline silicon is provided in a MOS portion. Next, as shown in FIG. 1 (b), phosphorus ions are implanted using the photoresist pattern 10 and the gate electrode 8 as a mask to form N-type low-concentration source / drain diffusion layers 9 serving as LDD.

Next, as shown in FIG. 1C, boron ions are implanted using the photoresist pattern 12 as a mask to form the base diffusion layer 11.

Next, as shown in FIG. 1 (d), after a first insulating film (here, an oxide film) 13 as a material for the side wall is deposited on the entire surface of the wafer, openings are formed in the oxide film in the emitter formation region.
The silicon surface is exposed, and an emitter contact 14 is formed.

Next, as shown in FIG. 1E, a polycrystalline silicon film 15 serving as an emitter electrode is deposited on the entire surface of the wafer, and is doped with arsenic by ion implantation. At the emitter contact portion, arsenic diffuses from the polycrystalline silicon film 15 to the base diffusion layer 11 by a subsequent heat treatment,
To form Thereafter, an oxide film 18 as a second insulating film is grown on the entire surface of the wafer.

Next, as shown in FIG. 1 (f), using the photoresist pattern 19 as a mask, the oxide film 18 and the polycrystalline silicon film 15 (not shown) are etched to form an emitter electrode 16
To form By this etching, the oxide film 13 as the first insulating film is completely exposed in a region other than the emitter electrode portion.

Next, as shown in FIG. 1 (g), the first insulating film (oxide film 13) is etched back by anisotropic etching (RIE) using the photoresist pattern 19 as a mask. As a result, a side wall (side wall) 20 is provided on the gate electrode, and the emitter electrode 1 of the bipolar portion is formed.
6, the silicon surface of the portion not covered with the three-layer film of the oxide film 18 and the photoresist pattern 19 is exposed. here,
Since the region of the emitter diffusion layer is covered with the above-described three-layer film, it is not damaged by the etch back.

Next, as shown in FIG. 1 (h), after removing the photoresist pattern 19, arsenic ions are implanted into the MOS portion using the gate electrode 8 and the side wall 20 as a mask, and the N ⁺ -type high-concentration source is removed. , A drain diffusion layer 21 is provided. Subsequently, boron ions are implanted into the bipolar portion using the two-layered film of the emitter electrode 16 and the oxide film 18 and the aluminum pattern 22 as a mask, and the P ⁺ -type high-concentration graft base diffusion layer 23 is formed.
Is provided. At this time, the graft base diffusion layer 23 is formed in a self-aligned manner with respect to the emitter electrode 16. Since the emitter electrode 16 is formed almost according to the mask pattern, there is no need to allow for a dimensional margin between the graft base diffusion layer and the emitter diffusion layer at the time of design. Therefore, the distance between the base contact and the emitter contact can be reduced,
The parasitic capacitance and the parasitic resistance of the base portion are reduced. When boron ions are implanted, the upper surface of the emitter electrode 16 is
Is covered with the oxide film 18, which is an insulating film, so that boron of the opposite conductivity type is not implanted into the arsenic-doped emitter electrode 16. For example, for an ion implantation energy of boron of 30 to 50 keV, if the second insulating film 18 is an oxide film, 2000 to 4000 ° is sufficient.

Next, as shown in FIG. 1 (i), a semiconductor integrated circuit is formed by forming an interlayer insulating film 24 on the entire surface of the wafer, opening contact holes and providing aluminum wirings 25 in the same manner as in the conventional manufacturing method. Complete.

FIG. 2 is a sectional view showing a semiconductor integrated circuit according to a second embodiment of the present invention in the order of manufacturing steps.

In the present embodiment, a polycide film 26 in which a polycrystalline silicon film and a tungsten silicide film are stacked is used for a gate electrode in place of the polycrystalline silicon film serving as a gate electrode in the first embodiment.

Further, a nitride film can be used as the first insulating film which is a material of the side wall.

The manufacturing method is exactly the same as in FIGS. 1 (a) to 1 (i).

In this embodiment, since the polycide film having a small layer resistance is used, there is an advantage that the input resistance of the gate can be reduced.

〔The invention's effect〕

In the present invention, an emitter diffusion layer and an emitter electrode are formed before etch-back of a sidewall material of a MOSFET, and the three-layer pattern of the emitter electrode, an insulating film formed on the upper surface thereof, and a photoresist is used as an emitter diffusion layer. Since the sidewalls are etched back as a mask, the RIE does not damage the surface of the emitter diffusion layer (the deterioration of the characteristics of the bipolar transistor can be prevented).

Further, at the time of ion implantation at the time of forming the graft base, by using the two-layer pattern of the emitter electrode and the insulating film as a mask, the graft base diffusion layer can be formed in a self-aligned manner with respect to the pattern of the emitter electrode. As compared with the conventional manufacturing method, there is an effect of reducing the parasitic capacitance and the parasitic resistance of the base portion.

[Brief description of the drawings]

1 (a) to 1 (i) are cross-sectional views showing a semiconductor integrated circuit according to a first embodiment of the present invention in the order of manufacturing steps, and FIG. 2 is one manufacture of a semiconductor integrated circuit according to a second embodiment of the present invention. 3 (a) to 3 (c) are cross-sectional views showing a conventional semiconductor integrated circuit in the order of manufacturing steps. 1 ... P-type silicon substrate, 2 ... N ⁺ type buried layer, 3 ... P
Buried layer, 4 ... N-type epitaxial layer, 5 ... P well, 6 ... field oxide film, 7 ... gate oxide film, 8
... Gate electrode, 9... N ^- type low concentration source and drain diffusion layers, 10... Photoresist pattern, 11... Base diffusion layer, 12.
14 ... Emitter contact, 15 ... Polycrystalline silicon film, 16 ... Emitter electrode, 17 ... Emitter diffusion layer, 18 ...
... oxide film, 19 ... photoresist pattern, 20 ... side wall (side wall), 22 ... aluminum mask pattern, 23
…… P ⁺ type high concentration graft base diffusion layer, 24 …… Interlayer insulating film, 25 …… Aluminum wiring, 26 …… Polycide gate electrode, 27 …… Nitride film.

Claims (2)

(57) [Claims] In a method of manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOSFET are integrated on the same silicon substrate, a field oxide film for element isolation, a gate oxide film of the MOSFET, a gate electrode, and a base diffusion layer of the bipolar transistor are provided. Forming a first insulating film on the entire surface of the wafer, and providing an opening in the first insulating film on the emitter forming region of the bipolar transistor to expose the silicon substrate surface; Depositing a polycrystalline silicon film on the entire surface of the wafer and introducing impurities therein, diffusing the impurity from the polycrystalline silicon film into the silicon substrate in the opening, and forming an emitter diffusion layer; Forming a second insulating film; and using the photoresist pattern as a mask to form the second insulating film and the second insulating film. Etching a crystalline silicon film to form an emitter electrode made of the polycrystalline silicon covered with the second insulating film on the emitter diffusion layer; and forming the first insulating film using the photoresist pattern as a mask. Performing the etch back, providing a sidewall on the gate electrode of the MOSFET, exposing a portion of the silicon substrate surface not covered by the emitter electrode in the base region, and removing the photoresist pattern, and then removing the gate electrode and Forming a source / drain diffusion layer using the side wall as a mask; and performing a ion implantation into the base region using the second insulating film and the emitter electrode as a mask to form a graft base diffusion layer. Of manufacturing a semiconductor integrated circuit. 2. After the formation of the gate electrode, ions are implanted into the source / drain regions using the gate electrode as a mask to form a low-concentration impurity diffusion layer, and then the first insulating film is formed to form a MOSFET. 2. The method according to claim 1, wherein the semiconductor integrated circuit has an LDD structure.