JPH01191478A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To implement the setting of a threshold voltage value and a short channel, to prevent the increase in junction capacitance in source/drain diffusing layers and to make it possible to implement a high speed, by forming a diffused layer whose impurity concentration is different from that of substrate in a channel region directly beneath a gate electrode in a self-aligning mode. CONSTITUTION:A polycrystalline silicon layer 4 and an insulating film 5 of a silicon nitride film are laminated on a gate oxide film 3. With photoresist 6 as a mask, boron ions are implanted, and a P-type impurity diffused layer 7 is formed in a silicon substrate 1. Then, the silicon nitride film 5 at a region where a gate electrode is formed is removed. A silicon oxide film 8 is formed by oxidation. With the film 8 as a mask, the layer 4 is etched, and a gate electrode is formed. As ions are implanted by a self-aligned manner, and N-type source/drain diffusing layers 9 are formed. Then, an interlayer insulating film 10 is laminated. A metal wiring 11 is formed, and a MOS transistor is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing an MO3 type semiconductor device, and more particularly to a method for manufacturing an MO3 type transistor with a shortened channel.

[Conventional technology]

Conventionally, as a method for manufacturing this type of MOS transistor, as shown in FIGS. 3(a) to 3(d),
A method of diffusing impurities onto the surface of a semiconductor substrate of one conductivity type after forming a gate oxide film to partially vary the surface concentration is used.

That is, as shown in FIG. 3(a), for example, a field oxide film 2 is formed on a P-type silicon substrate 1 by a normal LOGO3 process.
A gate oxide film 3 with a thickness of 1.0 μm is formed in the active region.
After forming the silicon substrate 1, a P-type impurity such as boron is ion-implanted into the silicon substrate 1 through the gate oxide film 3 in order to set the threshold voltage or shorten the channel. An impurity diffusion layer 7 is formed.

Thereafter, as shown in FIG. 3(b), a polycrystalline silicon layer 4 of about 6,000 layers is deposited on the gate oxide film 3, and a photoresist 6 is formed thereon only in the region to become the gate electrode.

Then, as shown in FIG. 3(C), this photoresist 6
Using this as a mask, the polycrystalline silicon layer 4 is etched to form the gate electrode 4. This photoresist 6 is then removed. Next, using the gate electrode 4 as a mask, 10% of an impurity having a conductivity type opposite to that of the substrate, such as arsenic (As), is added.
0K e V, 1. The source/drain diffusion layer 9 is formed in a self-aligned manner with respect to the gate electrode 4 by ion implantation under the condition of OXIO 16 cm-''.

Thereafter, as shown in FIG. 3(d), about 5,000 layers of a glabellar insulating film 10 such as PSG is formed, contact holes are formed in this, and metal wiring 11 such as aluminum is formed to form an N-channel MO3. It formed a type transistor.

[Problem to be solved by the invention]

In the conventional manufacturing method described above, after forming the gate oxide film 3, the concentration of the P-type impurity diffusion layer 7 is increased by ion-implanting P-type impurities into the semiconductor substrate 1. Between the N-type source/drain diffusion layer 9 and the P-type impurity diffusion layer 7 formed in the substrate 7, the junction capacitance becomes larger due to the higher concentration than the normal substrate concentration, which is useful for forming high-speed transistors. This was a big problem.

An object of the present invention is to provide a method for manufacturing a semiconductor device that suppresses junction capacitance and enables high-speed transistors.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes a step of sequentially laminating a gate oxide film, a polycrystalline silicon layer, and an insulating film on a conductive type semiconductor substrate, and a process of sequentially laminating a gate oxide film, a polycrystalline silicon layer, and an insulating film on a conductive type semiconductor substrate, and using a mask formed on the insulating film to form a gate electrode. a step of introducing an impurity of one conductivity type into the surface of the semiconductor substrate where the gate electrode is to be formed to form an impurity diffusion layer; a step of selectively removing the insulating film in the gate electrode forming region using the mask; A step of forming a layer having different properties from the insulating film and polycrystalline silicon in a region where the insulating film has been removed in a self-aligned manner, and etching away the insulating film and the polycrystalline silicon layer using this layer having different properties as a mask. and a step of introducing impurities of opposite conductivity type into the semiconductor substrate in a self-aligned manner using the gate electrode to form source/drain diffusion layers.

[Effect]

In the above method, it is possible to form a diffusion layer with an impurity concentration different from that of the substrate only in the channel region directly under the gate electrode, and while it is possible to set the threshold voltage and shorten the channel, it also reduces the junction capacitance in the source/drain diffusion layer. It becomes possible to manufacture an MO3 type transistor that prevents the increase in the number of transistors.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(f) are cross-sectional views showing the first embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), for example, a field oxide film 2 of about 1.0 am is formed on a P-type silicon substrate 1 by a normal LOGO3 process to define an element region, and a field oxide film 2 is formed in this element region. Forms gate oxide film 3 by 500 people.

Next, as shown in FIG. 1(b), 4000 layers of polycrystalline silicon N4 and about 1000 layers of an insulating film 5 such as a silicon nitride film are formed on the entire surface. Then, a photoresist 6 is formed in a pattern with an opening in the region where the gate electrode is to be formed, and using this photoresist 6 as a mask, P-type impurities such as boron are ion-implanted into the silicon substrate 1. As a result, a relatively high concentration P-type impurity diffusion layer 7 is selectively formed in the silicon substrate 1.

Next, as shown in FIG. 1C, the silicon nitride film 5 in the area where the gate electrode is to be formed is removed using the photoresist 6 as a mask, and after removing the photoresist 6, oxidation is performed to expose the silicon nitride film 5. The surface of the polycrystalline silicon layer 4 thus formed is used as a silicon oxide film 8.

Subsequently, as shown in FIG. 1(d), the silicon nitride film 5 is completely removed.

Then, as shown in FIG. 1(e), the polycrystalline silicon layer 4 is etched using the silicon oxide film 8 as a mask to form a gate electrode, and N is etched in a self-aligned manner to the gate electrode. Type impurity, for example, As, is ion-implanted, and N
A type source/drain diffusion layer 9 is formed.

Next, as shown in FIG. 1(f), about 5,000 layers of the eyebrow insulating film 10 such as PSG are formed, contacts are made thereon, and metal wiring 11 made of aluminum or the like is formed to form the target semiconductor device. is completed.

In the MO3 type transistor manufactured in this way, the impurity diffusion layer 7 which is higher than the silicon substrate 1 is formed only in the region directly under the gate electrode 4, so that punch-through due to shortened channels is suppressed, and the source・Without increasing the junction capacitance between the drain diffusion layer 9 and the substrate,
It is said that high-speed operation of the transistor is possible.

FIGS. 2(a) to 2(f) are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps.

First, as shown in FIG. 2(a), a P-type silicon substrate 1 is
After forming a field oxide film 2 of 1.0 μm in thickness and forming a gate oxide film 3 of 500 layers in the element region, a polycrystalline silicon layer 4 of 4000 layers was formed on the entire surface as shown in FIG. 2(b).
A CVD silicon oxide film 12 is formed in approximately 1000 layers as an insulating film. Then, a photoresist 6 is provided on this,
Moreover, a region where a gate electrode will be formed later is opened in this photoresist.

Thereafter, using this photoresist 6 as a mask, ions of a P-type impurity, such as boron, are implanted into the surface of the silicon substrate 1 to form a P-type impurity diffusion layer 7.

Next, as shown in FIG. 2(c), the CVD silicon oxide film 12 is selectively removed using the photoresist 6, and epitaxial growth is then performed on the removed portion of the polycrystalline silicon layer 4. A silicon layer 13 is grown using a method. Furthermore, after removing the photoresist 6, a high melting point metal is applied thereon.

For example, a tungsten layer 14 is laminated.

Next, as shown in FIG. 2(d), after the tungsten layer 14 and the silicon layer 13 are reacted by heat treatment, the unreacted tungsten layer 14 is removed to form tungsten silicide N15.

Thereafter, as shown in FIG. 2(e), the polycrystalline silicon layer 4 is etched using the tungsten silicide layer 15 as a mask to form a gate electrode. Then, an N-type impurity, for example, As, is added in a self-aligned manner to the gate electrode 4.
By ion-implanting, an N-type source/drain diffusion layer 9 is formed.

Furthermore, as shown in FIG. 2(f), the PSG film 10 is
The desired MO3 type transistor is completed by forming a metal wiring 11 by forming contacts and forming a metal wiring 11.

The MO3 type transistor manufactured by this method can obtain all the same effects as the first embodiment, and has a gate electrode made of polycrystalline silicon and a tungsten silicide layer 15.
Since it has a two-layer structure, it is possible to reduce the resistance of the gate electrode and achieve even higher speeds.

Note that the tungsten silicide layer may be a silicide layer of a high melting point metal such as molybdenum.

〔Effect of the invention〕

As explained above, in the present invention, a diffusion layer having an impurity concentration different from that of the substrate can be formed in a self-aligned manner only in the channel region directly under the gate electrode, so that the threshold voltage can be set and the channel can be shortened. MO that enables high-speed operation by preventing an increase in junction capacitance in the source/drain diffusion layer
This has the effect of making it possible to manufacture type 3 transistors.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(f) are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, and FIGS. 2(a) to 2(f)
) is a sectional view showing the second embodiment of the present invention in the order of manufacturing steps, and FIGS. 3(a) to 3(d) are sectional views showing the conventional manufacturing method in the order of steps. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4... Polycrystalline silicon layer (
gate electrode), 5... silicon nitride film, 6... photoresist, 7... P type impurity diffusion layer, 8... silicon oxide film, 9... N type source/drain diffusion layer, 1
0... Interlayer insulating film, 11... Metal wiring, 12...
CVD silicon oxide film, 13... silicon layer, 14.
...Tungsten layer, 15...Tungsten silicide layer. Figure 1 Figure 1 Figure 2

Claims (1)

[Claims] 1. The step of sequentially laminating a gate oxide film, a polycrystalline silicon layer, and an insulating film on a semiconductor substrate of one conductivity type, and the surface of the semiconductor substrate at a location where a gate electrode is formed using a mask formed on the insulating film. a step of introducing an impurity of one conductivity type to form an impurity diffusion layer; a step of selectively removing the insulating film in the gate electrode forming region using the mask; and a step of selectively removing the insulating film in the gate electrode formation region; forming a layer having different properties from the insulating film and polycrystalline silicon in a self-aligned manner;
A step of etching away the insulating film and the polycrystalline silicon layer using the layers with different properties as a mask to form a gate electrode, and introducing impurities of opposite conductivity type into the semiconductor substrate in a self-aligned manner using the gate electrode. 1. A method of manufacturing a semiconductor device, comprising the step of forming a source/drain diffusion layer.