JPH0127589B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a complementary MOS device in which a semiconductor layer, such as a polycrystalline silicon layer, is sandwiched between a shallow diffusion layer of a complementary semiconductor device and a wiring metal. The present invention relates to a method for manufacturing a semiconductor device.

Conventionally, when aluminum is used as a wiring material, diffusion layers 5 and 6 and aluminum wiring 1 are in direct contact through contact holes formed in oxide film 9, as shown in FIG. In this case, in order to improve electrical contact between the aluminum wiring 1 and the diffusion layers 5 and 6, heat treatment is usually performed at a temperature of 400°C to 500°C, and this heat treatment will hereinafter be referred to as alloying. In the prior art structure, the alloy causes the silicon of the substrate to diffuse into the aluminum for wiring, and at the same time, the aluminum for wiring also diffuses into the silicon of the substrate, forming a thermal alloy reaction product of silicon and aluminum. This thermal alloy reactant is called an alloy spike, and the reaction progresses from the contact area toward the vicinity of the bond. Alloy spikes have the drawback of becoming deeper with the time of alloying and eventually causing deterioration phenomena such as PN junction leakage and junction breakdown. With the increasing integration of integrated circuits made of complementary MOS semiconductor devices, in recent years there has been a demand for smaller device dimensions and shallower diffusion layers of 0.5 μm or less, but conventional processes have the drawbacks mentioned above. Therefore, the depth of the diffusion layer cannot be reduced to less than 0.5 μm, which limits the high integration of integrated circuits made of complementary MOS semiconductor devices.

The present invention provides a novel method for manufacturing a complementary MOS semiconductor device that eliminates the above-mentioned drawbacks and enables high integration of integrated circuits made of complementary MOS semiconductor devices.

A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a well region of an opposite conductivity type in a silicon substrate of one conductivity type, and forming a first polycrystalline silicon gate for a first channel type first insulated gate field effect transistor. forming an electrode on the silicon substrate and a second polycrystalline silicon gate electrode for a second channel type second insulated gate field effect transistor on the well region through a gate insulating film; forming the first source/drain regions of opposite conductivity type in the silicon substrate using the first polycrystalline silicon gate electrode as a mask; forming a conductive type second source/drain region; covering the surfaces of the first and second polycrystalline silicon gate electrodes and the surfaces of the silicon substrate and the well region with an insulating layer; forming first to fourth contact holes, exposing a portion of the first polycrystalline silicon gate electrode through the first contact hole, and exposing a portion of the first source/drain region to the second contact hole; a portion of the second polycrystalline silicon gate electrode is exposed through the third contact hole; and a portion of the second source/drain region is exposed through the fourth contact hole. ion-implanting the impurity of the opposite conductivity type into the first polycrystalline silicon gate electrode through the first contact hole, and implanting the impurity into the first source/drain region shallower than the first source/drain region through the second contact hole. ion-implanting the impurity of one conductivity type into the second polycrystalline silicon gate electrode through the third contact hole and from the second source/drain region through the fourth contact hole; The method also includes a step of shallowly implanting ions, a step of forming a polycrystalline silicon layer to which no impurity is added in each contact hole, and a step of forming aluminum on the polycrystalline silicon layer and heat-treating it.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings while comparing it with the prior art. As shown in FIG. 2, the contact wiring according to the present invention has a two-layer structure of non-doped polycrystalline silicon 11 and aluminum wiring 1. As shown in FIG. Therefore, although the diffusion phenomenon of silicon into aluminum occurs due to the alloy, since the diffused silicon is supplied from the non-doped polycrystalline silicon 11, the diffusion layers 5 and 6 of the silicon substrate 3 are free from this phenomenon. becomes completely unrelated, and good PN junction characteristics are maintained. Further, as shown in FIGS. 3a and 3b, which are enlarged views of the contact hole, according to the conventional technique, the opened contact hole 15 is connected to the diffusion layer 5.
Or if it deviates from 6, aluminum wiring 1
will short-circuit the PN junction, making it impossible to obtain a good PN junction. However, as shown in FIGS. 4a and 4b, according to the present invention, even if the opened contact hole 15 is displaced from the diffusion layer 5 or 6, the silicon substrate 3 under the contact hole Since the diffusion layer 5a or 6a is formed in advance by ion implantation, there is no short-circuit accident as described above, and a good PN junction can be obtained.

Next, one embodiment of the method for manufacturing a novel complementary MOS semiconductor device of the present invention will be sequentially described using FIGS. 5 to 18. First, according to the conventional manufacturing method, as shown in FIG.
Silicon dioxide 9 is applied to the surface by thermal oxidation method etc.
The part where the P well is to be formed is selectively etched by photolithography, and then boron is deposited and driven in using the thermal diffusion method or ion implantation method as shown in FIG. 6 to form the P well 4. do. Next, as shown in FIG. 7, the silicon dioxide in the area where the device is to be formed is selectively etched by photolithography, and then, as shown in FIG. 8, a gate oxide film 10 is formed by thermal oxidation. Thereafter, polycrystalline silicon 12 is deposited by vapor phase growth or the like. Thereafter, as shown in FIG. 9, the polycrystalline silicon 12 is selectively etched by photolithography, leaving only the gate portions 7 and 8. As shown in FIG. 10, the silicon nitride film 13 is etched by CVD or the like.
is deposited on the entire surface so that it becomes a layer thick enough to serve as a mask when forming the diffusion layer of the N-type impurity region, and the portion that will become the N-type impurity region is selectively etched using photolithography. Etching. Thereafter, as shown in FIG. 11, source and drain diffusion layers 5 for N-type impurity regions are formed by thermal diffusion or ion implantation. At this time, the N-type impurity is also diffused into the polycrystalline polysilicon 8 in the N-type impurity region. Thereafter, as shown in FIG.
selectively etched. Thereafter, as shown in FIG. 13, source/drain diffusion layers 6 are formed with P-type impurities in the P-type impurity region 30 by thermal diffusion or ion implantation. At this time, the P-type impurity is also diffused into the polycrystalline silicon 7 in the P-type impurity region. After that, as shown in FIG. 14, after forming a contact hole at a predetermined position, the surface of the N-type impurity region 31 is masked with a photoresist or the like, so that the contact hole portion of the P-type impurity region 30 is formed into a P-type. Impurity ions are implanted as indicated by arrows 20 to provide a P-type diffusion layer 6a in the silicon substrate below the contact hole of the P-type impurity region 30. Thereafter, after peeling off the photoresist masking the surface of the N-type impurity region 31, the surface of the P-type impurity region 30 is masked with a photoresist or the like.
N-type impurity ions are implanted into the contact hole portion of No. 1 in the direction indicated by the arrow 21, and the N-type impurity region 31 is
An N-type diffusion layer 5 is formed on the silicon substrate under the contact hole.
A is provided, and the photoresist masking the surface of the N-type impurity region 31 is peeled off. Thereafter, as shown in FIG. 15, polycrystalline silicon 11 with a thickness of about 500 Å to 3000 Å is grown over the entire surface by vapor phase growth or the like.
After this, as shown in FIG. 16, wiring aluminum 14 is deposited on the polycrystalline silicon 11 by vacuum evaporation or the like. Thereafter, as shown in FIG. 17, predetermined wirings 1 and 2 are formed by a photolithography process, and as shown in FIG. 18, using the wiring metals 1 and 2 as masks, the polycrystalline silicon 11
is selectively removed and heat treated to improve electrical contact. In this way, a complementary MOS semiconductor device is obtained. In this way, the complementary type according to the present invention
By using the manufacturing method of MOS semiconductor devices,
A complementary MOS semiconductor device having the above-mentioned advantages can be obtained.

[Brief explanation of drawings]

Figure 1 shows a silicon gate complementary type using conventional technology.
FIG. 2 is a cross-sectional view of a MOS semiconductor device, and FIG. 2 is a silicon gate complementary type, which is an embodiment based on the present invention.
FIG. 2 is a cross-sectional view of a MOS semiconductor device. Furthermore, FIGS. 3a and 3b are a plan view and a cross-sectional view taken along arrow A-A' of the contact portion when the diffusion layer and the contact hole are misaligned according to the prior art, and FIGS. FIG. 4b is a plan view and a sectional view taken along the line B-B' of the contact portion according to the present invention when the diffusion layer and the contact hole are misaligned. FIGS. 5 to 18 are diagrams illustrating, step by step, a method for manufacturing a complementary MOS semiconductor device according to an embodiment of the present invention. In the figure, 1... lead-out aluminum wiring for source and drain, 2... aluminum gate electrode, 3... N-type silicon substrate, 4...
P well, 5...N-type diffusion layer, 6...P-type diffusion layer, 7...Silicon gate electrode in P-type impurity region, 8...Silicon gate electrode in N-type impurity region, 9...Dioxide in field part Silicon, 10
...Silicon dioxide for gate portion, 11...Non-doped polycrystalline silicon for wiring, 12...Polycrystalline silicon for gate electrode, 13...Silicon nitride film, 14...Aluminum for wiring, 15...Opened hole Contact part, 20, 21...each P
Arrows 30, 31 indicating the state of ion implantation of type and N type impurities indicate portions constituting P type and N type impurity regions, respectively.

Claims (1)

[Claims] 1. A step of forming a well region of an opposite conductivity type in a silicon substrate of one conductivity type, and a step of forming a well region of a first channel type.
a first polycrystalline silicon gate electrode for an insulated gate field effect transistor on the silicon substrate and a second polycrystalline silicon gate electrode for a second channel type second insulated gate field effect transistor on the well region. , a step of forming the first source/drain region of the opposite conductivity type on the silicon substrate using the first polycrystalline silicon gate electrode as a mask, and a step of forming the first source/drain region of the opposite conductivity type on the silicon substrate using the first polycrystalline silicon gate electrode as a mask. forming the second source/drain region of one conductivity type in the well region using the crystalline silicon gate electrode as a mask;
covering the surfaces of the first and second polycrystalline silicon gate electrodes and the surfaces of the silicon substrate and the well region with an insulating layer; forming first to fourth contact holes in the insulating layer;
A portion of the polycrystalline silicon gate electrode is exposed through the first contact hole, a portion of the first source/drain region is exposed through the second contact hole, and the second polycrystalline silicon gate electrode is exposed through the second contact hole. exposing a portion of the second source/drain region through the third contact hole and exposing a portion of the second source/drain region through the fourth contact hole; implanting ions into the first polycrystalline silicon gate electrode through the hole and implanting ions into the first source/drain region through the second contact hole; A step of implanting ions into the second polycrystalline silicon gate electrode through the third contact hole and implanting ions shallower than the second source/drain region through the fourth contact hole, and then adding impurities. 1. A method of manufacturing a semiconductor device, comprising: forming a polycrystalline silicon layer in each contact hole; and forming aluminum on the polycrystalline silicon layer and heat-treating the layer.