JP2720553B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOS transistor having an improved structure.

[Conventional technology]

In order to reduce the size and the performance of MOS integrated circuit devices, it is important to reduce the distance between the gate electrode and the contact holes on the source and drain diffusion layers and to reduce the resistance of the source and drain diffusion layers.

To solve this problem, a self-aligned contact technology [“Self-Aligned-Contact Tachnology for
High Density MOS VLSI ", Sympo, on VLSI Tech.Digest,
P.34, (1983)]. FIG. 4 shows a cross-sectional structure of a MOS transistor according to the present technology. Polycrystalline silicon for electrode extraction is disposed in a self-aligned manner on the gate electrode, and is disposed so as to cover the entire surface of the source and drain diffusion layers. Therefore, the contact hole between the upper aluminum wiring and the source and drain is formed by the gate electrode. It can be arranged without being limited to the interval between. The resistance added to the source and the drain becomes a parallel resistance value of the polycrystalline silicon and the diffusion region, and effectively decreases.

[Problems to be solved by the invention]

The above-described conventional semiconductor device has the following disadvantages.

(1) In the transistor having the structure shown in FIG. 4, since the polycrystalline silicon film of the same layer is disposed on the source and the drain, the separation distance between the source electrode and the drain electrode is equal to the distance 1 Is determined. Assuming that this distance 1 is the minimum dimension of the processing technique used, the width (channel length) L of the gate electrode of the MOS transistor becomes larger than 1 and the minimum processing dimension cannot be used as the channel length of the MOS transistor. This is an obstacle to miniaturization.

(2) In order to miniaturize the transistor, particularly to reduce the channel length, the depth of the source and drain diffusion layers must be reduced. When the depth of the diffusion layer becomes shallower, a problem arises in that the junction withstand voltage of the source and the drain decreases. To avoid this, it is preferable to lower the power supply voltage and operate the device in a voltage range sufficiently lower than the junction withstand voltage. However, one type of power supply is often used in a system using a plurality of conventional semiconductor devices, and it is difficult to use a semiconductor device that requires a different low-voltage power supply than the conventional one. As a means for solving this problem, there is a method in which the interface with the outside of the semiconductor device is operated by the conventional power supply voltage and the inside of the device is operated by the stepped down internal power supply. In order to realize such a device, a fine transistor with a small diffusion layer depth is used in a highly integrated region, and a transistor with a large diffusion layer depth and a high junction breakdown voltage is used in the interface with the outside. It is desirable to do. In the device shown in FIG. 4, since the source and drain diffusion layers of all the transistors are formed by the same impurity diffusion from the same polycrystalline silicon film, it is difficult to form diffusion layers having two different depths.

[Means for solving the problem]

According to the present invention, the first conductive material is provided in contact with one of the source and drain diffusion layers of the MOS transistor formed on the semiconductor substrate, and the other of the diffusion layers is provided with the first conductive material. A second conductive material, which is a different material from the first conductive material and is a different layer, is provided in contact with the first conductive material, and a contact selectively formed on the interlayer insulating layer is provided on the first and second conductive materials. First and second wirings for source and drain diffusion layers are provided through holes, respectively, and the one diffusion layer has a greater depth than the other diffusion layer, and A junction voltage of the other diffusion layer is larger than the junction voltage of the other diffusion layer.

Further, according to the present invention, a semiconductor substrate is provided with a first MOS transistor operating at a first power supply voltage and a second MOS transistor operating at a second power supply voltage lower than the first power supply voltage. , The second MOS transistor is basically constructed as described above, while the first MOS transistor has its source and drain diffusion layers replaced by the other diffusion layer of the second MOS transistor. And the junction withstand voltage is set to be larger than the junction withstand voltage of the other diffusion.

In contrast to the above-described conventional device, the present invention provides: (1) A first conductive material is disposed so as to be in contact with the entire surface of the source / drain diffusion layer in a desired region, and the source / drain diffusion layer in the other region The second conductive material is disposed so as to be in contact with the entire surface. That is, the layer of the conductive material disposed on the surface of the diffusion layer is selectively used depending on the region on the same semiconductor substrate.

(2) The depth of the source and drain diffusion layers under the first conductive material and the depth of the source and drain diffusion layers under the second conductive material can be easily made different from each other, and the interface with the outside having a high power supply voltage. In this case, a transistor having a large diffusion depth and a high junction breakdown voltage is obtained, and a transistor having a small diffusion layer depth is obtained inside a highly integrated device operated at a low power supply voltage.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention. In this embodiment, the present invention is applied to one N-channel MOS transistor. A gate insulating film 2 and a polycrystalline silicon gate electrode 3 are provided on a P-type single crystal silicon substrate 1. A drain diffusion layer is formed of an n ⁻ -type impurity region 5 made of phosphorus and a shallow n ⁺ -type impurity region 12 made of arsenic. A drain electrode extraction polycrystalline silicon film 8 is arranged so as to be in contact with the entire surface of the drain diffusion layer. The source diffusion layer is formed of an n ⁻ -type impurity region 5 made of phosphorus and a deep n ⁺ -type impurity region 13 made of phosphorus. The source electrode extraction tungsten silicide film 11 is arranged so as to be in contact with the entire surface of the source diffusion layer. The contact hole 16 on the source electrode for connection with the aluminum wiring 17 in the upper layer is formed of the tungsten silicide film 11.
Above, the contact hole 15 on the drain electrode is provided on the polycrystalline silicon film 8.

FIGS. 2 (a) to 2 (c) are longitudinal sectional views of the main process,
A method for manufacturing the device of this embodiment will be described. A gate insulating film 2 and a polycrystalline silicon film are sequentially grown on a P-type single crystal silicon substrate 1, and the polycrystalline silicon film is patterned using a silicon oxide film 4 as a mask to form a polycrystalline silicon gate electrode 3. Using the silicon oxide film 4 and the polycrystalline silicon gate electrode 3 as masks, phosphorus, which is an n-type impurity, is ion-implanted into the future source and drain regions at an acceleration energy of 5 × 10 ¹³ / cm ² , 50 keV, and n A negative impurity region 5 is formed to obtain FIG. 2 (a).

Then, a 1000 mm thick CVD silicon oxide film 6 is grown on the entire surface, the source region is covered with a photoresist, and the CVD silicon oxide film 6 is etched back by 1000 mm by anisotropic etching. At the same time as the exposure,
A sidewall 7 of a CVD silicon oxide film is formed.
After removing the photoresist, a polycrystalline silicon film 8 is formed to a thickness of 2000.degree.
Ion implantation is performed at an acceleration energy of × 10 ¹⁶ / cm ² and 50 keV. Thereafter, the polycrystalline silicon film 8 is patterned into a desired electrode shape by masking the CVD silicon oxide
Figure (b) is obtained.

Next, after growing a CVD silicon oxide film having a thickness of 1000 mm, the CVD silicon oxide film having a thickness of 1000 mm and the silicon oxide film 6 remaining on the source region are etched back by anisotropic etching. At the same time as the surface is exposed, a sidewall 10 of a CVD silicon oxide film is formed on the side wall of the gate electrode on the source region side. afterwards
A tungsten silicide film 11 is grown to a thickness of 2000 mm,
Phosphor which is an n-type impurity is ion-implanted over the entire surface at an acceleration energy of 1 × 10 ¹⁶ / cm ² and 50 keV. When subsequently subjected to heat treatment in a nitrogen atmosphere at 900 ° C., polycrystalline arsenic silicon film 8, also shallow phosphorus tungsten silicide film 11 by the arsenic in the drain region due to the difference in diffuse the diffusion coefficient into silicon substrate n ⁺ A deep n ⁺ impurity region 13 of phosphorus is formed in the type impurity region 12 and the source region. Thereafter, the tungsten silicide film 11 is patterned into a desired electrode shape to obtain FIG. 2 (c).

Next, an interlayer insulating film 14 is grown, and a contact hole 15 on the drain electrode and a contact hole 16 on the source electrode are opened,
The aluminum wiring 17 is formed to complete the device shown in FIG.

In the device of the present embodiment, the contact hole 16 on the source electrode can be opened so as to overlap the gate electrode 3. Therefore, the alignment margin required for the normal PR technology is not required, which is suitable for high integration. Further, the tungsten silicide film 11 for extracting the source electrode and the polycrystalline silicon film 8 for extracting the drain electrode are independent layers and are insulated from each other by a silicon oxide film. Therefore, the width (channel length) of the gate electrode 3 is not limited by the existence of the conductive layer on the source and the drain.

In this embodiment, a polycrystalline silicon film and a tungsten silicide film are used as the first and second conductive layers for extracting the source and drain electrodes. However, the conductive layer can be arbitrarily selected depending on the case. is there. Although arsenic and phosphorus are used as impurities for forming the n ⁺ diffusion layer, it can be realized with only arsenic or only phosphorus. In this embodiment, an N-channel type MOS transistor is described. However, the present invention can be applied to a P-channel type and a CMOS type device.

 FIG. 3 is a longitudinal sectional view of a second embodiment of the present invention.

In this embodiment, an N-channel MOS transistor Q1 having a deep n ⁺ -type impurity region in the source and drain and the N-channel MOS transistor Q2 described in the first embodiment are formed on the same base. The details of the manufacturing method and the name of each part are the same as those described in the first embodiment with reference to FIGS.

In the MOS transistor Q1, the tungsten silicide film 11 and the deep n ⁺
It has a type impurity region 13. The MOS transistor Q1 has a tungsten silicide film on the source side so that it contacts the entire surface.
11 and has a deep n ⁺ impurity region 13 has a shallow n ⁺ -type impurity region 12 and the polycrystalline silicon film 8 in contact with the entire surface on the drain side.

According to the present embodiment, in a large-scale integrated circuit, a portion requiring a high junction withstand voltage such as an interface with the outside is constituted by the MOS transistor Q1, and a portion requiring high integration inside the LSI has a low drain withstand voltage. Can be configured with a MOS transistor Q2 suitable for miniaturization. The MOS transistor Q1 is directly driven by an external power supply, and the MOS transistor Q2 is driven by a reduced internal low voltage.

The combination of the depth of the n ⁺ impurity region and the conductive layer disposed so as to be in contact with the surface of the source / drain diffusion layer is not limited to the present embodiment, but may be varied depending on the purpose. Such a combination can be appropriately selected without departing from the gist of the present invention.

〔The invention's effect〕

As described above, according to the present invention, by using two different types of conductive materials for extracting source and drain electrodes of a plurality of MOS transistors formed on the same substrate, only one conductive material can be used. (1) There is no inconvenience that the spacing between the extraction electrodes in the same layer limits the fine processing and prevents miniaturization of the device. That is, a semiconductor device smaller than before can be realized.

(2) Source and drain diffusion layers can be formed by impurity diffusion from two types of conductive layers, and diffusion layers having different depths can be easily realized on the same base.

This has the effect.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, and FIG.
FIGS. 3A to 3C are cross-sectional views of main steps for explaining a method of manufacturing the device of the first embodiment, FIG. 3 is a vertical cross-sectional view of the second embodiment of the present invention, and FIG. FIG.

Claims (3)

(57) [Claims] In a semiconductor device having a MOS transistor on a semiconductor substrate, a first conductive material is provided in contact with one of a source and a drain diffusion layer of the MOS transistor, and the source and the drain are provided. A second conductive material, which is a different material from the first conductive material and is different from the first conductive material, is provided in contact with another of the diffusion layers, and an interlayer covering the first and second conductive materials is provided. Contact holes exposing portions of the first and second conductive materials are respectively formed in the insulating layer, and contact holes are respectively formed through the contact holes with the portions of the first and second conductive materials. First and second wirings for the source and drain diffusion layers are formed, and the one diffusion layer has a greater depth than the other diffusion layer. The semiconductor device junction withstand voltage of one of the diffusion layer and said semiconductor substrate being larger than the junction breakdown voltage between the other diffusion layer and the semiconductor substrate. 2. A semiconductor device having, on a semiconductor substrate, a first MOS transistor operating at a first power supply voltage and a second MOS transistor operating at a second power supply voltage lower than the first power supply voltage. Wherein a first conductive material is provided in contact with one of the source and drain diffusion layers of the second MOS transistor, and the other of the source and drain diffusion layers is provided with the first conductive material. A second conductive material, which is a material different from the first conductive material and is a different layer, is provided in contact with the wiring, and a wiring is formed on the second conductive material in contact with the second conductive material. The first diffusion layer has a depth greater than that of the other diffusion layer and a junction withstand voltage between the one diffusion layer and the semiconductor substrate is larger than a junction withstand voltage between the other diffusion layer and the semiconductor substrate; MOS type transformer Each of the source and drain diffusion layers of the star has a greater depth than the other diffusion layer of the second MOS transistor, and has a junction withstand voltage with the semiconductor substrate of the second MOS transistor. A semiconductor device characterized by being larger than a junction withstand voltage between the other diffusion layer and the semiconductor substrate. 3. The semiconductor device according to claim 1, wherein each of the first and second conductive materials contains an impurity, and an impurity contained in the first conductive material is different from an impurity contained in the second conductive material. 3. The semiconductor device according to claim 1, wherein: