JPH03157939A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form diffused layers in different depths for miniaturizing the device by a method wherein the conductive material comprising the two kinds of different layers is provided for leading-out the source and drain electrodes of MOS transistors formed on the same substrate. CONSTITUTION:A polycrystal Si gate electrode 3 is formed on a P type single crystal Si substrate 1 using a gate insulating film 2 and an Si oxide film 4 as masks while P is implanted using the film 4 and the electrode 3 as masks to form n<->type impurity regions 5. Another Si oxide film 6 is deposited on the whole surface and then processed to form sidewall 7; a polycrystal Si film 8 is deposited; and after implanting arsemic, an electrode leading-out film 8 is formed using the other Si oxide film 9 as a mask. Next, the film 6 is processed to form another sidewall 10, a W silicide film 11 is deposited; P is implanted in the whole surface to be heat-treated so as to form shallow and deep n<+>type impurity regions 12, 13 respectively in drain and source regions. Finally, an interlayer insulating film 14, contact holes 15, 16 and Al wiring 17 are formed. Through these procedures, diffused layers in different depths can be formed on the same substrate thereby enabling the device to be miniaturized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a MOS transistor having an improved structure.

[Conventional technology]

In order to advance the miniaturization and performance improvement of MOS type integrated circuit devices, important issues are: - Reducing the distance between the gate electrode and the contact hole on the source and drain diffusion layers; and - Reducing the resistance of the source and drain diffusion layers. .

As a way to solve this problem, self-line contact technology [: ” 5elf-Aligned-Co
ntact Technology for High
h Density MOS VLSI”, Sym
po,on VLSITech,DigesL,P,
34. (1982)) have been proposed. FIG. 4 shows a cross-sectional structure of a MOS transistor according to the present technology. Polycrystalline silicon for electrode extraction is placed in self-alignment with the gate electrode, and is placed so as to cover the entire source and drain diffusion layers. ■The contact hole between the upper layer aluminum wiring and the source and drain is connected to the gate electrode. It can be installed without being restricted by the distance between the electrodes. ■The resistance added to the source and drain becomes the parallel resistance value of the polycrystalline silicon and the diffusion region, and is effectively reduced.

[Problem to be solved by the invention]

The conventional semiconductor device described above has the following drawbacks.

(1) The transistor with the structure shown in FIG. 4 has a source,
Since the polycrystalline silicon film of the same layer is disposed on the drain, the separation distance between the source electrode and the drain electrode is determined by the distance 1 of the polycrystalline silicon. If this distance β is the minimum dimension of the processing technology used, then the width L of the gate electrode (channel length) of the MOS transistor is from l.

This also increases, making it impossible to use the minimum processing dimension as the channel length of a MOS transistor, which becomes an obstacle to miniaturization.

(2) In order to miniaturize a transistor, especially to reduce the channel length, the depth of the source and drain diffusion layers must be reduced. When the depth of the diffusion layer becomes shallow, the source
A decrease in the drain junction breakdown voltage becomes a problem. To avoid this, it is better to lower the power supply voltage and operate the device in a voltage range sufficiently lower than the junction breakdown voltage. However, conventional systems that use a plurality of semiconductor devices often use one type of power supply, and it is difficult to use semiconductor devices that require a low-voltage power supply different from conventional ones. As a means to solve this problem, there is a method in which the interface section with the outside of the semiconductor device is operated with a conventional power supply voltage, and the inside of the device is operated with a reduced voltage internal power supply. In order to realize such a device, it is necessary to use small transistors with a small diffusion layer depth in the internal highly integrated area, and use transistors with a large diffusion layer depth and high junction breakdown voltage in the interface area with the outside. It is desirable to do so. In the device shown in FIG. 4, the source and drain diffusion layers of all transistors are formed by the same impurity diffusion from the same layer of polycrystalline silicon film, so it is difficult to create diffusion layers of two different depths.

[Means to solve the problem]

The semiconductor device of the present invention has a plurality of MOS transistors on a semiconductor substrate of one conductivity type, and a first conductive material is applied so as to be in contact with the entire surface of the semiconductor substrate in desired regions of the source and drain diffusion layers. A second conductive material is disposed so as to be in contact with the entire surface of the semiconductor substrate in regions of the source and drain diffusion layers that are not covered with the first conductive material.

Further, in the device of the present invention, the diffusion layer covered with the first conductive material and the diffusion layer covered with the second conductive material are formed at different depths.

In contrast to the conventional device described above, in the present invention, (1) the first conductive material is arranged so as to be in contact with the entire surface of the source and drain diffusion layers in desired regions, and the first conductive material is placed in contact with the entire surface of the source and drain diffusion layers in other regions. The second layer should be in contact with the entire surface.
conductive material.

That is, the layer of conductive material disposed on the surface of the diffusion layer is used differently depending on the region on the same semiconductor substrate.

(2) The depth of the source/drain diffusion layer 5 under the first conductive material and the depth of the source/drain diffusion layer under the second conductive material can be easily set to different depths.

It has the following characteristics.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. In this embodiment, the present invention is applied to one N-channel type MOS transistor. A gate insulating film 2 is formed on a P-type nested crystal silicon substrate 1. The gate electrode 3 is made of polycrystalline silicon, and the drain diffusion layer is an n-type impurity region 5 made of phosphorus.
A polycrystalline silicon film 8 for drawing out the drain electrode is arranged so as to be in contact with the entire surface of the drain diffusion layer. deep n+ by phosphorus
A tungsten silicide film 11 for drawing out the source electrode is arranged so as to be in contact with the entire surface of the source diffusion layer. Upper layer aluminum wiring 17
A contact hole 16 on the source electrode for connection with the tungsten 6-reside film 11 is formed on the contact hole 15 on the drain electrode.
is provided on the polycrystalline silicon film 8.

The manufacturing method of the device of this example will be explained using the longitudinal sectional views of main steps shown in FIGS. 2(a) to 2(c). A gate insulating film 2 is formed on a P-type nested crystal silicon substrate 1. A polycrystalline silicon film is sequentially grown, and the polycrystalline silicon film is patterned using the silicon oxide film 4 as a mask to form a polycrystalline silicon gate electrode 3. Using the silicon oxide film 4 and the polycrystalline silicon gate electrode 3 as a mask, phosphorus, which is an n-type impurity, is added to the regions that will become the source and drain in the future at 5×10”/c♂.
Ion implantation is performed at an acceleration energy of 50 keV to form an n-type impurity region 5, as shown in FIG. 2(a).

In the next step, after growing a CVD silicon oxide film 6 with a thickness of 1000 nm over the entire surface, the source region is covered with a photoresist.
CVD silicon oxide film 6 is etched by anisotropic etching.
Etching back by 0.000 mm exposes the surface of the silicon substrate in the drain region, and at the same time forms a CVD silicon oxide film sidewall 7 on the side wall of the gate electrode on the drain region side.
is formed. After removing the photoresist, 2000
A polycrystalline silicon film 8 is grown to a human thickness, and arsenic, which is an n-type impurity, is doped over the entire surface at I x 1016/cf, 50
Ion implantation is performed with keV acceleration energy. Thereafter, using the CVD silicon oxide film 9 as a mask, the polycrystalline silicon film 8 is patterned into a desired electrode shape, as shown in FIG.
).

Next, after growing a CVD silicon oxide film with a thickness of 1000 nm, a CVD silicon oxide film with a thickness of 1000 nm was grown by anisotropic etching.
When the silicon oxide film 6 left on the silicon oxide film and the source region is etched back, the silicon substrate surface of the source region is exposed and at the same time a side wall 10 of the CVD silicon oxide film is formed on the side wall of the gate electrode on the source region side. is formed.

Then tungsten silicide film 1 to 2000 people thick
1 is grown, and phosphorus, which is an n-type impurity, is grown on the entire surface.
Ions are implanted with an acceleration energy of 016/c+fl, 50 ke'/. When heat treatment is then performed in a nitrogen atmosphere at 900°C, arsenic from the polycrystalline silicon film 8 and phosphorus from the tungsten silicide film 11 diffuse into the silicon substrate, and due to the difference in diffusion coefficient, arsenic forms a shallow n+ type in the drain region. Impurity region 12. A deep n+ impurity region 13 made of phosphorus is formed in the source region. Thereafter, the tungsten silicide film 11 is patterned into a desired electrode shape, as shown in FIG. 2(c).

Next, an interlayer insulating film 14 is grown to form a contact hole 15 on the drain electrode. A contact hole 16 above the source electrode is opened and an aluminum wiring 17 is formed to complete the device shown in FIG.

In the device of this embodiment, the contact hole 16 on the source electrode can be formed to overlap the gate electrode 3. Therefore, there is no need for alignment margin required in normal PR technology, making it suitable for high integration. Further, since the tungsten silicide film 11 for leading out the source electrode and the polycrystalline silicon film 8 for leading out the drain electrode are independent layers and are insulated from each other by a silicon oxide film, there are no restrictions on their mutual arrangement. Therefore, the width (channel length) of the gate electrode 3 is not limited by the presence of the 9- conductive layer on the source and drain.

In this example, a polycrystalline silicon film and a tungsten silicide film were used as the first and second conductive layers for leading out the source and drain electrodes, but the conductive layers can be arbitrarily selected depending on the case. be. Although arsenic and phosphorus were used as impurities for forming the n+ diffusion layer, it can also be realized using only arsenic or only phosphorus. Furthermore, although this embodiment describes an N-channel type MOS transistor, the present invention can also be applied to P-channel type and OMOS type devices.

FIG. 3 is a longitudinal sectional view of a second embodiment of the invention.

This embodiment consists of an N-channel MOS transistor Q1 having deep n+ type impurity regions in the source and drain, and an N-channel MOS transistor Q2 described in the first embodiment.
were fabricated on the same substrate. The details of the manufacturing method and the names of each part are the same as those explained in FIGS. 1 and 2 in the first embodiment, and therefore will be omitted.

10-MOS) The transistor Q1 has a tungsten silicide film 11 and a deep n+ type impurity region 13 in contact with the entire surface of the source and drain diffusion layers.

MOS) transistor Q1 has a tungsten silicide film 11 and a deep n+ impurity region 13 on the source side so as to be in contact with the entire surface, and a polycrystalline silicon film 8 and a shallow n+ type impurity region 12 on the drain side so as to be in contact with the entire surface. have

According to this embodiment, in a large-scale integrated circuit, parts that require a high junction breakdown voltage, such as an interface with the outside, are constructed with a MOS transistor Q1, and parts that require high integration inside the LSI are constructed with a drain breakdown voltage. It can be constructed with a transistor Q2 (MOS transistor) which is low in cost but suitable for miniaturization. M.O.
S) Transistor Q2 is directly driven by an external power supply and is a MOS
) The transistor Q1 is driven by a stepped down internal low voltage.

The combination of the depths of the conductive layer and the n+ impurity region arranged so as to be in contact with the surfaces of the source and drain diffusion layers is not limited to this embodiment, and may be determined depending on the purpose. Such combinations can be selected as appropriate without departing from the gist of the present invention.

[Effects of the Invention] As explained above, the present invention uses two different layers of conductive materials for drawing out the source and drain electrodes of a plurality of MOS transistors formed on the same substrate. - Compared to the case where a layer-only conductive material is used as an extraction electrode, (1) there is no inconvenience that the interval between extraction electrodes of the same layer becomes a restriction on microfabrication, which prevents miniaturization of the device; In other words, it is possible to realize a semiconductor device that is smaller than the conventional one.

(2) Source and drain diffusion layers can be formed by impurity diffusion from two types of conductive layers, and diffusion layers with different depths can be easily realized on the same substrate.

There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a vertical sectional view of an embodiment of the cylinder 1 of the present invention, and FIG. 2(a)
~(c) are main process sectional views for explaining the manufacturing method of the device of the first embodiment, FIG. 3 is a longitudinal sectional view of the embodiment of the tube 2 of the present invention, and FIG. 4 is a longitudinal sectional view of the conventional device. It is a diagram.

Claims (1)

[Claims] (1) A plurality of MOS transistors are provided on a semiconductor substrate of one conductivity type, and a first conductive material is applied so as to be in contact with the entire surface of the semiconductor substrate in desired regions of the source and drain diffusion layers of the MOS transistors. and a second conductive material is disposed so as to be in contact with the entire surface of the semiconductor substrate in regions of the source and drain diffusion layers that are not covered with the first conductive material (2). 2. The semiconductor device according to claim 1, wherein the depth of the diffusion layer covered with the first conductive material is different from the depth of the diffusion layer covered with the second conductive material.