JP2596117B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an MIS field effect in which a source / drain diffusion layer region is composed of a low impurity concentration region close to a channel formation region and a high impurity concentration region other than the low impurity concentration region. Transistor (FE
The present invention relates to a method for manufacturing a semiconductor integrated circuit including T).

[Conventional technology]

In order to increase the breakdown voltage of MIS type FETs, a structure in which a diffusion layer region of the same conductivity type and a relatively low impurity concentration is provided at the end of the source / drain diffusion layer region on the channel formation region side is widely used at present. I have. 2 (a) to 2 (e) show a method of introducing impurities into the source / drain regions in a method of manufacturing a MOS FET having such a structure. First, phosphorus 4 is ion-implanted at a low dose of about 1 × 10 ¹³ / cm ^{2 using} a polycrystalline silicon gate electrode 3 formed on a P-type silicon substrate 1 via a gate oxide film 2 as a mask. FIG. 2 (a)). Next, after a region to be a low impurity concentration region in the gate electrode 3 and the source / drain diffusion layers is covered with the photoresist film 5 (FIG. 2B), the region
Phosphorus ion implantation is performed again at a high dose of about × 10 ¹⁵ / cm ² (FIG. 2C). Next, after the photoresist film 5 is removed (FIG. 2 (d)), a heat treatment is performed.
A source / drain diffusion layer region of a high breakdown voltage structure MOS type FET having low impurity concentration and high impurity concentration N-type diffusion regions 6 and 7 is formed (FIG. 2E). MO including source / drain low impurity concentration diffusion layer 6 formed by the above steps
When the S-type FET is used, the electric field concentration in the drain diffusion layer is reduced as compared with a normal MOS-type FET, so that the withstand voltage between the source and the drain is improved.

By the way, in a recent semiconductor integrated circuit device, the MIS type FET for the purpose of high breakdown voltage and the fine MIS type FET for the purpose of high speed and high integration are integrated on the same substrate. Technology is important. However, when integrating an FET for high speed and high integration and an FET for high breakdown voltage on the same substrate, it is necessary to overcome the following problems. That is, the FET for high speed and high integration needs to have a relatively thin gate insulating film, and the FET for high breakdown voltage needs to be relatively thick.
However, in the conventional semiconductor device, the above two types of
Since the FETs were formed on the same gate dielectric film, it was extremely difficult to satisfy high speed, high integration, and high breakdown voltage simultaneously. Therefore, as a means for overcoming this problem, a semiconductor device having a structure having two or more gate dielectric films on the same substrate is disclosed in Japanese Patent Application No. 63-201473, filed by the present applicant. It is described in the specification. Third
FIGS. 1A to 1D show an example of a gate oxide film forming process in such a semiconductor device, and the process will be described below. First, by a normal selective oxidation method, P
After forming the field oxide film 8 on the mold Si substrate 1, the oxide film left in the element region is removed (FIG. 3A). Next, a 1800 ° gate oxide film 2 is formed on the entire surface of the wafer including the element region by heat treatment in dry oxygen (FIG. 3B). Next, after a portion other than the element region where the high breakdown voltage N-channel MOS type FET is formed is covered with a photoresist film 5, the gate oxide film 2 in the element region is removed by wet etching with hydrofluoric acid. FIG. 3 (c)).
Thereafter, the photoresist film 5 is removed by ashing with O ₂ plasma, and then a gate oxide film having a thickness of 400 ° is formed on the entire surface of the wafer including the element region by heat treatment in dry oxygen. With the above process, high breakdown voltage N-type FE
In the element region of T, a gate oxide film 21 having a thickness of 2000 mm can be obtained, and in the device region of a highly integrated, high-speed N-type FET, a gate oxide film 22 having a thickness of 400 mm can be obtained (FIG. 3D). .

[Problems to be solved by the invention]

The manufacturing method shown in FIG. 2 and FIG. 3 is suitable for producing, on the same substrate, an MIS type FET for high breakdown voltage and an MIS type FET for high speed and high integration. By combining both manufacturing methods, a high-breakdown-voltage MIS type FET and a high-speed, high-integration MIS-type FET can be fabricated on the same substrate. In addition, the thickness can be reduced in a highly integrated FET.
However, when these manufacturing methods are simply combined,
The number of steps added corresponding to each purpose is simply added, and there is a drawback that the number of steps is much larger than that of a conventional standard MIS type FET manufacturing process.

An object of the present invention is to provide a high-breakdown-voltage MIS type FET in which different types of MIS are used.
It is an object of the present invention to provide a method of manufacturing a semiconductor integrated circuit having a small number of steps even when integrated on the same semiconductor substrate as a type FET.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a high-breakdown-voltage MIS-type FET and a source / drain in which a source / drain diffusion layer region includes a low impurity concentration region close to a channel formation region and another high impurity concentration region. In a method of manufacturing a semiconductor integrated circuit including a high-speed and highly integrated MIS type FET in which a diffusion region includes only a high impurity concentration region,
An insulating film is formed on the entire surface above the region where the drain region is formed, the insulating film above the region where the high impurity concentration regions of both FETs are formed is removed, and an insulating film is formed again over the entire surface to form a low impurity concentration region. Forming two types of gate insulating films, a thick gate insulating film above a region to be formed and a thin gate insulating film above a region to form a high impurity concentration region; A gate electrode of a high-breakdown-voltage MIS type FET is formed thereon, and a gate electrode of a high-speed and highly-integrated MIS type FET is formed on the thin insulating film. To form simultaneously the low impurity concentration region and the high impurity concentration region of the high breakdown voltage MIS type FET and the high impurity concentration region of the high speed and high integration MIS type FET.

[Action]

By introducing impurities by ion implantation on different regions of the gate insulating film, it is possible to form a diffusion layer region having two types of impurity concentrations by ion implantation only once, thereby achieving a high breakdown voltage. The impurity concentration region and the high impurity concentration region of the source / drain diffusion layer of the MIS type FET can be formed on the same semiconductor substrate in the same process as the source / drain diffusion layer of the MIS type FET for high speed and high integration, for example. Therefore, the number of steps can be reduced.

〔Example〕

1 (a) to 1 (e) show the manufacturing process in one embodiment of the present invention for the high breakdown voltage MOS type FET on the left side of each drawing.
High-speed, highly-integrated MOS FETs on the same substrate are shown on the right side of each drawing, and the same reference numerals are given to the parts common to FIGS. 2 and 3. First, similarly to the method shown in FIG. 3, a gate oxide film 2 of 1800.degree. Is formed on the entire surface of the P-type Si substrate (FIG. 1 (a)), and the oxide film is selectively etched and heat-treated in dry oxygen. Gate oxide films 21 and 22 having various thicknesses are formed (FIG. 1B). On this occasion,
In the high breakdown voltage MOS type FET, the thickness of the gate oxide film 22 on the region where the low impurity concentration diffusion layer is formed is 2,000 mm, and the thickness of the gate oxide film 21 on the region where the high impurity concentration diffusion layer is formed is 40 μm.
0 °. For high-speed, highly integrated MOS type FETs,
A gate oxide film 21 of 00 ° is formed. Next, after the gate electrode 3 is formed of polycrystalline silicon (FIG. 1 (c)), ions of phosphorus 4 are implanted in a self-aligned manner using the gate electrode 3 as a mask (FIG. 1 (d)). The ion implantation conditions at this time are as follows: acceleration voltage 90 keV using P ₃₁ ⁺ ions,
The dose amount is 3.5 × 10 ¹⁵ / cm ² . At this time, the amount of P ₃₁ ⁺ ions reaching the P-type silicon substrate depends on the gate oxide film thickness on the surface of the substrate, and the larger the gate oxide film thickness, the smaller the amount of P ₃₁ ⁺ ions reaching the silicon substrate. . Therefore, when heat treatment is performed in a nitrogen atmosphere to diffuse and activate P ₃₁ ⁺ ions to form an N-type diffusion layer (FIG. 1E),
The diffusion layer under the gate oxide film 22 of 2000 mm is the source / drain region 6 of the N type low impurity concentration diffusion layer, and the diffusion layer under the gate oxide film 21 of 400 nm thickness is the source of the N type high impurity concentration diffusion layer. -It becomes the drain region 7. Fig. 4 and Fig. 5 show the agricultural degree distribution of the diffusion layer. FIG. 4 shows the concentration distribution of the N-type high impurity concentration diffusion layer 7, and FIG.
Concentration distribution. In both figures, line 11 is N-type, line
12 is the P type concentration distribution. As you can see from this figure,
The N-type high impurity concentration diffusion layer 7 has a concentration distribution suitable for driving a high-speed, highly integrated FET, and the N-type low impurity concentration diffusion layer 6 reduces the electric field concentration at the drain in a high breakdown voltage FET. The density distribution is sufficient.

According to the above method, the gate oxide film is divided into two types by etching without changing the manufacturing process of the conventional method shown in FIG. 3 in which two types of gate oxide films are formed on the same substrate. By changing only the source / drain part in the high voltage MOS type FET with the pattern
The high breakdown voltage FET as shown in FIG. 2 could be formed on the same substrate as the high-speed, highly integrated FET. That is, as compared with the case where the conventional method in FIGS. 2 and 3 is combined,
The steps of forming the low impurity concentration diffusion layer in FIG. 2 and FIGS. 2A and 2B can be omitted.

〔The invention's effect〕

According to the present invention, a high breakdown voltage MIS type FET and a high speed, highly integrated MIS
Utilizing a process based on the method of the patent application of forming a gate insulating film with a different thickness on the same substrate as the
The thickness of the gate insulating film at the source / drain of the FET is 2
The source / drain portions of the high-breakdown-voltage MIS type FET and, for example, a high-speed, high-integration MIS type FET can be formed simultaneously in a single ion implantation step only by preparing a pattern for dividing the type.
This is extremely effective in reducing the number of steps in the manufacture of a semiconductor integrated circuit including a high-breakdown-voltage MIS type FET requiring high and low impurity concentration source / drain diffusion layer regions.

[Brief description of the drawings]

1 (a) to 1 (e) show a manufacturing process in one embodiment of the present invention on the left side of each drawing for a high breakdown voltage MOS type FET portion, and on the right side of each drawing for a high speed and highly integrated MOS type FET, respectively. The cross-sectional views shown in FIGS. 2 (a) to 2 (e) show a conventional high breakdown voltage MO.
FIG. 3A to FIG. 3C are cross-sectional views sequentially showing the manufacturing process of the S-type FET.
FIG. 4D is a cross-sectional view sequentially showing the steps of a patent application for forming two types of gate oxide films on the same semiconductor substrate, and FIG. 4 is a graph showing the concentration of a high impurity concentration N-type diffusion layer formed according to an embodiment of the present invention. FIG. 5 is a distribution diagram of the low impurity concentration N-type diffusion layer. 1: P-type silicon substrate, 2: 1800Å gate oxide film, 21: 400Å
Gate oxide film, 22: 2000ÅGate oxide film, 3: Gate electrode, 4: Phosphorus ion, 6: N-type low impurity concentration source / drain diffusion layer, 7: N-type high impurity concentration source / drain diffusion layer.

Claims (1)

(57) [Claims] 1. A high-breakdown-voltage MIS type FET in which a source / drain diffusion region is composed of a low impurity concentration region close to a channel formation region and another high impurity concentration region, and a source / drain diffusion region is only a high impurity concentration region. High speed
In a method of manufacturing a semiconductor integrated circuit including a highly integrated MIS type FET, an insulating film is formed on an entire surface of a region where source / drain regions of both FETs are formed, and a region above which a high impurity concentration region of both FETs is formed. The insulating film is removed and an insulating film is formed again on the entire surface to form a low impurity concentration region. A thick gate insulating film above a region where a high impurity concentration region is formed and a thin gate insulating film above a region where a high impurity concentration region is formed. A gate insulating film having two types of thicknesses is formed, and a gate electrode of a high-breakdown-voltage MIS type FET is formed on the thick gate insulating film, and a gate electrode of a high-speed and highly integrated MIS type FET is formed on the thin gate insulating film. Are formed, and ion implantation is performed using the gate insulating film and the gate electrode of these two FETs as masks, respectively, to form the low impurity concentration region and the high impurity concentration region and the high speed / high integration MI of the high breakdown voltage MIS type FET.
A method for manufacturing a semiconductor integrated circuit, comprising simultaneously forming a high impurity concentration region of an S-type FET.