JPH0345548B2 - - Google Patents
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- Publication number
- JPH0345548B2 JPH0345548B2 JP58125309A JP12530983A JPH0345548B2 JP H0345548 B2 JPH0345548 B2 JP H0345548B2 JP 58125309 A JP58125309 A JP 58125309A JP 12530983 A JP12530983 A JP 12530983A JP H0345548 B2 JPH0345548 B2 JP H0345548B2
- Authority
- JP
- Japan
- Prior art keywords
- bipolar transistor
- film
- transistor
- type
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 4
- 230000000295 complement effect Effects 0.000 claims description 3
- 229910052751 metal Inorganic materials 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 2
- 230000008018 melting Effects 0.000 claims description 2
- 229910052750 molybdenum Inorganic materials 0.000 claims description 2
- 239000011733 molybdenum Substances 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- BUMGIEFFCMBQDG-UHFFFAOYSA-N dichlorosilicon Chemical group Cl[Si]Cl BUMGIEFFCMBQDG-UHFFFAOYSA-N 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、Bi−CMOS半導体装置を構成する
MOSトランジスタおよびバイポーラトランジス
タの双方を高性能なものとすることができる製造
方法に関する。[Detailed Description of the Invention] Industrial Application Field The present invention constitutes a Bi-CMOS semiconductor device.
The present invention relates to a manufacturing method that allows high performance of both MOS transistors and bipolar transistors.
従来例の構成とその問題点
近年、半導体プロセス技術の進歩に伴い、半導
体集積回路の高性能化、高機能化が進んでいる。
その中で、同一チツプ上にアナログ機能とデジタ
ル機能を共存させる複合デバイスが注目されつつ
ある。このような回路機能の要求を実現させる技
術の１つとして、バイポーラ素子とCMOS素子
の双方を同一半導体基板内に集積化するBi−
CMOS技術がある。このBi−CMOS技術は、
CMOS回路による低消費電力、高集積化ならび
に高速化の面での効果と、バイポーラ回路による
電流駆動能力ならびにアナログ量の高精度処理能
力などの効果の全てが奏される半導体装置を実現
するものである。Bi−CMOS半導体装置は、性
能面では極めて優れたものであるが、これを製造
するに際しては、上記のようにバイポーラ素子と
相補チヤネル形のMOS素子を同一の半導体基板
内へ作り込まなければならず、このため、製造工
程数の増加、すなわち製造プロセスが複雑化する
ところとなる。Conventional Structure and Problems In recent years, with the progress of semiconductor process technology, the performance and functionality of semiconductor integrated circuits have been increasing.
Among these, composite devices that coexist analog and digital functions on the same chip are attracting attention. One of the technologies to realize these circuit function requirements is Bi-2, which integrates both bipolar elements and CMOS elements on the same semiconductor substrate.
There is CMOS technology. This Bi-CMOS technology is
The goal is to realize a semiconductor device that takes advantage of the low power consumption, high integration, and high speed effects of CMOS circuits, as well as the current drive ability and high precision processing ability of analog quantities of bipolar circuits. be. Bi-CMOS semiconductor devices are extremely superior in terms of performance, but when manufacturing them, bipolar elements and complementary channel MOS elements must be built into the same semiconductor substrate as described above. First, this results in an increase in the number of manufacturing steps, that is, the manufacturing process becomes complicated.
従来のBi−CMOS技術では、上記のような製
造プロセスが複雑化する問題を排除する目的で、
MOS素子であるMOSトランジスタのゲート電極
としてAl電極を用いるのが一般的であつたが、
近年システムの規模が大きくなるに伴い、寸法の
微細化、高集積化あるいは作り込まれる素子の高
性能化が強く望まれ、Alゲート電極構造では、
これらの要求に対応できなくなりつつある。とこ
ろで、素子の微細化ならびに高性能化のために
は、熱拡散法よりも不純物濃度の制御精度が高
く、しかもマスク下部への拡がりが少いイオン注
入法によつて素子の各領域を形成すればよいとこ
ろであるが、イオン注入のためのマスクとして用
いるフオトレジストの材質に起因するイオン注入
条件の制限が生じる。 In conventional Bi-CMOS technology, in order to eliminate the problem of complicating the manufacturing process as described above,
It was common to use Al electrodes as the gate electrodes of MOS transistors, which are MOS devices.
In recent years, as the scale of systems has increased, there has been a strong desire for smaller dimensions, higher integration, and higher performance of the devices being built.
It is becoming impossible to meet these demands. By the way, in order to miniaturize and improve the performance of devices, it is necessary to form each region of the device using ion implantation, which has higher precision in controlling impurity concentration than thermal diffusion, and also has less spread to the bottom of the mask. However, there are restrictions on the ion implantation conditions due to the material of the photoresist used as a mask for ion implantation.
なお、Bi−CMOS半導体装置では、Alゲート
電極構造とするばかりでなく、MOSトランジス
タの領域とバイポーラトランジスタの領域で導電
形が同一の領域を同時に形成することにより、工
程数の低減をはかる配慮も払われるところである
が、上記のようにイオン注入条件に制限が生じる
状況下でこのような配慮を払つた場合には、
MOSトランジスタとバイポーラトランジスタの
双方を高性能なものとすることが困難となる。 In addition, in Bi-CMOS semiconductor devices, in addition to using an Al gate electrode structure, consideration is also given to reducing the number of steps by simultaneously forming regions with the same conductivity type in the MOS transistor region and the bipolar transistor region. However, if such consideration is taken under the circumstances where the ion implantation conditions are restricted as described above,
It becomes difficult to make both MOS transistors and bipolar transistors high performance.
発明の目的
本発明の目的は、ポリシリコンなどの高融点金
属材料をMOSトランジスタおよびバイポーラト
ランジスタの不純物導入のためのマスクとして用
いることにより、従来の製造方法に存在した不都
合を排除することにある。OBJECT OF THE INVENTION An object of the present invention is to eliminate the disadvantages that existed in conventional manufacturing methods by using a high melting point metal material such as polysilicon as a mask for introducing impurities into MOS transistors and bipolar transistors.
発明の構成
本発明の半導体装置の製造方法は、一導電形の
半導体基板上に成長されたこれとは逆導電形のエ
ピタキシヤル層を分離して形成した少くとも２個
のエピタキシヤル島領域の一方にバイポーラトラ
ンジスタを、他方に相補チヤネル形MOSトラン
ジスタを作り込むにあたり、前記バイポーラトラ
ンジスタの少くともエミツタ領域およびこれと導
電形が同一となるMOSトランジスタのソースな
らびにドレイン領域を、高融点金属膜をマスクと
する自己整合式イオン注入法によつて、同時に形
成するようにした方法である。Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes at least two epitaxial island regions formed by separating an epitaxial layer of an opposite conductivity type grown on a semiconductor substrate of one conductivity type. When fabricating a bipolar transistor on one side and a complementary channel type MOS transistor on the other side, at least the emitter region of the bipolar transistor and the source and drain regions of the MOS transistor having the same conductivity type are masked with a high-melting point metal film. This method uses a self-aligned ion implantation method to simultaneously form the ion implantation method.
かかる本発明の半導体装置の製造方法による
と、イオン注入条件の制限が除かれるため、例え
ば、バイポーラトランジスタがNPN形であると
きにはＮ形エミツタ領域を、また、横形PNP構
造であるときにはＰ形のエミツタおよびコレクタ
領域をこれらと導電形が同じになるMOSトラン
ジスタのソースおよびドレイン領域とともに一度
のイオン注入処理で形成し、しかも、イオン注入
条件をバイポーラトランジスタおよびMOSトラ
ンジスタの双方を高性能なものとするのに好まし
い条件に設定することが可能になる。 According to the method for manufacturing a semiconductor device of the present invention, restrictions on ion implantation conditions are removed, so for example, when the bipolar transistor has an NPN type, the N type emitter region is formed, and when the bipolar transistor has a lateral PNP structure, the P type emitter region is formed. The collector region and the source and drain regions of the MOS transistor, which have the same conductivity type as these, are formed in a single ion implantation process, and the ion implantation conditions are set so that both the bipolar transistor and the MOS transistor have high performance. This makes it possible to set favorable conditions.
実施例の説明
以下に、Bi−CMOS半導体装置の製造過程を
示す第１図〜第６図を参照して本発明の半導体装
置の製造方法について詳しく説明する。DESCRIPTION OF EMBODIMENTS The method for manufacturing a semiconductor device of the present invention will be described in detail below with reference to FIGS. 1 to 6 showing the manufacturing process of a Bi-CMOS semiconductor device.
本発明の半導体装置の製造方法では、先ず、第
１図で示すように、バイポーラ集積回路において
出発材料として用いられるＰ型シリコン基板１を
準備し、この中へ二酸化シリコン（SiO2）膜を
マスクとして用いる周知の選択拡散法によりN+
形埋込層２およびP+形埋込層３を形成したのち、
表面を覆うSiO2膜を除去し、さらに、ジクロル
シラン（SiH2Cl2）の熱分解によりＮ形エピタキ
シヤル層４を約5μｍの厚さに成長させる。 In the method for manufacturing a semiconductor device of the present invention, first, as shown in FIG. 1, a P-type silicon substrate 1 used as a starting material in a bipolar integrated circuit is prepared, and a silicon dioxide (SiO 2 ) film is masked into it. N +
After forming the shaped buried layer 2 and the P + shaped buried layer 3,
The SiO 2 film covering the surface is removed, and an N-type epitaxial layer 4 is grown to a thickness of about 5 μm by thermal decomposition of dichlorosilane (SiH 2 Cl 2 ).
次いで、第２図で示すように、上記と同様の選
択拡散法により、Ｎ形エピタキシヤル層１を貫通
してP+形埋込層３に繋るＰ形拡散層５を形成す
る。このＰ形拡散層５の形成により、Ｎ形エピタ
キシヤル層４が島状に分離される。こののち、選
択拡散時にマスクとして用いたSiO2膜ならびに
選択拡散時の熱処理で生成されたSiO2膜の全て
を除去し、表面全域に厚さが約500ÅのSiO2膜６
と厚さが約1200Åの窒化シリコン（Si3N4）膜７
とを積層形成したのち、周知のフオトエツチング
処理を施すことによつて、MOSトランジスタを
形成するべき基板部分上ならびにバイポーラトラ
ンジスタのベース領域とコレクタコンタクト領域
を形成するべき基板部分上にのみ積層された２種
類の膜を残す。 Next, as shown in FIG. 2, a P type diffusion layer 5 is formed which penetrates the N type epitaxial layer 1 and connects to the P + type buried layer 3 by the same selective diffusion method as described above. By forming this P type diffusion layer 5, the N type epitaxial layer 4 is separated into islands. After this, all of the SiO 2 film used as a mask during selective diffusion and the SiO 2 film generated by the heat treatment during selective diffusion were removed, leaving a SiO 2 film with a thickness of approximately 500 Å over the entire surface.
and a silicon nitride (Si 3 N 4 ) film 7 with a thickness of approximately 1200 Å.
After that, by performing a well-known photoetching process, the film was laminated only on the substrate portion where the MOS transistor was to be formed and the substrate portion where the base region and collector contact region of the bipolar transistor were to be formed. Two types of films are left behind.
以上の処理が施されたシリコン基板に対して、
熱酸化のための処理を施すことにより積層膜によ
つて覆われることなく露出するシリコン基板部分
に厚さが約0.8μｍのフイールド酸化膜を形成し、
さらにSi3N4膜７とこの直下のSiO2膜６とを順次
エツチングして除去したのち、これらの膜の除去
部分に露出するシリコン基板面の上に厚さが、
500〜700Å程度のゲート酸化膜を形成する。 For the silicon substrate that has been subjected to the above processing,
By performing thermal oxidation treatment, a field oxide film with a thickness of approximately 0.8 μm is formed on the exposed portion of the silicon substrate that is not covered by the laminated film.
Furthermore, after sequentially etching and removing the Si 3 N 4 film 7 and the SiO 2 film 6 immediately below it, a thick layer is formed on the silicon substrate surface exposed in the removed portion of these films.
Form a gate oxide film of approximately 500 to 700 Å.
第３図は、以上の過程を経た後の構造を示す図
であり、後の工程で不純物導入がなされることの
ないシリコン基板部分上にはフイールド酸化膜８
が形成され、一方、不純物導入がなされるシリコ
ン基板部分上にはゲート酸化膜９が形成された構
造が得られる。 FIG. 3 is a diagram showing the structure after the above process, in which a field oxide film 8 is formed on the silicon substrate portion where impurities will not be introduced in later steps.
A structure is obtained in which a gate oxide film 9 is formed on the silicon substrate portion into which impurities are introduced.
次いで、第４図で示すように、全面にポリシリ
コン膜１０を約4000Åの厚さで形成し、この後、
NMOSトランジスタのゲートとなりうる部分、
PMOSトランジスタのゲート、ソース、ドレイ
ンとなりうる部分およびバイポーラトランジスタ
のベースとなりうる部分で、エミツタ領域の作り
込みがなされる部分を除く残余の部分のみにポリ
シリコン膜１０を残すためのパターンエツチング
処理を施す。こののち、ポリシリコン膜１０とフ
イールド酸化膜８をマスクとして加速電圧
150KeV、ドーズ量８×1015cm-2の注入条件で砒
素（As）をイオン注入し、NMOSトランジスタ
のＮ形ソース領域１１、Ｎ形ドレイン１２および
バイポーラトランジスタのＮ形エミツタ領域１
３、Ｎ形コレクタコンタクト領域１４を形成す
る。 Next, as shown in FIG. 4, a polysilicon film 10 with a thickness of about 4000 Å is formed on the entire surface, and then,
The part that can be the gate of an NMOS transistor,
A pattern etching process is performed to leave the polysilicon film 10 only in the remaining parts except for the part where the emitter region is created, in the part that can become the gate, source, and drain of a PMOS transistor and the part that can become the base of a bipolar transistor. . After this, the acceleration voltage is applied using the polysilicon film 10 and the field oxide film 8 as a mask.
Arsenic (As) was ion-implanted under the implantation conditions of 150 KeV and a dose of 8×10 15 cm -2 to form the N-type source region 11, N-type drain 12 of the NMOS transistor, and the N-type emitter region 1 of the bipolar transistor.
3. Form N-type collector contact region 14.
次いで、第５図に示すように、PMOSトラン
ジスタのゲートとなりうる部分、NMOSトラン
ジスタのゲート、ソース、ドレイン領域およびバ
イポーラトランジスタのコレクタコンタクト領域
の上をフオトレジスト１５で覆い、このフオトレ
ジスト１５をマスクとして、ポリシリコン膜１０
を周知のプラズマエツチによりエツチングする。
その後フオトレジスト１５、フイールド酸化膜
８、ポリシリコン膜１０をマスクにして、加速電
圧50KeV、ドーズ量５×1014cm-2の注入条件でボ
ロン(B)をイオン注入し、PMOSトランジスタの
Ｐ形ソース領域１６、Ｐ形ドレイン領域１７およ
びバイポーラトランジスタのＰ形ベース領域１８
を形成する。 Next, as shown in FIG. 5, the portion that can become the gate of the PMOS transistor, the gate, source, and drain regions of the NMOS transistor, and the collector contact region of the bipolar transistor are covered with a photoresist 15, and this photoresist 15 is used as a mask. , polysilicon film 10
is etched by a well-known plasma etch.
Thereafter, using the photoresist 15, the field oxide film 8, and the polysilicon film 10 as masks, boron (B) ions are implanted under the conditions of an acceleration voltage of 50 KeV and a dose of 5×10 14 cm -2 to form a P-type PMOS transistor. Source region 16, P-type drain region 17 and P-type base region 18 of the bipolar transistor
form.
次いで、第６図で示すように、周知の気相成長
により、表面全域にSiO2膜１９を形成したのち、
ソース領域とドレイン領域の押し込みとSiO2膜
１９の緻密化をはかるため、N2雰囲気中で、
1000℃の熱処理を10分間にわたり施す。 Next, as shown in FIG. 6, after forming a SiO 2 film 19 over the entire surface by well-known vapor phase growth,
In order to push in the source and drain regions and make the SiO 2 film 19 denser, in an N 2 atmosphere,
Heat treatment is performed at 1000°C for 10 minutes.
そして最後に、ソース領域１１，１６、ドレイ
ン領域１２，１７、バイポーラトランジスタのエ
ミツタ領域、コレクタコンタクト領域およびベー
ス領域１３，１４および１８のそれぞれにアルミ
ニウム電極を形成するためのコンタクト孔を穿設
し、それぞれの領域にアルミニウム電極２０を形
成することによつて本発明の製造方法によるシリ
コンゲート構造のBi−CMOS半導体装置の製作
が完了する。 Finally, contact holes for forming aluminum electrodes are formed in each of the source regions 11 and 16, the drain regions 12 and 17, the emitter region of the bipolar transistor, the collector contact region and the base regions 13, 14 and 18, By forming aluminum electrodes 20 in each region, the manufacture of a Bi-CMOS semiconductor device with a silicon gate structure by the manufacturing method of the present invention is completed.
以上、本発明を一例を示して説明したが、本発
明によれば、バイポーラトランジスタとして
PNP形のトランジスタを作り込むこともできる。
また、高融点金属膜としてポリシリコン膜を例示
したが、これにかえて、タングステンあるいはモ
リブデンなどの膜を用いてもよいこと勿論であ
る。 The present invention has been explained above by showing an example, but according to the present invention, as a bipolar transistor
It is also possible to incorporate PNP type transistors.
Further, although a polysilicon film is exemplified as the high-melting point metal film, it goes without saying that a film of tungsten, molybdenum, or the like may be used instead.
発明の効果
以上説明したところから明らかなように、本発
明の製造方法によれば、MOSトランジスタとバ
イポーラトランジスタの領域の中で、導電形が同
じである領域を一度のイオン注入の処理で作り込
むことができ、また高い寸法精度を確保すること
ができる自己整合法により、MOSトランジスタ
ならびにバイポーラトランジスタの主要な領域が
形成されるものであるため、不純物導入処理の統
合による工程数の削減ならびにBi−CMOS半導
体集積回路の高集積化などの効果が奏される。さ
らに、各領域を形成するに際して、イオン注入法
を採用した場合の注入条件の制限が緩和されるた
め、注入条件設定の範囲が拡がり、MOSトラン
ジスタとバイポーラトランジスタの双方を高性能
なものとすることができる効果も奏される。Effects of the Invention As is clear from the above explanation, according to the manufacturing method of the present invention, regions having the same conductivity type among the regions of the MOS transistor and the bipolar transistor can be created by a single ion implantation process. Since the main regions of MOS transistors and bipolar transistors are formed using the self-alignment method that can ensure high dimensional accuracy, it is possible to reduce the number of steps by integrating impurity introduction processes and to improve Bi- Effects such as higher integration of CMOS semiconductor integrated circuits can be achieved. Furthermore, when forming each region, the restrictions on implantation conditions when using ion implantation are relaxed, which expands the range of implantation condition settings, making it possible to improve the performance of both MOS transistors and bipolar transistors. The effect that can be achieved is also produced.
第１図〜第６図は、本発明の製造方法によつて
Bi−CMOS半導体装置が製造される過程を説明
するための断面図である。
１……Ｐ形シリコン基板、２……N+形埋込層、
３……P+形埋込層、４……Ｎ形エピタキシヤル
層、５……Ｐ形拡散層、６，１９……二酸化シリ
コン膜、７……窒化シリコン膜、８……フイール
ド酸化膜、９……ゲート酸化膜、１０……ポリシ
リコン膜、１１……Ｎ形ソース領域、１２……Ｎ
形ドレイン領域、１３……Ｎ形エミツタ領域、１
４……Ｎ形コレクタコンタクト領域、１５……フ
オトレジスト、１６……Ｐ形ソース領域、１７…
…Ｐ形ドレイン領域、１８……Ｐ形ベース領域、
２０……アルミニウム電極。
FIG. 1 to FIG. 6 show the results obtained by the manufacturing method of the present invention.
FIG. 3 is a cross-sectional view for explaining the process of manufacturing a Bi-CMOS semiconductor device. 1...P type silicon substrate, 2...N + type buried layer,
3... P + type buried layer, 4... N type epitaxial layer, 5... P type diffusion layer, 6, 19... silicon dioxide film, 7... silicon nitride film, 8... field oxide film, 9... Gate oxide film, 10... Polysilicon film, 11... N type source region, 12... N
type drain region, 13...N type emitter region, 1
4...N-type collector contact region, 15...Photoresist, 16...P-type source region, 17...
...P type drain region, 18...P type base region,
20...Aluminum electrode.
Claims (1)
は逆導電形のエピタキシヤル層を分離して形成し
た少なくとも２個のエピタキシヤル島領域の一方
にバイポーラトランジスタを、他方に相補チヤネ
ル形MOSトランジスタを作り込むにあたり、前
記バイポーラトランジスタのエミツタ領域およ
び、これと導電形が同一となる一方の前記MOS
トランジスタのソースならびにドレイン領域を、
前記バイポーラトランジスタのベース領域およ
び、これと導電形が同一となる他方の前記MOS
トランジスタのソースならびにドレイン領域を、
それぞれ、単一工程で形成した高融点金属膜をマ
スクとする自己整合式イオン注入法で形成するこ
とを特徴とする半導体装置の製造方法。 ２ 高融点金属膜が、ポリシリコン膜、タングス
テン膜およびモリブデン膜から選択されたもので
あることを特徴とする特許請求の範囲第１項に記
載の半導体装置の製造方法。[Claims] 1. A bipolar transistor is provided in one of at least two epitaxial island regions formed by separating epitaxial layers of an opposite conductivity type grown on a semiconductor substrate of one conductivity type, and a bipolar transistor in the other. In manufacturing a complementary channel type MOS transistor in the emitter region of the bipolar transistor and one of the MOS transistors having the same conductivity type as the emitter region of the bipolar transistor,
The source and drain regions of the transistor,
The base region of the bipolar transistor and the other MOS having the same conductivity type as the base region of the bipolar transistor.
The source and drain regions of the transistor,
A method for manufacturing a semiconductor device, characterized in that each semiconductor device is formed by a self-aligned ion implantation method using a refractory metal film formed in a single step as a mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the high melting point metal film is selected from a polysilicon film, a tungsten film, and a molybdenum film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58125309A JPS6017943A (en) | 1983-07-08 | 1983-07-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58125309A JPS6017943A (en) | 1983-07-08 | 1983-07-08 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6017943A JPS6017943A (en) | 1985-01-29 |
| JPH0345548B2 true JPH0345548B2 (en) | 1991-07-11 |
Family
ID=14906910
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58125309A Granted JPS6017943A (en) | 1983-07-08 | 1983-07-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6017943A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5190886A (en) * | 1984-12-11 | 1993-03-02 | Seiko Epson Corporation | Semiconductor device and method of production |
| JPS61139058A (en) * | 1984-12-11 | 1986-06-26 | Seiko Epson Corp | Production apparatus for semiconductor |
| ATE59917T1 (en) * | 1985-09-13 | 1991-01-15 | Siemens Ag | CIRCUIT CONTAINING INTEGRATED BIPOLAR AND COMPLEMENTARY MOSTRANSISTORS ON A COMMON SUBSTRATE AND METHOD FOR THEIR MANUFACTURE. |
| JP2578757B2 (en) * | 1985-10-17 | 1997-02-05 | 日本電気株式会社 | Semiconductor device |
| JPS63216370A (en) * | 1987-03-05 | 1988-09-08 | Toshiba Corp | Semiconductor device |
| JP2610906B2 (en) * | 1987-11-18 | 1997-05-14 | 富士電機株式会社 | Method for manufacturing BiMOS semiconductor circuit device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420679A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Bipolar mos semiconductor integrated circuit device and the same |
| JPS55165669A (en) * | 1979-06-11 | 1980-12-24 | Hitachi Ltd | Bipolar-mos device |
| JPS5768075A (en) * | 1980-10-16 | 1982-04-26 | Nippon Gakki Seizo Kk | Manufacture of integrated circuit device |
-
1983
- 1983-07-08 JP JP58125309A patent/JPS6017943A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5420679A (en) * | 1977-07-18 | 1979-02-16 | Hitachi Ltd | Bipolar mos semiconductor integrated circuit device and the same |
| JPS55165669A (en) * | 1979-06-11 | 1980-12-24 | Hitachi Ltd | Bipolar-mos device |
| JPS5768075A (en) * | 1980-10-16 | 1982-04-26 | Nippon Gakki Seizo Kk | Manufacture of integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6017943A (en) | 1985-01-29 |
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