JPH02241057A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To simplify steps and to eliminate reduction in the thickness of an isolating insulating film between a base and an emitter of a p-channel MOS transistor by an etching step by simultaneously forming a gate electrode and an emitter electrode, and forming a graft base simultaneously upon formation of the source and drain regions of the transistor in a self-alignment manner. CONSTITUTION:A first laminated layer film of a silicon oxide film 20 and a silicon nitride film 22 is formed on a first N-well region 5, and a second laminated layer film of a silicon oxide film 10 and a polycrystalline silicon film 23 is provided on a second N-well region 51 and a P-well region 7. Then, P-type impurity is ion implanted to the region 5 to form a base region 13, an N-type impurity is doped from an opening formed at the laminated layer film on the region 13 to form an emitter region 19. Thereafter, a polycrystalline silicon film 24 and a high melting point metal silicide film 25 are selectively formed on the emitter region 19 and the second laminated layer film, an emitter electrode 18 and a gate electrode 11 are simultaneously formed, boron ions are implanted with them as masks, and a graft base region 26, a source region 17 and a drain region 171 are simultaneously formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor integrated circuit, particularly to a method for manufacturing a Bi-CMOS in which a bipolar transistor and a complementary MO5 (hereinafter referred to as CMO8) transistor are formed in the same semiconductor substrate. It is.

Conventional technology In recent years, there has been a desire for higher speed semiconductor integrated circuits and coexistence of analog and digital functions, and B t -CMO, which integrates bipolar transistors and CMOS transistors on the same substrate, has been developed.
3 integrated circuits are attracting attention.

A conventional Bi-CMO8 integrated circuit device had a structure as shown in FIG. Below, with reference to Fig. 2, conventional Bi
- An example of a method for manufacturing a CMO8 integrated circuit device will be described.

First, an n-type silicon epitaxial layer 4 having a specific resistance of 1 to 5 Ωcm is formed on a p-type wheel crystal silicon substrate 1 on which n-type buried regions 2 and 21 and n-type buried regions 3 and 31 are selectively formed. , n-well regions 5 and 51 are connected to the n-type buried regions 2 and 21, and an isolation region 6 is connected to the n-type buried region 3.
A p-well region 7 is formed on the mold buried region 31 and connected thereto. Further, by selective oxidation, a thick isolation oxide film 8 is grown to isolate the elements.

Thereafter, a silicon oxide film 9 for space emitter separation of the npn transistor is formed on the surface of the n-well region 5 in the bipolar transistor formation region by selective oxidation. Furthermore, a thin silicon oxide film 10 that will become a gate oxide film is formed on the n-well region 51 and p-well region 7 that form the MOS transistor, and on top of this is a polycrystalline silicon film doped with a high concentration of phosphorus by thermal diffusion. is selectively formed as a first conductive film to form the gate electrode 11. Next, a collector all layer 12 of an npn transistor is formed by diffusion of n-type impurities, and a space region 13 is formed by selectively ion-implanting p-type impurities. Next, n-type impurities are selectively ion-implanted to form an n-channel M
After forming an n-type source region 14 and a drain region 141 at a low concentration for the OS transistor and further forming a silicon oxide film 15 for side walls on the side walls of the gate electrode 11, n-type impurities are selectively ion-implanted. to form a highly doped n-type source region 16 of an n-channel MOS transistor.
By forming a drain region 161 and a drain region 161, an LDD structure of an n-channel MOS transistor is formed. Furthermore, p-type impurities are selectively ion-implanted to form a high-concentration p-type source region 1 of an n-channel MOS transistor.
7 and a drain region 171 are formed. Next, an arsenic-doped polycrystalline silicon film is used as a second conductive film and is selectively formed in the base region 13 to form an emitter electrode 18. Then, an emitter region 19 is formed by diffusion of arsenic from the emitter electrode 18.

Problems to be Solved by the Invention These conventional manufacturing methods require a low-resistance polycrystalline silicon film heavily doped with phosphorus through thermal diffusion as the gate electrode of the MOS transistor.
As the emitter electrode of the transistor, polycrystalline silicon doped with arsenic is required to serve as a diffusion source for the shallow emitter region, so two types of polycrystalline silicon films are required, and pattern formation is also required for this purpose. It is necessary to do it once. As a result, there was a drawback that the process became complicated. Furthermore, since the emitter electrode made of polycrystalline silicon is formed after the p-type source region and drain region of the n-channel MOS transistor are formed,
If a graft base of a pn transistor is formed, it has the disadvantage that it cannot be formed in a self-aligned manner simultaneously with the formation of the p-type source region and drain region of an n-channel MOS transistor. Furthermore, since the separation film between the pace emitters of the npn transistor is formed of a silicon oxide film, the film thickness is reduced due to the silicon oxide film etching process in the middle of the process, and it becomes extremely thin due to manufacturing variations, resulting in a reverse bias between the pace emitters. When a strong electric field is applied, hot electron injection traps occur in the oxide film separating the pace emitters, which tends to cause characteristic fluctuations that cause reliability problems such as fluctuations in the current amplification factor, and increases parasitic capacitance. It had drawbacks. The present invention solves the above-mentioned conventional problems by simplifying the process by forming the gate electrode and the emitter electrode at the same time, and by forming the graft base of the npn transistor with the formation of the source and drain regions of the n-channel MOS transistor. The object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit that can simultaneously form a semiconductor integrated circuit in a self-aligned manner and prevent the thickness of a paste emitter isolation film from being reduced due to an intermediate silicon oxide film etching process. be.

Means for Solving the Problems In order to solve these problems, the method for manufacturing a semiconductor integrated circuit of the present invention includes forming a semiconductor layer on a p-type silicon substrate, and forming a first layer in a bipolar transistor formation region of the semiconductor layer. a second n-well region in the p-channel MOS transistor formation region, an n-well region in the n-channel MO3 transistor formation region, and a base of the bipolar transistor in the first n-well region. selectively forming a first laminated film of a silicon oxide film and a silicon nitride film on the formation region; and a step of selectively forming a first laminated film of a silicon oxide film and a polycrystalline silicon film on the second n-well region and the n-well region. 2, a step of selectively ion-implanting p-type impurities onto the base formation region of the bipolar transistor to form a base region, and a step of forming a base region on the emitter formation region in the base region. selectively removing said first laminated film to form an opening; doping said opening with an n-type impurity to form an emitter region; and forming an emitter region and said second laminated film. selectively forming a polycide film made of a polycrystalline silicon film and a high melting point metal silicide film on top of the film to simultaneously form an emitter electrode of a bipolar transistor and a gate electrode of a MOS transistor, and masking the emitter electrode and gate electrode. Boron ions are implanted into the graft base region of the bipolar transistor and the p-channel MO.
This method includes a step of simultaneously forming a source region and a drain region of an S transistor.

According to the semiconductor integrated circuit of the present invention, the gate electrode of the MOS transistor and the emitter electrode of the bipolar transistor can be formed at the same time, thereby simplifying the process. In addition, the graft base of the bipolar transistor is used as a p-channel Mo in a self-aligned manner using the emitter electrode as a mask.
Since it can be formed in the same process as the p-type source region and drain region of the S transistor, the base resistance can be easily reduced and the speed of the bipolar transistor can be increased. Furthermore, since the isolation insulating film between the base and emitter of the bipolar transistor is formed of a silicon nitride film, the film thickness does not decrease due to the silicon oxide film etching step in the middle of the process, and an increase in parasitic capacitance can also be prevented.

Embodiment An embodiment of the method for manufacturing a semiconductor integrated circuit according to the present invention will be described with reference to the process flowchart shown in FIG.

First, as shown in FIG. 10.
n-type or p-type silicon epitaxial layer 4 of Ωcm
, n-well regions 5 and 51 are formed above the n-type buried regions 2 and 21, and an isolation region 6 is formed above the n-type buried region 3, and an isolation region 6 is formed above the n-type buried region 31. An n-well region 7 connected thereto is formed above. Furthermore, after a thick isolation oxide film 8 is grown by selective oxidation to isolate the elements, a collector all layer 12 of the bipolar transistor is formed by diffusion of n-type impurities.

Next, as shown in Figure 1, a thin silicon oxide film 20 is placed on the surface.
After forming, a silicon nitride film 22 is continuously formed,
The silicon nitride film 22 is selectively removed so that it remains in the base formation region of the bipolar transistor in the n-well region 5, and the MOS transistor formation region is doped with impurities for threshold voltage control.

Thereafter, the thin silicon oxide film 20 in the MOS transistor formation region is selectively removed.

Next, as shown in FIG. 1C, a thin silicon oxide film 10 that will become a gate oxide film is formed on the surface using the silicon nitride film 22 as a mask, and then a thin polycrystalline silicon film 23 is formed over the entire surface.
form. Next, after selectively removing the thin polycrystalline silicon film 23 on the base formation region of the bipolar transistor, p-type impurity ions are selectively implanted to form the base region 13.

Next, as shown in FIG. 1d, after selectively removing the thin polycrystalline silicon film 23 on the collector all layer 12 and further removing the silicon nitride film 22 on the emitter formation region, the collector all layer 12 is removed. The thin silicon oxide films 10 and 20 on the emitter formation region are selectively removed. Thereafter, arsenic is selectively ion-implanted as an n-type impurity to form an emitter region 19 and a collector contact region 27.

Next, as shown in Figure 1e, the thickness of the arsenic-doped film is 200 mm.
~300 nm polycrystalline silicon film 24 and a film thickness of 150 nm~
A 200 nm low resistance high melting point metal silicide film 25 is grown on the surface to form a so-called polycide structure, and this is selectively etched to simultaneously form the gate electrode 11 of the Mo8 transistor and the emitter electrode 18 and collector electrode 28 of the bipolar transistor. Form.

Next, as shown in FIG. 1f, n-type impurities are selectively ion-implanted into the p-well region 7 to form a low concentration n-type source region 14 and drain region 141 of the n-channel MOS transistor. Then, after forming a silicon oxide film 15 for sidewalls on the side walls of the gate electrode 11, emitter electrode 18, and collector electrode 28, n-type impurities are selectively ion-implanted to form a high-concentration n-channel Mo8 transistor. n-type source region 16 and drain region 161
By forming , an LDD structure of an n-channel MOS transistor is formed. Furthermore, p-type impurities are selectively ion-implanted into the n-well regions 5 and 51 to form a graft base region 26 of the bipolar transistor and a high concentration p-type source region 17 and drain region 171 of the p-channel MOS transistor. are formed at the same time.

According to this embodiment formed as described above, the polycrystalline silicon film 24 doped with arsenic and the high melting point metal silicide are used as the films for forming the gate electrode 11 of the MoS transistor and the emitter electrode 18 of the NPN bipolar transistor. Since the polycide film consisting of the film 25 is used, there is only one type of film, and the emitter, collector, and gate electrode can be formed at the same time, which simplifies the process.

Furthermore, since the graft base region 26 of the npn bipolar transistor can be formed simultaneously with the formation of the highly doped p-type source region 17 and drain region 171 and in a self-aligned manner using the emitter electrode 18 as a mask, the base resistance can be reduced. , it is possible to easily speed up bipolar transistors. In addition, since the silicon nitride film 22 of the pace emitter isolation film of the bipolar transistor serves as an etching-resistant mask for the silicon oxide film 20, the thickness of the pace emitter isolation film does not decrease due to etching of the silicon oxide film in the middle of the process, thereby reducing manufacturing variations. The initial film thickness can be maintained without becoming extremely thin due to the effects of It is possible to suppress characteristic fluctuations that cause problems in terms of reliability, such as fluctuations in current amplification factor, and it is also possible to prevent an increase in extra parasitic capacitance between pace emitters.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor integrated circuit of the present invention, the gate electrode of the Mo8 transistor and the emitter electrode of the bipolar transistor can be formed at the same time, thereby simplifying the process. In addition, the graft base of the npn bipolar transistor can be formed simultaneously with the formation of the source and drain of the p-channel MoS transistor in a self-aligned manner with respect to the emitter polycide electrode, making it easy to increase the speed of the npn bipolar transistor. can. In addition, reliability can be improved by covering the silicon oxide film of the isolation film between the pace emitters of bipolar transistors with a nitride film, and furthermore, by forming the emitter electrode and gate electrode into a polycide structure, emitter resistance and gate wiring resistance can be reduced. This makes it possible to increase the speed of the device. As described above, it is possible to realize a method for manufacturing a highly reliable and high-performance semiconductor integrated circuit.

[Brief explanation of drawings]

FIG. 1 is a process sectional view showing the method of manufacturing a semiconductor integrated circuit according to the present invention, and FIG. 2 is a sectional view showing the structure of a conventional semiconductor integrated circuit device. 1... Single crystal silicon substrate, 2, 21...
... n-type buried region, 3, 31... n-type buried region, 5.51... n-well region, 6...
...Separation region, 7...P well region, 8.
...Isolation oxide film, 9.10°20...Silicon oxide film, 11...Gate electrode, 12...
... Collector all region, 13 ... Base region, 14 ... Low concentration n-type source region,
141...Low concentration n-type drain region, 15
・・・・・・Silicon oxide film for sidewall, 16
...High concentration n-type source region, 161...
...High concentration n-type drain region, 17...
p-type source region, 171... p-type drain region, 18... emitter electrode, 19...
・Emitter region, 22...Silicon nitride film, 2
3.24...polycrystalline silicon film, 25...
... High melting point silicide film, 26 ... Graft base region, 27 ... Collector contact region,
28... Collector electrode. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (1)

[Claims] A semiconductor layer is formed on a p-type silicon substrate, a first n-well region is formed in the bipolar transistor formation region of the semiconductor layer, a second n-well region is formed in the p-channel MOS transistor formation region, and an n-channel MOS transistor is formed. a step of forming a p-well region in the region; a step of selectively forming a first laminated film of a silicon oxide film and a silicon nitride film on the base formation region of the bipolar transistor in the first n-well region; selectively providing a second laminated film of a silicon oxide film and a polycrystalline silicon film on the second n-well region and the p-well region, and doping p-type impurities on the base formation region of the bipolar transistor. a step of selectively implanting ions to form a base region; a step of selectively removing the first laminated film on an emitter formation region in the base region to form an opening; A step of doping an emitter region with impurities of A step of simultaneously forming an emitter electrode and a gate electrode of a MOS transistor, and implanting boron ions using the emitter electrode and gate electrode as masks, forming a graft base region of a bipolar transistor and a source region and a drain region of a p-channel MOS transistor. 1. A method of manufacturing a semiconductor integrated circuit, comprising: a step of simultaneously forming a semiconductor integrated circuit.