JP2507055B2 - Method for manufacturing semiconductor integrated circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit in which a bipolar transistor and a MOS transistor are formed in the same semiconductor substrate.

2. Description of the Related Art In recent years, there has been a demand for higher speed semiconductor integrated circuits and coexistence of analog and digital functions. Bi-CM is a bipolar transistor and CMOS (complementary MOS) transistor integrated on the same substrate.
OS integrated circuits are receiving attention.

A conventional Bi-CMOS integrated circuit device has a structure as shown in FIG. Hereinafter, referring to FIG. 2, the conventional Bi-CMOS
An example of the structure of the integrated circuit device and the manufacturing method thereof will be described.

First, a p-type single crystal silicon substrate 1 in which n-type buried regions 2 and 21 and p-type buried regions 3 and 31 are selectively formed
An n-type silicon epitaxial layer 4 having a specific resistance of 1 to 5 Ωcm, an n-well region 5 connected to the n-type buried regions 2 and 21, and a p-type buried region 3 on the n-type buried regions 2 and 21. Forms an isolation region 6 connected to this and a p well region 7 on the p type buried region 31. Further, a thick silicon oxide film 8 is grown by a selective oxidation method to separate the elements. After that, the base-emitter isolation oxide film 9 of the npn transistor is formed in the bipolar transistor region by the selective oxidation method. Further, a thin silicon oxide film 10 to be a gate oxide film is formed, and a polycrystalline silicon film doped with a high concentration of phosphorus by thermal diffusion is selectively formed as a first conductive film thereon to form a gate electrode 11. . Next, a collector wall layer 12 of an npn transistor is formed by diffusing n-type impurities, and p-type impurities are selectively ion-implanted to form a base region 13. Next, n-type impurities are selectively ion-implanted to form the n ^- sole region 14 and the n ^- drain region 114 of the n-channel MOS transistor,
After the side wall 15 is formed on the gate electrode 11 with a silicon oxide film or the like, n type impurities are selectively ion-implanted to form the n ⁺ source region 16 and the n ⁺ drain region 116 of the n channel MOS transistor. An LDD structure of a channel MOS transistor is formed. Further, p-type impurities are selectively ion-implanted to form the p ⁺ source region 17 and the p ⁺ drain region 117 of the p-channel MOS transistor. Then, an arsenic-doped polycrystalline silicon film is selectively formed as a second conductive film to form an emitter electrode 18. The emitter diffusion layer 19 is formed by diffusing arsenic from the emitter electrode 18.

In the conventional manufacturing method described above, two kinds of conductive films are required to form the gate electrode 11 of the MOS transistor and the emitter electrode 18 of the npn transistor, and the pattern formation needs to be performed twice. Further, since the emitter electrode 18 is formed after forming the p ⁺ source region 17 and the p ⁺ drain region 117 of the p-channel MOS transistor, the graft base of the npn transistor is connected to the p-channel MOS transistor of the p-channel MOS transistor.
^{+ It} is necessary to form the source region 7 and the drain region 17 in separate steps. Further, since the base-emitter isolation film 9 of the npn transistor is a silicon oxide film, the film is reduced by the silicon oxide film etching process in the middle process.

Problems to be Solved by the Invention In such a conventional manufacturing method, a low resistance polycrystalline silicon film highly doped with phosphorus by thermal diffusion is required as a gate electrode of a MOS transistor, and an emitter electrode of an npn transistor is required. As a source of shallow diffusion of the emitter diffusion layer having a desired impurity profile, a polycrystalline silicon film doped with arsenic of an appropriate concentration is required, and thus two types of polycrystalline silicon films are required. Further, there is a drawback that the process becomes complicated because it is necessary to form the pattern twice. Further, the polycrystalline emitter electrode made of silicon, to form after the formation of the p ⁺ source region and a p ⁺ drain region of the p-channel MOS transistor, p ⁺ source region and the p-channel MOS transistor graft base of the npn transistor p ⁺
It has a drawback that it needs to be formed in a separate step from the formation of the drain region. Furthermore, since the base-emitter isolation film of the npn transistor is formed of a silicon oxide film, the film is reduced by the silicon oxide film etching process in the middle process, and it becomes extremely thin due to manufacturing variations, and a reverse aroma bias is applied between the base and emitter. If a strong electric field is applied, hot electron injection traps occur in the base-emitter isolation oxide film, which easily causes characteristic fluctuations such as fluctuations in current amplification factor, which are a problem in terms of reliability, and parasitic capacitance increases. Had.

The present invention solves the above-mentioned conventional problems by simplifying the process by forming a gate electrode and an emitter electrode at the same time, and forming a graft base of an npn transistor and a source and drain region of a p-channel MOS transistor. At the same time, by forming the emitter electrode on the mask in a self-aligned manner, the external base resistance can be easily reduced.
By preventing the base-emitter isolation film thickness of the npn transistor from decreasing due to the silicon oxide film etching process in the middle of the process, it is possible to suppress the characteristic variation of the npn transistor which may cause a reliability problem and increase the parasitic capacitance. It is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit, which enables suppression.

Means for Solving the Problems In order to solve these problems, a method of manufacturing a semiconductor integrated circuit according to the present invention comprises a step of continuously growing a thin oxide film and a nitride film to provide a first composite film, A step of selectively removing the first composite film to leave the first composite film on at least a region serving as a base of the bipolar transistor; and a selective oxidation to thin oxidation by using the first composite film as a mask. After the film is formed, a thin polycrystalline silicon film is continuously grown to form a second composite film, and the second composite film on the base formation region of the bipolar transistor is selectively removed to form a p-type or n-type film. Forming a base region by selectively doping a type impurity, selectively removing the second composite film on the collector contact region, on the emitter forming region and on the collector contact region A step of selectively removing the first composite film to form an opening,
A step of doping an n-type or p-type impurity through the opening, and a step of growing a low-resistance polycrystalline silicon film doped with a high concentration of an n-type or p-type impurity to selectively select the polycrystalline silicon film. Forming a gate electrode of the MOS transistor and an emitter electrode and a collector electrode of the bipolar transistor at the same time, and p-type or n-type impurities are implanted by using the electrode as a mask to form a source region and a drain region of the MOS transistor. Forming the graft base region of the bipolar transistor at the same time.

Action With this configuration, the gate electrode of the MOS transistor and the npn
A low resistance polycrystalline silicon film can be used for the emitter electrode of the transistor, and the gate electrode and the emitter electrode can be formed at the same time, which simplifies the process. Further, the graft base of the npn transistor can be formed in a self-aligned manner by using the emitter electrode as a mask in the same step as the formation of the p ⁺ source region and the p ⁺ drain region of the p-channel MOS transistor, which reduces external base resistance. This makes it easy to realize high speed npn transistors. Also, the decrease in the thickness of the base-emitter isolation film of the npn transistor due to the etching process of the silicon oxide film in the middle process is suppressed because the silicon nitride film acts as an anti-etching stopper, improving the reliability of the npn transistor and reducing the parasitic capacitance. Since it also prevents an increase in the number of transistors, it is easy to increase the speed of the npn transistor.

Embodiment An embodiment of the present invention will be described with reference to the process sectional view of FIG.

First, as shown in FIG. 1A, the n-type buried regions 2 and 21 are formed.
On the p-type single crystal silicon substrate 1 on which the p-type buried regions 3 and 31 are selectively formed, an n having a specific resistance of 0.3 to 10 Ωcm is formed.
A p-type or p-type silicon epitaxial layer 4 is formed,
An n well region 5 connected to the n type buried regions 2 and 21 is formed, an isolation region 6 connected to the n well region 5 is formed above the p type buried region 3, and an isolation region 6 is formed above the p type buried region 31. A p well region 7 is formed. Further, a thick silicon oxide film 8 is grown by the selective oxidation method, the elements are separated from each other, and the collector wall layer 12 of the npn transistor is formed by diffusing n-type impurities.

Next, as shown in FIG. 1B, a thin silicon oxide film 20 is formed, and then a silicon nitride film 22 is continuously formed, and the silicon nitride film 22 is selectively formed so that the silicon nitride film 22 remains in the bipolar transistor region. Then, impurities are doped to control the threshold voltage of the MOS transistor. After that, the thin silicon oxide film 20 in the MOS transistor region is selectively removed.

Next, as shown in FIG. 1C, a thin silicon oxide film 10 to be a gate oxide film is selectively formed, and a thin polycrystalline silicon film 23 is continuously formed. Next, after the thin polycrystalline silicon film 23 on the base formation region of the npn transistor is selectively removed, p-type impurities are selectively ion-implanted to form the base region 13.

Next, as shown in FIG. 1D, the thin polycrystalline silicon film 23 on the collector contact forming region is selectively removed, and the silicon nitride film 22 on the emitter forming region and the collector contact forming region and the thin silicon oxide film are removed. After selectively removing the film 20, arsenic is selectively ion-implanted as an n-type impurity to form the emitter diffusion layer 19 and the collector contact region.
27.

Next, as shown in FIG. 1 (e), a polycrystalline silicon film 24 in which arsenic of 300 to 400 nm is highly doped is grown, and this is selectively etched to form the gate electrode 11 of the MOS transistor and the emitter of the npn transistor. Electrode 18 and collector electrode 28
Are formed at the same time.

Next, as shown in FIG. 1 (f), n-type impurities are selectively ion-implanted to form the n ^- source region 14 and the n ^- drain region 114 of the n-channel MOS transistor, and the gate electrode 11 is formed by a silicon oxide film or the like. After the side wall 15 is formed on the emitter electrode 18 and the collector electrode 28, n-type impurities are selectively ion-implanted to form the n ⁺ source region 16 and the n ⁺ drain region 116 of the n-channel MOS transistor. An LDD structure of a channel MOS transistor is formed. Furthermore, p
-Type impurities are selectively ion-implanted to p-channel MOS
The p ₊ source region 17, p ⁺ drain region 117 of the transistor and the graft base region 26 of the npn transistor are formed simultaneously.

According to the present embodiment configured as described above, since the emitter diffusion layer 19 is formed by the impurity doping process prior to electrode formation, regardless of the diffusion from the emitter electrode 18, the arsenic concentration of the emitter electrode 18 is reduced. MOS without having to control
As the film for forming the gate electrode 11 of the transistor and the emitter electrode 18 of the npn transistor, the low resistance polycrystalline silicon film 24 highly doped with arsenic can be used and it becomes one type, and both electrodes can be formed at the same time. Therefore, the process is simplified. Also, the graft base region 26 of the npn transistor is the p ⁺ source region 17 and the p ⁺ drain region 117.
Since it can be formed in a self-aligning manner at the same time as the formation of the above, and the emitter electrode 18 is used as a mask, the external base resistance can be reduced and the npn transistor can be easily speeded up. Further, since the silicon nitride film 22 of the base-emitter isolation film of the npn transistor serves as an etching stopper for the silicon oxide film 20, the base-emitter isolation film thickness does not decrease due to the etching of the silicon oxide film in the middle process, etc. Since the initial film thickness can be maintained without being affected by, the high electric field does not occur even if a reverse bias is applied between the base-emitters, injection traps of hot electrons into the base-emitter isolation film are prevented, and the current amplification factor changes. It is possible to suppress the characteristic fluctuation that causes a problem in the reliability of the npn, and prevent the increase of extra parasitic capacitance between the base and emitter.
The transistor speed can be increased.

As described above, the present invention simplifies the process by forming the gate electrode of the MOS transistor and the emitter electrode of the npn transistor at the same time, and the graft base of the npn transistor is formed at the time of forming the source and drain of the p-channel MOS transistor. Simultaneously and forming in self-alignment with the polycrystalline silicon electrode of the emitter facilitates speeding up of the npn transistor, and by covering the silicon oxide film of the isolation film between the base and emitter of the npn transistor with a nitride film, reliability is improved. It is possible to realize an excellent method for manufacturing a semiconductor integrated circuit, which improves the speed of an npn transistor.

[Brief description of drawings]

1 (a) to 1 (f) are process sectional views showing a method for manufacturing a semiconductor integrated circuit according to an embodiment of the present invention, and FIG. 2 is a sectional view showing manufacturing of a conventional semiconductor integrated circuit device. 1 ... p-type single crystal silicon substrate, 9 ... silicon oxide film, 10 ... silicon oxide film, 11 ... gate electrode, 13 ...
Base region, 18 ... Emitter electrode, 20 ... Silicon oxide film, 22 ... Silicon nitride film, 23 ... Polycrystalline silicon film,
24: Polycrystalline silicon film, 26: Graft base region.

Claims (1)

(57) [Claims] 1. A step of continuously growing a thin oxide film and a nitride film to form a first composite film, and selectively removing the first composite film to form at least a base region of a bipolar transistor. The step of leaving the first composite film remaining on the substrate, and forming a thin oxide film by a selective oxidation method using the first composite film as a mask, and then continuously growing a thin first polycrystalline silicon film. And the step of providing the composite film, and the first polycrystalline silicon film on the base formation region of the bipolar transistor is selectively removed to obtain a p-type (or n-type)
To selectively form the base region by selectively doping the impurities of the above step, selectively removing the first polycrystalline silicon film on the collector contact formation region, and the first formation on the emitter formation region. A step of selectively removing the composite film and the thin oxide film on the collector contact formation region to form an opening; and an emitter region and a collector contact region by doping an n-type (or p-type) impurity from the opening. And a low-resistance second polycrystalline silicon film doped with an n-type (or p-type) impurity at a high concentration is grown, and the second polycrystalline silicon film is selectively removed. Forming the gate electrode of the MOS transistor and the emitter electrode and collector electrode of the bipolar transistor at the same time, and p-type (or n-type) masking the electrodes.
Type) impurities are implanted to simultaneously form a source region and a drain region of a MOS transistor and a graft base region of a bipolar transistor.