JPH056961A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a Bi-CMOS semiconductor device having high performance by performing only two steps of implanting impurities for forming both conductivity type source.drain regions, an external base region, an emitter electrode, an emitter diffused layer and both conductivity type gate electrodes. CONSTITUTION:A silicon nitride film 11 is selectively formed on a base region 9 of a bipolar transistor, and an emitter opening 14 is formed in the film 11. An emitter electrode 15 and a gate electrode 16 made of polycrystalline silicon are selectively formed, and an N-type high concentration impurity is ion implanted to forming regions of an N-channel MOSFET and a bipolar transistor thereby to dope the electrodes 16, 15 and to form source.drain regions 18 of the MOSFET. An external base region and source.drain region of a P-channel MOSFET are formed by heat treating in an oxidative atmosphere and ion implanting P-type high concentration impurity in the entire surface. Thus, a semiconductor device having high performance can be manufactured in less number of steps.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a Bi-CMOS semiconductor device having a polycrystalline silicon emitter electrode.

[0002]

2. Description of the Related Art In recent years, Bi-CMOS devices, which realize a high-speed logic circuit by combining a fine bipolar transistor and a fine CMOSFET, have been attracting attention. Since a highly reliable diffusion layer having a shallow junction depth can be easily obtained in the emitter electrode of a bipolar transistor of such a high-speed Bi-CMOS device, for example, IEDM t
It is advantageous to use polycrystalline silicon as disclosed in echnical digest P408, 1986 and the like.

Further, in the conventional CMOS semiconductor device, P
In both channel and N-channel MOSFETs, N-type polycrystalline silicon is generally used for the gate electrode. In this case, the P-channel MOSFET is usually of the buried channel type in order to obtain a desired inversion voltage for circuit operation. However, the buried channel type device easily causes punch-through, and it is difficult to cope with the miniaturization of the device. Therefore, a method of making a P-channel MOSFET a surface channel type by using P-type polycrystalline silicon for a gate electrode is disclosed in, for example, IEEE Trans. Electron Devices, Vol. ED32,
p584, 1985.

Next, a method of manufacturing a Bi-CMOS device using the emitter electrode made of polycrystalline silicon and further having the gate electrode of P-type polycrystalline silicon will be described with reference to FIGS. First, as shown in FIG. 8, an N-type high-concentration buried layer 102 to be a high-concentration collector region of a bipolar transistor and a buried diffusion layer of a P-channel MOSFET, a buried separation region of a bipolar transistor, and an N-channel MOSF on a semiconductor substrate 101.
P-type high-concentration buried layer 103 serving as a buried diffusion layer for ET
Then, an N-type low-concentration epitaxial layer 104 is formed, and an N-type well region of the P-channel MOSFET is formed.
A low-concentration diffusion layer 105 and a P-type low-concentration diffusion layer 106 to be the well region of the N-channel MOSFET and the isolation region of the bipolar transistor are formed. Next, as shown in FIG.
N-type high concentration collector region 107 of bipolar transistor
The field oxide film 108, the P-type base region 109 of the bipolar transistor, and the gate oxide film 110 are sequentially formed. Next, as shown in FIG. 10, a gate electrode 111 made of polycrystalline silicon of MOSFET is formed.

Next, as shown in FIG. 11, a resist pattern 11 is formed.
2 is formed and a high concentration P-type impurity is ion-implanted to form an external base region of the bipolar transistor and a P channel M.
High-concentration P-type diffusion layer serving as source / drain of OSFET
113 is formed and the gate electrode 111 of the P-channel MOSFET is P-type doped. Next, as shown in FIG. 12, a resist pattern 114 is formed, and high-concentration N-type impurities are ion-implanted to form a high-concentration N-type diffusion layer 115 which becomes the collector contact region of the bipolar transistor and the source / drain of the N-channel MOSFET. Forming and N
The gate electrode 111 of the channel MOSFET is N-type doped. Next, as shown in FIG. 13, a silicon oxide film 116 is formed on the entire surface by a chemical vapor deposition method, and an emitter opening 117 is formed in a bipolar transistor formation region.
A high-concentration N-type diffusion layer 119 which becomes an emitter diffusion layer is formed by forming an emitter electrode 118 made of polycrystalline silicon, further doping this to a high-concentration N-type, and further diffusing through an emitter opening 117 by heat treatment. Form. After that, the normal interlayer insulating film and the wiring region are formed, and then the Bi-CM
Complete the OS semiconductor device.

According to this method, MO of both conductive polarities is used.
Since the SFET is a surface channel type, a fine MOSF
High punch-through resistance can be obtained even in ET, and a high-performance bipolar transistor having an emitter electrode made of polycrystalline silicon can be formed.

[0007]

However, in the above manufacturing method, the gate electrode is etched, the P-type and N-type high-concentration diffusion layers, and the emitter opening are formed from the formation of the base region to the formation of the CMOSFET and the bipolar transistor. A problem that the number of steps is remarkably increased as compared with a normal CMOS device, for example, five resist pattern forming steps and three high-concentration impurity introducing steps are required for forming a portion and etching an emitter electrode. There is a point.

As a method of forming the emitter electrode, a method of forming the emitter electrode at the same time as the method of forming the emitter electrode is described in "CM of Tetsuya Iizuka", for example.
Design of OS VLSI "(Baifukan, published April 25, 1989,
p72), this method requires four resist pattern forming steps and two high-concentration impurity introducing steps from the formation of the base region to the formation of the CMOSFET and the bipolar transistor. In such a method, in order to prevent the high-concentration P-type impurity in the external base region from being doped into the emitter electrode, it is necessary to separate the emitter electrode and the external base region by an alignment margin in the resist pattern forming process. There is a problem that the base resistance increases, and moreover, since the emitter opening is formed in the gate oxide film, contamination is likely to be introduced into the gate oxide film in the step of forming this opening, and the stability of the MOSFET characteristics is impaired. There is danger.

The present invention has been made in order to solve the above problems in the conventional method for manufacturing a Bi-CMOS semiconductor device, and has a small base resistance, and is high in that contamination is not introduced into the gate oxide film. An object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a high-performance Bi-CMOS semiconductor device with a small number of steps.

[0010]

In order to solve the above problems, the present invention provides a bipolar transistor having a base region of one conductivity type, a MOSFET of one conductivity type having a gate electrode of one conductivity type, and a reverse conductivity type. Composed of MOSFETs of opposite conductivity polarity with different gate electrodes
In a method of manufacturing a semiconductor device including a FET, a step of selectively forming an oxidation resistant film in a base region of the bipolar transistor, a step of forming an emitter opening in the oxidation resistant film, and an emitter electrode made of polycrystalline silicon And a step of selectively forming a gate electrode and M having an opposite conductivity polarity.
A high-concentration impurity of the opposite conductivity type is selectively ion-implanted into a region for forming an OSFET and a bipolar transistor to dope the gate electrode and the emitter electrode and to perform the MOSFE.
A step of forming a source / drain region of T, a step of performing a heat treatment in an oxidizing atmosphere to form an emitter diffusion layer and a relatively thick thermal oxide film in each region doped with an opposite conductivity type, A step of selectively removing the exposed region of the oxidation resistant film; and a high-concentration one-conductivity-type impurity ion-implanted over the entire surface to form an external base region and one-conductivity-polarity MOSF.
It is characterized by including a step of forming a source / drain region of ET.

[0011]

According to the above method of manufacturing a semiconductor device of the present invention,
The impurity introduction step for forming both the conductive type source / drain regions, the external base region, the emitter electrode, the emitter diffusion layer, and the both conductive type gate electrodes is performed twice.
Further, since the emitter electrode and the gate electrode are formed at the same time, and the P-type and N-type high-concentration impurities can be separately implanted in a self-aligned manner, the number of photo processes is reduced, and the emitter electrode and the external base region are formed in a self-aligned manner. High performance Bi
-A CMOS semiconductor device can be manufactured in a small number of steps.

[0012]

EXAMPLES Next, examples will be described. 1 to 7
FIG. 6A is a diagram showing a manufacturing process for explaining the embodiment of the method for manufacturing the semiconductor device according to the present invention. First, as shown in FIG. 1, an N-type high-concentration buried layer 2 serving as a high-concentration collector region of a bipolar transistor and a buried diffusion layer of a P-channel MOSFET, a buried separation region of a bipolar transistor, and an N-channel MOSF are formed on a semiconductor substrate 1.
After forming the P-type high-concentration buried layer 3 to be the ET buried diffusion layer, the N-type low-concentration epitaxial layer 4 is formed,
Further, an N-type low-concentration diffusion layer 5 which becomes the well region of the P-channel MOSFET and a P-type low-concentration diffusion layer 6 which becomes the well region of the N-channel MOSFET and the isolation region of the bipolar transistor are formed. Then, as shown in FIG. 2, an N-type high-concentration collector region 7, a field oxide film 8, a P-type base region 9 and a thermal oxide film 10 of the bipolar transistor are sequentially formed. Next, as shown in FIG. 3, a silicon nitride film 11 is selectively formed in the base region 9 of the bipolar transistor, and the silicon nitride film 11 is used as a mask to form the MO film.
After removing the thermal oxide film 10 in the element region of the SFET, a gate oxide film 12 is formed, and a thinner first polycrystalline silicon film 13 is formed on the entire surface.

Next, as shown in FIG. 4, after forming the emitter opening 14, a second polycrystalline silicon is deposited on the entire surface, and the second polycrystalline silicon and the first polycrystalline silicon film 13 are further deposited. By etching the emitter electrode
15 and the gate electrode 16 are formed. At this time, the gate electrode 16 and the emitter electrode 15 excluding the opening are formed of the second polycrystalline silicon and the first polycrystalline silicon film 13 previously formed.
It has a layered film structure. As described above, the emitter opening 14 is formed with the gate oxide film 12 protected by the thin polycrystalline silicon film 13.
Therefore, the gate oxide film 12 is not contaminated in the emitter opening forming step. In addition to this, when the emitter electrode 15 is separated by the thermal oxide film 10 and the silicon nitride film 11, the emitter opening is formed in the gate oxide film by forming these films 10 and 11 relatively thick. Compared with, the parasitic capacitance of the emitter electrode 15 and the base region 9 can be reduced.

Next, as shown in FIG. 5, arsenic of high concentration is ion-implanted using the resist pattern 17 formed in the N well region as a mask to form the N type source / drain region 18 and collector contact region of the N channel MOSFET. 19 is formed, the emitter electrode 15 and the N channel MOSF are formed.
The gate electrode 16 of the ET is heavily doped with N type. At this time, by making the range of ion implantation sufficiently smaller than that of the silicon nitride film 11 and the thermal oxide film 10, the implantation of arsenic into the base region 9 can be prevented.

Next, as shown in FIG. 6, arsenic is diffused from the emitter electrode 15 through the emitter opening 14 by heat treatment in an oxidizing atmosphere to form an emitter diffusion layer 20. At this time, the N-type high-concentration impurity-doped N
Gate electrode 16 and emitter electrode of channel MOSFET
At 15, a thermal oxide film 21 is formed which is thicker than the gate electrode 16 of the P-channel MOSFET which is not doped with the N-type high-concentration impurity. Further, the oxide film in the source / drain region and the collector contact region of the MSOFET also becomes thicker, but the N-channel MO doped with N-type high concentration impurities is used.
The source / drain region 18 and the collector contact region 19 of the SFET are the P channel M which is not doped.
A thermal oxide film 22 thicker than the source / drain formation region of the OSFET is formed. Further, since the silicon nitride film 11 is formed in the base region 9, this region is not oxidized.

Next, as shown in FIG. 7, the silicon nitride film formed in the base region 9 by the treatment with hot phosphoric acid.
After selectively removing the exposed part of the emitter electrode 15 which is not covered with the emitter electrode 15, a high concentration of BF ₂ is ion-implanted into the entire surface to expose the P-type external base region 23 and the P-channel MOS.
The P-type source / drain region 24 of the FET is formed, and the gate electrode 16 of the P-channel MOSFET is heavily doped with P-type. At this time, by reducing the range of the injected BF ₂ , the BF is introduced into the region doped with the N-type high-concentration impurities in which the thick thermal oxide films 21 and 22 are formed by the heat treatment in the oxidizing atmosphere. ₂ can be prevented from being injected. After that, the semiconductor device is completed through the usual steps of forming an interlayer insulating film and a wiring layer.

As described above, in the manufacturing method of the present invention,
The resist pattern forming process required from the formation of the base region 9 to the formation of the CMOSFET and the bipolar transistor is the process of selectively forming the silicon nitride film 11 in the base region 9 and the process of forming the emitter opening 14. And the step of forming the gate electrode 16 and the emitter electrode 15 and the step of doping the N-type high-concentration impurity are performed four times. Further, since the emitter electrode 15 and the gate electrode 16 are doped with the impurity at the same time, The number of steps can be reduced as compared with the conventional manufacturing method, such that the step of introducing the high-concentration impurity is only required twice. In addition, according to the method of the present invention, since the external base region 23 is formed in self-alignment with the emitter electrode 15, a high performance bipolar transistor having a low base resistance can be formed.

[0018]

As described above on the basis of the embodiments,
According to the present invention, a bipolar transistor having a small base resistance and having an emitter electrode made of polycrystalline silicon, and a P-channel MOSFE made of P-type polycrystalline silicon.
A high-performance Bi-CMOS semiconductor device including a CMOSFET having a T gate electrode can be easily manufactured with a small number of steps.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process for explaining an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG.

FIG. 3 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 2;

FIG. 4 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 3;

FIG. 5 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 4;

FIG. 6 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 5;

FIG. 7 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 6;

FIG. 8 is a diagram showing a manufacturing process for explaining an example of a conventional method for manufacturing a semiconductor device.

9 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 8. FIG.

FIG. 10 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 9.

FIG. 11 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 10.

FIG. 12 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 11.

FIG. 13 is a diagram showing a manufacturing process that follows the manufacturing process shown in FIG. 12.

[Explanation of symbols]

1 Semiconductor substrate 2 N type high concentration buried layer 3 P type high concentration buried layer 4 N type low concentration epitaxial layer 5 N type low concentration diffusion layer 6 P type low concentration diffusion layer 7 N-type high concentration collector region 8 field oxide film 9 P-type base area 10 Thermal oxide film 11 Silicon nitride film 12 Gate oxide film 13 Thin first polycrystalline silicon film 14 Emitter opening 15 Emitter electrode 16 Gate electrode 17 Resist pattern 18 N-type source / drain region 19 Collector contact area 20 Emitter diffusion layer 21 Thermal oxide film 22 Thermal oxide film 23 P type external base area 24 P-type source / drain region

Claims (2)

[Claims] 1. A CMOS including a bipolar transistor having a base region of one conductivity type, a MOSFET of one conductivity polarity having a gate electrode of one conductivity type, and a MOSFET of a reverse conductivity polarity having a gate electrode of the opposite conductivity type.
In a method of manufacturing a semiconductor device including a FET, a step of selectively forming an oxidation resistant film in a base region of the bipolar transistor, a step of forming an emitter opening in the oxidation resistant film, and an emitter electrode made of polycrystalline silicon And a step of selectively forming a gate electrode and M having an opposite conductivity polarity.
A high-concentration impurity of the opposite conductivity type is selectively ion-implanted into a region for forming an OSFET and a bipolar transistor to dope the gate electrode and the emitter electrode and to perform the MOSFE.
A step of forming a source / drain region of T, a step of performing a heat treatment in an oxidizing atmosphere to form an emitter diffusion layer and a relatively thick thermal oxide film in each region doped with an opposite conductivity type, A step of selectively removing the exposed region of the oxidation resistant film; and a high-concentration one-conductivity-type impurity ion-implanted over the entire surface to form an external base region and one-conductivity-polarity MOSF.
A method of manufacturing a semiconductor device, comprising a step of forming source / drain regions of ET. 2. A step of forming a gate oxide film at least in a region where a MOSFET is formed, and a step of forming a thin polycrystalline silicon film on the entire surface, prior to the step of forming an emitter opening in the oxidation resistant film. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of selectively removing at least the polycrystalline silicon film in a region where a bipolar transistor is formed.