JPS6017943A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the number of steps and to integrate a Bi-CMOS semiconductor integrated circuit by using a high melting point metal material such as polysilicon as a mask for introducing impurity of an MOS transistor and a bipolar transistor. CONSTITUTION:A polysilicon film 10 is formed on a field oxidized film 8 and a gate oxidized film 9, pattern etching is executed, and with the films, 10, 8 as masks arsenic ions As are implanted to form an N type source region 11, an N type drain 12 of an NMOS transistor, and an N type emitter region 13 and an N type collector contacting region 14 of a bipolar transistor. Then, with the photoresist 15, a field oxidized film 18 and the film 10 as masks boron ions B are implanted, thereby forming a P type source region 16, a P type drain region 17 of a PMOS transistor and a P type base region 18 of a bipolar transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to Mos constituting a B1-CMO8 semiconductor device.
＋・Conventional configurations and problems associated with manufacturing methods that can achieve high performance for both transistors and bipolar transistors In recent years, with the advancement of semiconductor process technology, the performance and functionality of semiconductor integrated circuits have increased. is progressing.

Among these, composite devices that coexist analog and digital functions on the same chip are attracting attention. One of the technologies to realize these circuit function requirements is Bi-CMO8 technology, which integrates both bipolar elements and 0MO8 elements on the same semiconductor substrate. ? Nino Bi-CM OS technology combines the low power consumption, high integration, and high-speed effects of the 0M08 circuit, as well as the current drive ability and high-precision analog processing ability of the bipolar circuit. This realizes a semiconductor device that can be played. The Bi-CMO8 semiconductor device is
Although it is extremely superior in terms of performance, in manufacturing it, as mentioned above, a bipolar element and a complementary channel type MOS element must be fabricated in the same semiconductor substrate. Therefore, the number of manufacturing steps increases, that is, the manufacturing process becomes complicated.

In conventional Bi-CMOS technology, in order to eliminate the problem of complicating the manufacturing process as described above, it was common to use Afi electrodes as the gate electrodes of transistors (MOS devices), but in recent years As the scale of the system increases, there is a strong demand for smaller dimensions, higher integration, and higher performance of the devices to be manufactured, and the An gate electrode structure is becoming unable to meet these demands. Although it would be possible to form each region of the element by an ion implantation method that causes less spread to the bottom of the screen, there are restrictions on the ion implantation conditions due to the material of the photoresist used as a mask for ion implantation.

In Nao, Bi-CM OS semiconductor devices, Afi game
1. Consideration is being given to reducing the number of process steps by not only forming an electrode structure but also forming regions of the same conductivity type in the MOS transistor region and the bipolar transistor region at the same time. If such considerations are taken under conditions where ion implantation conditions are restricted, it will be difficult to achieve high performance in both the MOS transistor and the bipolar transistor.

OBJECTS OF THE INVENTION An object of the present invention is to eliminate the disadvantages of conventional manufacturing methods by using a high melting point metal material such as polysilicon as a mask for introducing impurities into MOS transistors and bipolar transistors.

Structure of the Invention The method for manufacturing a semiconductor device of the present invention includes forming an epitaxial layer of an opposite conductivity type grown on a semiconductor substrate of a -conductivity type in one of at least two epitaxial island regions formed separately. In fabricating a bipolar transistor and a complementary channel type MOS transistor on the other hand, at least the emitter region of the bipolar transistor and the source and drain regions of a MOS transistor having the same conductivity type as the bipolar transistor, This method uses a self-aligned ion implantation method using a high melting point metal film as a mask to simultaneously form the layers.

According to the method for manufacturing a semiconductor device of the present invention, restrictions on ion implantation conditions are removed, and for example, when the bipolar transistor has an N P N type, the N type emitter region is formed, and when the bipolar transistor has a lateral PNP structure, the P type emitter region is formed. The emitter and collector regions of the MOS transistor, which have the same conductivity type as these, are formed in a single ion implantation process along with the source and drain regions of the MOS transistor, and the ion implantation conditions are changed to those of the bipolar transistor and MO! 3) It becomes possible to set both transistors to conditions favorable for achieving high performance.

DESCRIPTION OF THE EMBODIMENTS The semiconductor device 6' of the present invention will now be described with reference to FIGS. 1 to 6, which show the manufacturing process of a Bi-CMOS semiconductor device.

The manufacturing method of the device will be explained in detail.

In the method for manufacturing a semiconductor device of the present invention, first, as shown in FIG. 1, a P-type silicon substrate 1 used as a starting material in a bipolar integrated circuit is prepared, and a silicon dioxide (S i02 ) film is masked into the substrate. After forming an N+ type buried layer 2 and a P+ type buried layer 3 using a well-known selective diffusion method, the S102 film covering the surface is removed, and dichlorosilane (SI H2CF'-2)
The N-type epitaxial layer 4 is grown to a thickness of about 5 μm by thermal decomposition.

Next, as shown in FIG. 2, a P-swelled diffusion layer 5 penetrating the N-type epitaxial layer 1 and connected to the pi-type buried layer 3 is formed by the same selective diffusion method as described above.

By forming this P-swelled diffusion layer 5, the N-type epitaxial layer 4 is separated into islands. After this, all of the S 102 film used as a mask during selective diffusion and the S 102 film generated during the heat treatment during selective diffusion were removed, leaving a 3102 film 6 with a thickness of approximately 500 mm over the entire surface. 1200
After forming a layered silicon nitride (Si3N4) film 7, a well-known photoetching process is performed to form the base region and collector contact region of the bipolar transistor as well as on the substrate portion where the MO8 transistor is to be formed. Two types of films are left laminated only on the desired substrate portion.

A thermal oxidation treatment is applied to the silicon substrate that has been subjected to the following process, so that the exposed portion of the silicon substrate that is not covered by the laminated film has a thickness of approximately 0.8 μm.
m field oxide film is formed, and then a Si3N4 film 7 is formed.
and the S t 02 film 6 directly below this are sequentially etched 17.
After removing these films, a gate oxide film having a thickness of approximately 500 to 700 mm is formed on the silicon substrate surface exposed in the removed portions of these films.

FIG. 3 is a diagram showing the structure after going through the following process, in which a field oxide film 8 is formed on the silicon substrate portion where impurities will not be introduced in the subsequent process, and on the other hand,
A structure is obtained in which a gate oxide film 9 is formed on a portion of the silicon substrate into which impurities are introduced.

Next, as shown in FIG. 4, a polysilicon film 1 is formed on the entire surface.
o to a thickness of about 4000, after which NMO3)
Part that can become the gate of a transistor, PMO 8) A polysilicon film 1o is applied only to the remaining part excluding the part where the emitter region is formed, in the part that can become the gate, source, and drain of the transistor and the part that can become the base of the bipolar transistor. Perform pattern etching to remove any remaining parts. After this, using the polysilicon film 1° and the field oxide film 8 as a mask, an acceleration voltage of 150 KeV was applied.
Arsenic (As) was ion-implanted at a dose of 8×10 m2 to form the N-type source region 11 and N-type drain 12 of the NMO transistor, and the N-type emitter region 13 and N-type collector contact region 14 of the bipolar transistor. Form.

Next, as shown in FIG. 5, photoresist 15 is applied to the parts of the PMO (3) that can become the gate of the transistor, the gate, source, and drain regions of the NMO (3) transistor, and the collector contact region of the bipolar transistor.
Cover this photo register with 9.

Using the resist 16 as a mask, the polysilicon film 1o is etched by well-known plasma etching. After that, photoresist 15, field oxide film 8, polysilicon film 10
using a mask, acceleration voltage 50 KeV, dose amount 5
Boron (B) is ion-implanted under the implantation condition of ×10 crn, and the P-type source region 16, P
shaped drain region 17 and P of the bipolar transistor
A shape base region 18 is formed.

Next, as shown in FIG. 6, by well-known vapor phase growth,
After forming the Si 0 2 film 19 over the entire surface, heat treatment is performed at 1000° C. for 10 minutes in an N 2 atmosphere in order to push in the source and drain regions and to make the 5IO 2 film 19 denser.

And finally, source region 11.16, drain region 1
2, 17, emitter region of bipolar transistor,
A contact hole for forming an aluminum electrode is formed in each of the collector contact region and the base region 13, 14 and 18, and an aluminum electrode 20 is formed in each region, thereby forming a silicon oxide film according to the manufacturing method of the present invention. The fabrication of the Bi-CMOS semiconductor device with the gate structure is completed.

Hereinafter, the present invention has been explained by showing an example, but according to the present invention, a PNP type transistor can also be fabricated as a bipolar transistor.

Although a polysilicon film is exemplified as the high melting point metal film, it goes without saying that a film of tungsten, molybdenum, or the like may be used instead.

As is clear from the detailed description of the invention, according to the manufacturing method of the present invention, the MO3) transistor can be manufactured using a self-aligning method that can ensure extremely high dimensional accuracy. Since the main regions of bipolar transistors and bipolar transistors are formed, the number of steps can be reduced by integrating impurity introduction processes, and Bi-CMO
Effects such as higher integration of S semiconductor integrated circuits can be achieved. Furthermore, when forming each region, restrictions on implantation conditions when using the ion implantation method are relaxed, which expands the range of implantation condition settings, making it possible to achieve high performance for both MO3I transistors and bipolar transistors. It also has the effect of making it more effective.

[Brief explanation of the drawing]

1 to 6 show Bi-C produced by the manufacturing method of the present invention.
FIG. 3 is a cross-sectional view illustrating a process of manufacturing an MO3 semiconductor device. DESCRIPTION OF SYMBOLS 1...P type silicon substrate, 2...N4-type buried layer, 3...P''-type buried layer, 4...N
type epitaxial layer, 6...P swelling diffusion layer, 6,
19...Silicon dioxide film, 7...Silicon nitride film, 8...Field oxide film, 9...
Gate oxide film, 10... Polysilicon film, 11.
...N type source region, 12...N type drain region, 13...N type emitter region, 14...
N-type collector contact region, 16... Photoresist, 16... P-type source region, 17...
. . . P type drain region, 18 . . . P type base region, 20 . . . aluminum electrode. Figure 1 Figure 2 Figure 3 az 3 za 2

Claims (1)

[Claims] 0) - At least two epitaxial layers grown on a semiconductor substrate of a conductivity type and separated from each other and of a reverse electrostatic type.
In fabricating a bipolar transistor in one of the epitaxial island regions and a complementary channel type MOS transistor in the other, at least the emitter region of the bipolar transistor and the MOS transistor having the same conductivity type as the bipolar transistor are formed.
S) A method for manufacturing a semiconductor device, characterized in that the source and drain regions of the transistor are simultaneously formed by a self-aligned ion implantation method using a high melting point metal film as a mask. (2) The method for manufacturing a semiconductor device according to claim 1, wherein the high melting point metal film is a polysilicon film.