JPS6292358A - Semiconductor device - Google Patents

Abstract

PURPOSE:To make a MOSTr having high withstanding voltage, a high-speed bipolar transistor and a microminiaturized CMOSTr coexist by forming a source-drain region in the MOSTr by using a deep well having low concentration. CONSTITUTION:An N<+> type buried layer 2 and a P<+> type buried layer 3 are shaped to a P-type substrate 1, and an N-type epitaxial layer 4 is grown. A P well and an N well are each formed, and thick isolation oxide films 6 are shaped selectively. A gate oxide film 8 and N<+> type gate polycrystalline silicon 9 are formed. A base region 10 composed of BiTr is shaped, an emitter diffusion window is bored, and a second polycrystalline silicon layer 11 thinner than the gate polycrystalline silicon layer 9 is formed so as to coat the emitter diffusion window. A source-drain region 12 in an NMOSTr and an emitter 17 consisting of BiTr are shaped. A source-drain region 13 in a PMOSTr and a base contact region 14 composed of BiTr are formed, an insulating film 15 is shaped, a contact window is bored, and an aluminum electrode 16 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to an integrated circuit device in which a silicon MOS field effect transistor and a bipolar transistor are formed on the same substrate.

[Conventional technology]

Conventionally, an integrated circuit in which a bipolar transistor and a complementary MOS field effect transistor (hereinafter referred to as a C'MOS transistor) are formed on the same substrate is characterized by the low power consumption operation of the C'MOS transistor, and the high speed operation and high drive ability of the bipolar transistor. Many attempts have been reported in recent years because they can simultaneously achieve the following.

Conventionally reported silicon gate Bi-CMOSIC
FIG. 2 shows a process cross-sectional view of a Bi-0MOS element formed by an example of the manufacturing process. To explain the manufacturing process step by step, an N-type buried region 3 is formed in a P-type silicon substrate 1,
An N-type epitaxial layer 114 is formed. Then NMOST
After forming a P-well region 5 in the region where R is formed and the element isolation region of the bipolar transistor, and forming an N-well region 7 in the region where PMOSTr is to be formed, a silicon nitride layer having a predetermined shape is formed. An oxide film 6 for element isolation is formed using the nitride film as an oxidation-resistant mask.

Next, after forming the gate oxide film 8, the gate polycrystalline silicon 9
is formed to form the base region 10 of the bipolar transistor. Next, the emitter diffusion window of the bipolar transistor is opened, and the second polycrystalline silicon layer 11, which is larger than the opening size, is formed, and the second polycrystalline silicon layer 11 on the emitter is formed at the same time as the source/drain region 12 of the NMOSTr. Introduce N-type impurities into the layer. Next, source/drain regions 13 of the PMOSTr and base contact regions 14 of the bipolar transistor are formed. Next, Zetsuya Pigeon 1
After forming 5, a contact window and an aluminum wiring 16 are formed.

The above shows an example of the B1-CMOS process that supports recent high-speed processing.
There is also the use of second polycrystalline silicon to increase the speed and reduce the size of the bipolar section. As can be seen from the example of the Bi-0 MOS process shown here, as speed increases and miniaturization progress in recent years, the complexity of the process has become remarkable. Moreover, it is desired that high-voltage elements coexist with high-speed bipolar transistors at the same time, but as the current processes become more and more complex, the coexistence of high-voltage elements is a national crisis.

[Problem that the invention seeks to solve]

As described above, an object of the present invention is to provide a semiconductor device fin that can form high-speed and miniaturized bipolar and MOS elements as well as high-voltage MOS transistors without adding any additional steps to the conventional method.

[Failure to solve the problem]

The semiconductor device of the present invention includes an N-type buried layer, a P-type buried layer,
Bi-CM having an N-type well region and a P-type well region
With respect to the OS process, the source of at least one MOS type field effect transistor.

The drain region is formed by an N-type well or a P-type well.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The structure of one embodiment of the present invention and its manufacturing method are shown in Figure 1 (
a) - (shown in -).

First, as shown in FIG. 1(a), ten N type embeddings r@2. A P-type buried layer 3 is formed and an N-type epitaxial layer I@4 is grown. Next, as shown in (b), the NMOS Tr formation region 18 and the bipolar Tr isolation region 19. A P well is formed in the source/drain region 5 of the high breakdown voltage PMO8Tr, and the PMOS'I'r formation region 7 and the source/drain region 2 of the high breakdown voltage NMOSTr are formed.
0 and collector contact part 2 of bipolar transistor
A 1KN well is formed, and a thick isolation oxide film 6 is selectively formed using a silicon nitride film. Next, as shown in FIG. 2C, a gate oxide film 8°+N type gate polycrystalline silicon 9 is formed. Next, the same figure (d
As shown in l, the base region lO of the bipolar transistor
A second polycrystalline silicon layer 111m1, which is thinner than the gate polycrystalline silicon N9, is formed.
ik emitter diffusion window 1t is formed.

Next, in the same figure (as shown in el, the source/drain of NMOS Tr: /9@12 and the emitter 1 of bipolar transistor
7 is formed by, for example, arsenic ion implantation.

Next, as shown in FIG.
Later, as shown in FIG. ) Bi-0MOS is formed.

According to the structure and manufacturing method as described above, the source/drain regions of M08T can be formed by deep, low concentration wells, which has the advantage of dramatically improving the withstand voltage of N08Tr.

〔Effect of the invention〕

As explained above, by forming the source/drain regions of the MOSTr using deep, low-concentration wells, the present invention can produce a high-voltage MOS'rr and a high-speed biboelectric MOSTr without increasing the number of steps in the conventional process. - There is an advantage that large transistors and miniaturized CMOSTr can coexist.

[Brief explanation of drawings]

Figure 1 (al~(gl) is a sectional view showing one embodiment of the present invention together with the manufacturing process, and m2 is a sectional view showing the prior art.
Figure 1. 1...P-type semiconductor substrate, 2...N-type buried region, 3...P-type bill-embedded region, 4...
N-type epi region, 18... P-type well region, 6.
...Silicon oxide film, 7...N type reel region, 8...Gate oxide film, 9...Cate polycrystalline silicon% 10... ... P-type base + region, 11 ... polycrystalline silicon layer, 12 ...
...N-type source/drain region, 13...P
Type 7-y, dray/region, 14...Pfi base contact territory, 15...insulating group, 1G...electrode,
17...N-type emitter region, 19...
Insulating isolation region, 5...P5 source/drain region, 20...Nf1M source/drain region,
21...N-type collector region @Figure 7

Claims (1)

[Claims] In a semiconductor device including a silicon gate MOS field effect transistor and a bipolar transistor, a buried region of a first conductivity type, a buried region of a second conductivity type, an epitaxial layer of a first conductivity type, a well region of a first conductivity type, and a semiconductor having a well region of a second conductivity type, wherein the source/drain region of at least one MOS field effect transistor is formed by the well of the first conductivity type or the well of the second conductivity type. Device.