JPS63124575A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the parasitic capacitance of the source and the drain of a MOS transistor without impairing the improving method of a short channel effect, by making the impurity concentration in a region directly beneath the gate of the MOS transistor on the side of a substrate higher than that in other region. CONSTITUTION:The parasitic capacitance of a part other than a side surface part, where source and drain regions 2 and 7 are in contact with high concentration impurity regions 5 and 10, is determined with the impurity concentrations of semiconductor substrate 1 and 6. Therefore, the parasitic capacitance in the source and drain regions can be reduced in the low concentration semiconductor substrate 1 and 6. Since the high concentration impurity regions 5 and 10 are formed directly beneath gate electrodes 4 and 9, the threshold length of a gate, where punch through occurs between the source and the drain due to a short channel effect, can be shortened.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device equipped with a MOS (MOS) run lister, and in particular aims to reduce source/drain parasitic capacitance without impairing the short channel effect improvement effect of the MOS (MOS) run lister. Related to semiconductor devices.

[Conventional technology]

As semiconductor integrated circuits become more and more integrated into LSIs, the semiconductor elements that make up these circuits are required to be increasingly miniaturized.This miniaturization has led to reductions in gate dimensions, that is, shortened channels, in MOS transistors. Improving the short channel effect associated with this shortened channel is an important issue. P-channel M using impurities with particularly high diffusion rates
The diffusion transverse wave edge of the source and drain of the O3) Run Lister is thicker than that of the N-channel MO3) Run Lister (as is well known, this transverse wave radius affects the N-type impurity concentration in the P-channel MOS transistor region.

Conventionally, as a means to solve this problem, the methods shown in Figs. 3(a) and (b)
) have a structure exemplified by an N-channel MOS transistor and a P-channel MO3I-run lister, respectively.

As shown in the figure, the N-channel MO3I-run lister includes a P-well layer 22 formed in a P-type semiconductor substrate 21, and an N-type diffusion layer 24. A gate insulating film 26 and a gate electrode 27 are formed. In addition, for the P channel MOS transistor, an N well layer 23 is formed on the same semiconductor substrate 21, and a P channel MOS transistor is formed on the same semiconductor substrate 21.
A type diffusion layer 25, a gate insulating film 28, and a gate electrode 29 are formed.

Then, by increasing the impurity concentration of both the wells 1g22 and 23 with respect to the semiconductor substrate 21, each of the MO
N-type diffusion layer 24 of S transistor. The structure was such that the short channel effect of the source/drain regions made of the P-type diffusion layer 25 is suppressed.

[Problem that the invention seeks to solve]

In the conventional structure described above, since the impurity concentration in the well regions 22 and 23 is increased, the short channel effect in the source and drain regions of the MOS (MOS) Run Lister is improved, but the parasitic capacitance in the source and drain regions increases. A problem arises in that this junction capacitance causes a reduction in the operating speed of a circuit constituted by a MOS (MOS) run lister.

The present invention provides a method for improving short-channel effects (MOS) without compromising short-channel effect improvement measures.
An object of the present invention is to provide a semiconductor device that can reduce the source/drain parasitic capacitance of a Runristor.

[Means for solving problems]

The semiconductor device of the present invention has a structure in which the impurity concentration on the substrate side in the region immediately below the gate of the MOS (MOS) run lister is higher than in other regions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

(First Embodiment) FIGS. 1A and 1B are cross-sectional views of an N-channel transistor and a P-channel transistor, respectively, in an embodiment of the present invention.

In FIG. 1(a), a P-type semiconductor substrate 1 has a source and
An N-type diffusion layer 2.2 is formed as a drain region, and the gate insulating film 3 and gate electrode 4 formed on the substrate surface constitute an N-channel MO3I-run lister. and,
Here, a P-type impurity is introduced into the semiconductor substrate 1 directly under the gate electrode 4 at a higher concentration than this to form a P-type high concentration impurity region 5.

Further, in FIG. 1(b), a P-type diffusion layer 7.7 as a source/drain region is formed on the N-type semiconductor substrate 6, and a gate insulating film 8 and a gate electrode 9 are formed on the substrate surface.
This constitutes a P-channel MO3I-run lister. Here, N-type impurities are introduced into the semiconductor substrate 6 directly under the gate electrode 9 at a higher concentration than this to form an N-type high concentration impurity region 10.

According to this structure, the parasitic capacitance of the side surface portions where the source/drain regions 2.7 are in contact with the high concentration impurity regions 5.10, respectively, is the same as that of the conventional one, but the parasitic capacitance of other portions is the same as that of the semiconductor substrate 1. Since the impurity concentration is determined by an impurity concentration of .6, the parasitic capacitance in the source/drain region can be reduced in a semiconductor substrate with a lower concentration of 1.6 than in a conventional well layer.

Further, since the high concentration impurity regions 5 and 10 are formed directly under the gate electrode 4.9, the source/drain regions 2.
The transverse wave caused by the heat treatment step 7 is the same as that of the conventional method. Therefore, by setting the concentration of this high concentration impurity region 5.10 to be the same as the concentration of the conventional well, the critical gate length for punch-through between the source and drain due to the short channel effect can be secured to the same extent as in the conventional well. can.

In other words, as long as a MOS transistor with the same parasitic capacitance as the conventional one is manufactured, the critical gate length of the MOS run lister of the present invention can be made much shorter.

(Second Embodiment) FIGS. 2(a) and 2(b) are cross-sectional views of an N-channel MOS transistor and a P-channel MOS transistor in a second embodiment of the present invention. In these figures, the same parts as in FIG. 1 are designated by the same reference numerals.

In this structure, a P-type semiconductor substrate 11 is configured as a common substrate, a P-well layer 12 is formed on this substrate 11 as shown in FIG. 2(a), and an N-type diffusion N2. A gate insulating film 3 and a gate electrode 4 are formed, and a P highest concentration impurity region 5 with a higher concentration than the P well layer 12 on the substrate side is formed directly below the gate electrode 4 to form an N-channel MO3) run lister. There is.

Further, as shown in FIG. 2(b), an N-well J'i13 is formed in the P-type semiconductor substrate 11, and a P-type diffusion layer 7. A gate insulating film 8 and a gate electrode 9 are formed, and an N-type high concentration impurity region 10 with a higher concentration than the N well 1J13 is further formed directly under the gate electrode 9 to constitute a P channel MOS transistor.

Note that an N-type semiconductor substrate may be used.

In this configuration as well, the source
While the parasitic capacitance in the diffusions N2 and 7 serving as the drain region can be reduced, the punch-through limit gate length between the source and drain due to the short channel effect can be reduced by the high concentration impurity regions 5 and 10.

This embodiment is effective when forming a composite element of an N-channel MO3) run lister and a P-channel MO3) run lister.

〔Effect of the invention〕

As explained above, in the present invention, the impurity concentration on the substrate side in the region directly under the gate of the MO3I-run lister is made higher than in other regions, so that the impurity concentration in the source of the MOS transistor is achieved without impairing the conventional short channel effect improvement measures. - Drain parasitic capacitance can be significantly reduced, and a semiconductor device with high circuit operation speed can be obtained.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) show N of the first embodiment of the present invention, respectively.
Channel MO3) Run lister and P channel MO3I-
2(a) and (b) are cross-sectional views of a run lister, and FIG. 3(a) is a cross-sectional view of an N-channel MOS transistor and a P-channel MOS transistor, respectively, according to a second embodiment of the present invention.
and (b) are cross-sectional views of a conventionally structured N-channel MO3) run lister and P-channel MO3I-run lister. 1... P-type semiconductor substrate, 2... N-type diffusion layer, 3...
・Gate insulating film, 4... Gate electrode, 5... P wall high concentration impurity region, 6... N type semiconductor substrate, 7... P
Type diffusion layer, 8... Gate insulating film, 9... Gate electrode, 10... N type high concentration impurity region, 11... P type semiconductor substrate, 12... P well layer, 13... - N well layer, 21... P type semiconductor substrate, 22... P well layer, 23... N well layer, 24... N type diffusion layer, 25
...P-type diffusion layer, 26...gate insulating film, 27...
- Gate electrode, 28... Gate insulating film, 29... Gate electrode. 1', 3,) Part (a) Part (a) Part: Fig. 2, 5) Fig. 3 (1))

Claims (3)

[Claims] (1) In a semiconductor device including a MOS transistor constituted by a diffusion layer as a source/drain region formed on one main surface of a semiconductor substrate and a gate electrode formed on this one main surface with an insulating film interposed therebetween, 1. A semiconductor device characterized in that the impurity concentration on the base side in a region immediately below the gate of a MOS transistor is higher than in other regions. (2) The semiconductor device according to claim 1, wherein the concentration of the semiconductor substrate directly under the gate is higher than that of other parts. (3) The semiconductor device according to claim 1, wherein the well layer directly under the gate is formed to have a higher concentration than other parts.