JPH04142039A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture a semiconductor device which is fine and whose reliability is high by a method wherein, in a state that sidewall spacers are formed at a gate electrode and an offset film laminated on its upper part, a high-concentration impurity region is formed, and, after that, the offset film and the sidewall spacers are etched back. CONSTITUTION:A gate electrode 13 where an offset film 17 is laminated on the upper part is formed on a semiconductor substrate 11; first impurity regions 15 whose impurity concentration is relatively low are formed in the semiconductor substrate 11 by making use of the gate electrode 13 as a mask. Sidewall spacers 14 are formed at side parts of the gate electrode 13 and the offset film 17; second impurity regions 16 whose impurity concentration is relatively high are formed in the semiconductor substrate 11 by making use of the gate electrode 13 and the sidewall spacers 14 as a mask. The offset film 17 and the sidewall spacers 14 are etched back. Thereby, it is possible to manufacture a semiconductor device which is fine and whose reliability is high.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a semiconductor device called an LDD structure, in which an electric field near a high concentration impurity region is relaxed by an offset by a low concentration impurity region. This relates to a manufacturing method.

[Summary of the Invention] The present invention provides a method for manufacturing a semiconductor device as described above.
By forming a high tM impurity region with a sidewall spacer formed on the gate electrode and the offset film laminated on top of the gate electrode, and then etching back the offset film and sidewall spacer, a fine and reliable impurity region can be formed. This makes it possible to manufacture semiconductor devices with high orbital characteristics.

[Conventional technology]

There is an LDD structure as a structure that alleviates the deterioration of various characteristics of a MOS (MOS) transistor due to the presence of carriers or changes over time.

In a MOS transistor, a gate electrode 13 is formed on a gate oxide film 12 on the surface of a semiconductor substrate 11 as shown in FIG. 2, but in an LDD structure, sidewall spacers 14 are formed on the sides of the gate electrode 13. ing.

The N-diffusion Ji 15 is formed using the gate electrode 13 as a mask, while the N-diffusion layer 16 is formed using the gate electrode 13 and sidewall spacer 14 as a mask.

Therefore, the N-diffusion layer 15 is left under the sidewall spacer 14, and the electric field near the drain region, which is one of the N-diffusion layers 16, is relaxed by the offset caused by the 20N-diffusion layer 15.

[Problem to be solved by the invention]

However, with the miniaturization of semiconductor devices, the thickness H of the gate electrode 13 is also becoming thinner in order to reduce the vertical step difference.

As a result, the width of the side wall spacer 140 becomes narrower.

The offset caused by the N-diffusion layer 15 is also becoming smaller.

When the design rule reaches the half-micron level, the offset measurement becomes insufficient and the electric field near the N° diffusion layer 16 cannot be sufficiently relaxed.

One way to solve this problem is to increase the impurity concentration of the N-diffusion layer 15 and widen the N-diffusion layer 15 in the channel direction to ensure an offset measurement.

However, in this method, the N- diffusion layer 15 also expands in the depth direction, increasing the junction depth X and deteriorating the punch-through breakdown voltage.

[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes an offset film 1
forming a gate electrode 13 on which a gate electrode 7 is laminated on the semiconductor substrate 11; using the gate electrode 13 as a mask, forming a first impurity region 15 having a relatively low impurity concentration on the semiconductor substrate 11; A sidewall spacer 14 is formed on the side of the gate electrode 13 and the offset film 17, and a second impurity region 16 having a relatively high impurity concentration is formed using the gate electrode 13 and the sidewall spacer 14 as a mask. It is formed on the semiconductor substrate 11, and the offset film 17 and the sidewall spacer 14 are etched and banked.

(Function) In the method for manufacturing a semiconductor device according to the present invention, the gate electrode 1
Since the sidewall spacer 14 is formed on the side of the gate electrode 130 and the offset film 17, the sidewall spacer 14 is formed on the side of the gate electrode 130.
It's wide.

Since the sidewall spacer 14 is also used as a mask when forming the second impurity region 16, the first impurity '#J
The offset measurement due to region 15 is large. Therefore, the second
The electric field near the impurity region 16 can be sufficiently relaxed.

Moreover, the offset film 17 and the sidewall spacer 14 are
Since the etch hack is performed after the impurity region 16 is formed, the step height does not increase.

(Embodiment) Hereinafter, an embodiment of the present invention applied to the manufacture of an N-channel MO3I-transistor will be described with reference to FIG.

In this embodiment, as shown in FIG. 1A, a gate oxide film 12 is formed on the surface of a semiconductor substrate 11, and a conductive film such as a polycrystalline Si film and a 5iOz film are sequentially formed on this gate oxide film 12. Laminated on.

Then, by patterning these SiO□ films and conductive films, an offset made of a 5iO7 film is formed.

A gate electrode 13 is formed on which a gate film 17 is laminated.

Thereafter, using the gate electrode 13 as a mask, the semiconductor substrate 11 is
An N- diffusion layer 15 is formed in the semiconductor substrate 11 by ion-implanting N-type impurities into the semiconductor substrate 11 at a low concentration.

Next, a SiO□ film is deposited on the entire surface by CVD, and this Si
By etching and puncturing the O2 film, sidewall spacers 14 made of a SiO□ film are formed on the sides of the gate electrode 13 and the offset film 17, as shown in FIG. 1B.

Thereafter, N type impurities are ion-implanted into the semiconductor substrate 11 at a high concentration using the gate electrode 13 and the sidewall spacers 14 as masks, thereby forming an N diffusion layer 16 in the semiconductor substrate 11.

Next, as shown in FIG. 1C, the offset film 17 and the sidewall spacer 14 are etched and hacked until the offset film 17 is removed.

In this embodiment as described above, the film thickness H of the gate electrode 13 is the same as in the case of FIG.
Since the sidewall spacer 14 is formed on the side of the offset film 17, the width of the sidewall spacer 14 when forming the N₂ diffusion layer 16 is wider than in the case of FIG.

Therefore, in order to reduce the level difference, the offset film 17 and the sidewall spacer 14 are etched and hacked after the N diffusion layer 16 is formed, so that the width of the sidewall spacer 14 is finally equal to that in the case of FIG. Even so, the offset due to the N- diffusion layer 15 is larger than in the case of FIG.

As a result, the electric field near the drain region, which is one of the N diffusion layers 16, can be sufficiently relaxed.

Incidentally, increasing the offset measurement can alleviate deterioration of transistor characteristics due to hot carriers, but the resistance value of the N-diffusion layer 15 increases and the driving ability of the transistor decreases, and the two are in a trade-off relationship. be.

Therefore, in the above embodiment, the offset value is constant for all transistors, but the offset value is adjusted according to the duty ratio of each transistor, that is, the ratio of the usage time of each transistor to the usage time of the IC, and the drive capacity can be improved. It is also possible to obtain a plurality of different types of transistors.

That is, for transistors having a small duty ratio and requiring little consideration of deterioration of characteristics, it is possible to obtain a large drive capability by reducing the offset measurement.

In order to adjust the offset measurement in this way, the thickness of the offset film 17 and the thickness of the offset film 17 and the side wall spacer 1 are
It is sufficient to adjust at least one of the etch hack amount and the amount of etch hack with respect to 4 in accordance with the duty ratio, and form the N' diffusion layer 16 in a state in which the width of the sidewall spacer 140 differs in accordance with the duty ratio.

Although the above-described embodiments apply the present invention to the manufacture of N-channel Os transistors, the present invention can also be applied to the manufacture of P-channel Mos transistors and the like.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to the present invention, it is possible to sufficiently relax the electric field near the second impurity region without increasing the step height, and therefore it is possible to manufacture a fine semiconductor device with high reliability. .

[Brief explanation of the drawing]

Fig. 1 is a side sectional view sequentially showing one embodiment of the present invention;
The figure is a side sectional view of a MOS transistor manufactured according to a conventional example of the present invention. In addition, in the symbols used in the drawings, 11 --------1 Semiconductor substrate 13 -----1 ---- Gate electrode 14 ---- Side wall spacer 15 - ・ -------N- Diffusion layer 16 ---N Diffusion layer 17 --- Offset film.

Claims (1)

[Claims] A gate electrode on which an offset film is laminated is formed on a semiconductor substrate, and a first impurity region having a relatively low impurity concentration is formed on the semiconductor substrate using the gate electrode as a mask. a sidewall spacer is formed on a side of the gate electrode and the offset film, and a second impurity region having a relatively high impurity concentration is formed in the semiconductor substrate using the gate electrode and the sidewall spacer as a mask. A method of manufacturing a semiconductor device, further comprising etching back the offset film and the sidewall spacer.