JPS621276A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To speed up operation, to increase withstanding voltage and to fine an element by forming source-drain regions by utilizing a gate electrode and shallowing junction depth and lowering impurity concentration at the lower position of a projecting section in a second electrode layer. CONSTITUTION:An insulating isolation region 12 is formed onto a P-type silicon substrate 11, a gate insulating film 13 is shaped in an element region by a thin silicon oxide film, a polysilicon layer 14 is applied onto the insulating film 13, resistance is lowered, and a molybdenum silicide layer 15 is superposed and applied onto the layer 14. The molybdenum silicide layer 15 and the polysilicon layer 14 are etched while using a resist layer 16 shaped according to a pattern so as to be made longer than gate length as a mask. A gate electrode 17 is formed by a first electrode layer 14a and a second electrode layer 15a, and both ends of the second electrode layer 15a are projected to both sides from the first electrode layer 14a. The resist layer 16 is removed, arsenic ions are implanted, and a source region 18 and a drain region 19 are shaped through a self-alignment manner.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS type semiconductor device, and particularly to an MO5 type semiconductor device in which elements are miniaturized and operation speed is increased.

[Conventional technology]

In recent years, as semiconductor devices, especially MOS type semiconductor devices, have become highly integrated and operate at high speeds, MOAs with the structure shown in FIG.
S-type field effect transistors have been proposed. That is, in this MOS type field effect transistor 1, the gate electrode 2 has a two-layer structure, the lower layer 3 is made of polysilicon doped with phosphorus, and the upper layer 4 is made of silicide, which is a high melting point metal, in order to lower the resistance. ing. Further, the source region 5 and the drain region 6 are each formed by a self-alignment method using the gate electrode 2, and the impurity layers constituting the source region 5 and the drain region 6 reduce layer resistance and increase speed. In order to achieve this, the junction is relatively deep and the impurity concentration is high.

On the other hand, in order to miniaturize the MOS field effect transistor, its gate length is made as small as possible.
AlW, 10 is a semiconductor substrate.

[Problem that the invention seeks to solve]

In the above-mentioned conventional MOS field effect transistor, the gate length is further shortened in order to miniaturize the device. An electric field will be concentrated at the drain end of the electrode 2, and this electric field will cause hot carriers to be injected into the gate insulating film, degrading the characteristics of the MOS field effect transistor, resulting in a so-called decrease in drain breakdown voltage.

For this reason, a structure (LDD structure) in which the impurity concentration on the gate side of the source/drain region is lowered has been proposed, but this structure requires at least two impurity doping steps and the manufacturing process is slow. The problem is that it gets complicated.

[Means for solving problems]

The MOS semiconductor device of the present invention has the following features in order to achieve high-speed operation, improved breakdown voltage, and miniaturization of elements.
The gate electrode is composed of at least two layers, a first and a second electrode layer, and both ends of the upper second electrode layer extend from the first electrode layer to both sides, while the source/drain regions are formed from the gate electrode. formed by a self-alignment method using
Further, the junction depth and the impurity concentration are configured to be shallower and lower at a position below the projecting portion of the second electrode layer than at other portions.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG.
) to (C) show the manufacturing process diagrams.

To explain this according to the manufacturing process, first, Figure 2 (a)
A selective oxidation method (LO
An insulating isolation region 12 between elements is formed using a thick silicon oxide film (CO3 method), and a gate insulating film 13 is formed in the element region using a thin silicon oxide film. A polysilicon layer 14 is deposited thereon by the CVD method, and phosphorus is thermally diffused into the polysilicon layer 14 to lower the resistance. Furthermore, on top of that, molybdenum silicide (M
oSi, ) layer 15 is formed by sputtering for 1,000 to 30
Coat in layers to a thickness of 0.00 mm.

Next, as shown in FIG. 2(b), using a resist layer 16 patterned by photolithography to be somewhat longer than the gate length as a mask, the upper molybdenum layer is etched using reactive sputter etching. A silicide layer 15 is formed by etching. Subsequently, the polysilicon layer 14 is etched, and by adjusting the etching conditions appropriately, side etching is performed by about 0.2 μm so that the polysilicon layer 14 has the original gate length. As a result, the gate electrode 17 is constituted by the lower first electrode layer 14a made of the polysilicon layer 14 and the upper second electrode layer 15a made of the molyb silicide layer 15, and the second electrode layer 15a is configured such that its both ends extend beyond the first electrode layer 14a.

Then, after removing the resist layer 16, as shown in FIG.
As shown in C), using the gate electrode 17 as a mask, N
Arsenic is ion-implanted as a type impurity to form the source region 18.
And a drain region 19 is formed by a self-alignment method.

At this time, the ion acceleration energy is set to such an extent that a portion of the implanted ions can pass through the second electrode layer 15a. As a result, in the source region 18 and drain region 19, the impurity regions 18a and 19a with high concentration and deep junction outside the second electrode layer 15a and the second electrode layer 1
The impurity regions 18b, 1 with a low concentration and a shallow junction formed by the impurities partially passed through by the impurity 5a
9b are respectively configured.

Thereafter, the glabellar insulating film 20 and the contact holes 21 . ．． 22 and an aluminum wiring layer 23, the MOS type field effect transistor shown in FIG. 1 can be completed.

According to the above configuration, most of the source region 18 and drain region 19 are high concentration regions 18a.

19a, it is possible to reduce the resistance and achieve high-speed operation. On the other hand, since low concentration regions 18b and 19b are formed on the gate electrode 17 side, especially in the drain region 19. Concentration of electric field can be alleviated and breakdown voltage can be improved. This makes it possible to reduce the gate length and miniaturize the device, and also to improve the breakdown voltage and achieve faster operation.

Furthermore, in the above configuration, if the second electrode layer 15a is formed on the gate electrode 17 and extends to both sides of the first electrode layer 14a, the source/drain regions 18 and 19 can be formed by a self-alignment method. Since the source/drain regions having high and low concentration regions can be naturally formed by simply using the above steps, a significant increase in the number of manufacturing steps can be avoided and manufacturing can be facilitated.

In the above embodiment, an N-channel MOS field effect transistor is formed on a P-type silicon substrate, but a P-channel MOS field-effect transistor may be formed by introducing P-type impurities into an N-type semiconductor substrate. It's okay. Furthermore, the semiconductor substrate is not limited to a single conductivity type semiconductor substrate, and a semiconductor substrate having a well structure may be used. Furthermore, as impurities, a plurality of ions such as arsenic and phosphorus may be combined.

On the other hand, the gate electrode is not limited to a two-layer structure, but may have a multilayer structure of three or more layers, and these materials may be any combination of polysilicon, metal silicide, metal, etc., and an insulating film may be used as the upper layer. May be used.

〔Effect of the invention〕

As explained above, in the MOS type semiconductor device of the present invention, the second electrode layer of the multilayered gate electrode is extended to both sides beyond the first electrode layer, and the source under this extended portion is・Since the drain region is configured with a shallower junction and lower impurity concentration than other parts, the drain breakdown voltage can be improved even by reducing the gate length, and it is also possible to improve the drain breakdown voltage by reducing the gate length. The resistance can be lowered by concentration and deep junction depth, which has the effect of achieving miniaturization of semiconductor elements, higher breakdown voltage, and faster operation.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an embodiment of the MOS semiconductor device of the present invention, FIGS. 2(a) to (c) are cross-sectional views for explaining the manufacturing process, and FIG. 3 is a cross-sectional view of a conventional semiconductor device. It is a diagram. DESCRIPTION OF SYMBOLS 1... MOS field effect transistor, 2... Gate electrode, 5... Source region, -6... Drain region, 7... Gate insulating film, 10... Semiconductor substrate, 11
... silicon substrate, 12 ... inter-element insulation isolation region,
13... Gate insulating film, 14... Polysilicon layer,
14a... First electrode layer, 15... Molypsilicide layer, 15a... Second electrode layer, 16... Resist layer, 17... Gate electrode, 18... Source region, 1
8b...Low concentration region, 19...Drain region, 19
b...Low concentration region, 20...Interlayer insulating film, 23...
・Aluminum wiring layer. Figure 1 Figure 3

Claims (1)

[Claims] 1. In a semiconductor device having a MOS field effect transistor in which the gate electrode is configured in two layers, at least a lower first electrode layer and an upper second electrode layer, both ends of the second electrode layer are The source/drain regions are formed by a self-alignment method using this gate electrode, while the source/drain regions are formed by a self-alignment method using this gate electrode. 1. A MOS semiconductor device comprising a region having a shallower junction depth and lower impurity concentration than the region.