JPH0521454A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To comparatively simply form a high-reliability MOS transistor with an LDD structure. CONSTITUTION:A polycrystalline silicon layer 4 is formed on a gate insulating film 3 and a high-melting-point metal silicide layer 5 formed sequentially on it; then, a gate electrode by an eaves structure wherein the gate size of the high-melting-point metal silicide layer 5 in a channel direction is longer than the size of the polycrystalline silicon layer 4 is formed. After that, impurity ions are implanted with an acceleration voltage which transmits through the high-melting-point metal silicide layer 5 but which does not transmit through the polycrystalline silicon layer 4; an N<-> type drain region 7 and an N<-> type source region 6, whose impurity concentration is comparatively thin, are formed. In addition, impurity ions are implanted at an acceleration voltage at which the high-melting-point metal silicide layer 5 acts as a mask; an N-type drain region 9 and an N-type source region 8, whose impurity concentration is comparatively thin, are formed. Thereby, a MOS transistor, by an LDD structure, whose high reliability can be ensured can be formed by a comparatively simple manufacturing process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device.

[0002]

2. Description of the Related Art The main cause of fluctuations in various characteristics of a fine N-channel MOS transistor is hot electrons in a high electric field near the drain region. Therefore, in order to obtain a highly reliable element, this electric field is relaxed. I have to let them do it. For this purpose, the conventional LDD (Lightly Dop)
An ed drain structure having a smoothed impurity distribution in the drain region is produced.

FIG. 3 is a sectional view of an example of a conventional MOS transistor having an LDD structure.

A field insulating film 2 is formed on a P-type silicon substrate 1.
Are formed to partition the element region, and the gate insulating film 3 is formed in the element region. A gate electrode 14 is formed of a polycrystalline silicon layer, and a silicon oxide film 15 having an inclined surface is formed on the side wall of the gate electrode 14. An N-type impurity such as phosphorus is ion-implanted to form N-type regions 16 and 17 having a gradient concentration, an N-type source region 8 and a drain region 9 to obtain an LDD structure MOS transistor.

The N-type regions 16 and 17 in which the impurity concentration changes in proportion to the silicon oxide film having the inclined surface are for alleviating a high electric field in the source and drain regions.

[0006]

However, in order to obtain the above-mentioned LDD structure, it is necessary to form the silicon oxide film 15 having an inclined surface, but it is not easy to form this silicon oxide film 15. It has the drawback of lengthening the manufacturing process and increasing the number of steps.

An object of the present invention is to provide a method of manufacturing a semiconductor device which can relatively easily form a highly reliable MOS transistor with an LDD structure.

[0008]

According to the present invention, in a gate electrode comprising two layers of a polycrystalline silicon layer and a refractory metal silicide layer, the dimension of the refractory metal silicide layer in the channel direction is polycrystalline silicon. Forming a pattern larger than the dimension of the layer in the channel direction, and then implanting impurity ions at an accelerating voltage that transmits the refractory metal silicide layer but not the polycrystalline silicon layer; The feature is that the impurity ions are implanted at an acceleration voltage that does not permeate the silicide layer or the polycrystalline silicon layer.

[0009]

The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor device according to a manufacturing process of an embodiment of the present invention.

First, as shown in FIG. 1A, a field insulating film 2 is formed on a P-type silicon substrate 1 to divide an element region, and a gate insulating film 3 is formed in the element region. A polycrystalline silicon layer 4 and a refractory metal silicide (for example, tungsten silicide) layer 5 thereon are each formed to a thickness of 100 nm.
A gate electrode having a two-layer structure is formed by sequentially forming the gate electrodes with a certain thickness. Next, general lithography and reactive
After forming the gate pattern by ion etching or the like, buffered hydrofluoric acid (for example, HF: NH ₄ F = 3:
80), the structure of the gate electrode is set so that the gate dimension of the tungsten silicide layer 5 is 200 nm in the channel direction more than the dimension of the polycrystalline silicon layer 4.
The eaves structure is formed to have a relatively long length. Figure 1
It shows in (b). When N-type impurity ions such as phosphorus are implanted thereafter, the eaves structure is utilized to first implant the tungsten silicide layer 5 at an accelerating voltage of, for example, about 100 keV, which does not penetrate the polycrystalline silicon layer. Relatively thin N ^- type drain region 7
And the source region 6 is formed. This is shown in FIG. Further, arsenic ions are added to the tungsten silicide layer 5
Are implanted at an accelerating voltage serving as a mask, for example, about 70 keV to form the N-type drain region 9 and the source region 8 having a relatively high impurity concentration. This is shown in FIG. As a result, the LDD structure can be formed relatively easily and accurately.

FIG. 2 is a sectional view of another embodiment of the present invention. The gate electrode formed on the P-type silicon substrate 1 via the gate insulating film 3 has a two-layer structure similar to that of the first embodiment. In this embodiment, only the gate electrode near the drain, which is a problem in terms of reliability, has an eaves structure, and by implanting impurity ions in two separate steps by selecting the ion species and acceleration voltage, only the drain side can be injected. An LDD structure in which an N ⁻ type drain region 7 having a relatively low impurity concentration for relaxing a high electric field is formed can be obtained.

[0012]

As described above, according to the present invention, a polycrystalline silicon layer formed via a gate insulating film on a semiconductor substrate and a refractory metal silicide layer thereon are sequentially formed to form a refractory metal. After forming the gate electrode so that the dimension of the silicide layer in the channel direction is larger than the dimension of the polycrystalline silicon layer in the channel direction, impurity ions are transmitted through the refractory metal silicide layer but are transmitted through the polycrystalline silicon layer. It is relatively easy to perform LD by implanting at an acceleration voltage that does not
This has the effect that a highly reliable MOS transistor can be formed with the D structure.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device, which is shown in order of steps for explaining an embodiment of the present invention.

FIG. 2 is a sectional view of a semiconductor device for explaining another embodiment of the present invention.

FIG. 3 is a cross-sectional view of an element for explaining an example of a conventional method for manufacturing a MOS transistor having an LDD structure.

[Explanation of symbols]

1 P-type silicon substrate 2 Field insulating film 3 Gate insulating film 4 Polycrystalline silicon layer 5 Refractory metal silicide layer 6 N ⁻ type source region 7 N ⁻ type drain region 8 N type source region 9 N type drain region 14 Gate electrode

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 21/265 8617-4M H01L 21/265 L

Claims (1)

Claim: What is claimed is: 1. A step of sequentially forming a polycrystalline silicon layer and a refractory metal silicide layer on a gate insulating film provided on a semiconductor substrate, and a step of forming the refractory metal silicide layer. Forming a gate electrode so that the dimension in the channel direction is larger than the dimension in the channel direction of the polycrystalline silicon layer;
A step of implanting impurity ions at an accelerating voltage that allows the refractory metal silicide layer of the gate electrode to pass through but does not pass through the polycrystalline silicon layer; and the refractory metal silicide layer and the polycrystalline silicon layer of the gate electrode as well. And a step of implanting impurity ions at an accelerating voltage that does not permeate the semiconductor device.