JPS6229168A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6229168A JPS6229168A JP16743685A JP16743685A JPS6229168A JP S6229168 A JPS6229168 A JP S6229168A JP 16743685 A JP16743685 A JP 16743685A JP 16743685 A JP16743685 A JP 16743685A JP S6229168 A JPS6229168 A JP S6229168A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- polysilicon
- metal
- substrate
- metal silicide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 32
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 9
- 239000012535 impurity Substances 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- -1 arsenic ions Chemical class 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000000151 deposition Methods 0.000 abstract 1
- 230000008020 evaporation Effects 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 43
- 238000005468 ion implantation Methods 0.000 description 7
- 238000009792 diffusion process Methods 0.000 description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 239000011733 molybdenum Substances 0.000 description 4
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910018503 SF6 Inorganic materials 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229960000909 sulfur hexafluoride Drugs 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、ＭＯＳ型の半導体装置の製造方法に関し、
特にＬＤＤ構造ＭＯ８ＦＥＴ製造方法を簡易化できるよ
うにしたものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a MOS type semiconductor device.
In particular, it is possible to simplify the manufacturing method of MO8FET with LDD structure.
（従来の技術）
第２図は従来のＭＯ８型半導体装置の製造工程を示すも
のであり、まず、第２図（＆）に示すように、Ｓｌ基板
１上に素子分離用酸化膜２、ゲート酸化膜３、ゲート電
極４を順次形成して、ゲート電極４となる部分の上面に
レジスト５を塗布してエツチングを行い、ゲート酸化膜
３とゲート電極４となる部分以外を除去した後、第２図
ら）に示すようにレジスト５を除去する。(Prior Art) FIG. 2 shows the manufacturing process of a conventional MO8 type semiconductor device. First, as shown in FIG. After sequentially forming the oxide film 3 and the gate electrode 4, applying a resist 5 on the upper surface of the part that will become the gate electrode 4 and performing etching, and removing the part other than the part that will become the gate oxide film 3 and the gate electrode 4, The resist 5 is removed as shown in Figure 2 et al.
次いで、この第２図（ｂ）に示すように、Ｓｌ基板１内
にドレイン・ソース電極となる不純物拡散層を形成する
ために、イオン６の注入を行い、第２図（ｃ）に示すよ
うに、ｎ一層７を形成する。Next, as shown in FIG. 2(b), ions 6 are implanted in order to form impurity diffusion layers that will become drain and source electrodes in the Sl substrate 1, and as shown in FIG. 2(c). Then, n layers 7 are formed.
次いで、第２１１（ｄ）に示すように、上面にゲート側
壁用酸化膜８を形成し、第２図（ｅ）に示すように、ゲ
ート電極４とゲート酸化膜３の側面のみにゲート側壁用
酸化膜８を残して残りは全部除去する。Next, as shown in FIG. 211(d), a gate sidewall oxide film 8 is formed on the upper surface, and as shown in FIG. The rest is completely removed except for the oxide film 8.
次に、第２図（ｆ）に示すように、このゲート側壁用酸
化膜８とゲート電極４をマスクとして、第２回目のイオ
ン９の注入を行うと、第２図□□□）に示すように、ｎ
層１０が形成され、ｎ′″層７はゲート酸化膜３の斜め
下にのみ形成されることになる。その後、図示しないが
、Ａｔ配線および各電極と配線を接続するためのフンタ
クトホール、絶縁膜などを形成する。Next, as shown in FIG. 2(f), a second implantation of ions 9 is performed using this gate sidewall oxide film 8 and gate electrode 4 as a mask, as shown in FIG. Like, n
The layer 10 is formed, and the n''' layer 7 is formed diagonally below the gate oxide film 3.After that, although not shown, holes for connecting the At wiring and each electrode to the wiring are formed. Form an insulating film, etc.
上記ゲート電極４用の材料として従来多結晶シリコン（
以降ポリシリコンと呼ぶ）が用いられており、またソー
ス会ドレイン電極となるＳｌ基板１内の拡散層は、ポリ
シリコンによるゲート電極部分をホトリソ・エツチング
工程によって形成した後、イオン注入法により、電気的
に活成な不純物をＳｌ基板１に打ち込み、ゲート電極４
が形成された部分では、ポリシリコン層により上記不純
物がＳｌ基板１中には入り込まず、ゲート電極４が形成
されていない部分のみに不純物が打ち込まれ、拡散層を
形成する自己整合法（以下、セル７アラインと呼ぶ）に
より製造されてきた。Conventionally, polycrystalline silicon (
The diffusion layer in the Sl substrate 1, which will become the source/drain electrode, is formed by forming the gate electrode part of polysilicon by a photolithography/etching process, and then by ion implantation. A highly active impurity is implanted into the Sl substrate 1 to form the gate electrode 4.
In the area where the gate electrode 4 is formed, the impurity does not enter into the Sl substrate 1 due to the polysilicon layer, and the impurity is implanted only into the area where the gate electrode 4 is not formed, thereby forming a diffusion layer using the self-alignment method (hereinafter referred to as It has been manufactured by Cell 7 Align).
また、素子の微細化に伴い、ドレイン近傍が高電界にな
り、これにより発生したホットキャリアがゲート酸化膜
３中に注入され、ＭＯ８型半導体装置の特性劣化（しき
い値電圧の上昇と相互コンダクタンスの低下）を引き起
こすため、ゲート電極４近傍のソース番ドレイン部分の
拡散層の不純物濃度を低下させるＬＤＤ構造（Ｌｉｇｈ
ｔｌｙ ＤｏｐｅｄＤｒａｉｎ ）となってきた。In addition, with the miniaturization of devices, a high electric field is generated near the drain, and hot carriers generated thereby are injected into the gate oxide film 3, resulting in deterioration of the characteristics of the MO8 type semiconductor device (increase in threshold voltage and mutual conductance). Therefore, an LDD structure (Light
Try DopedDrain).
ＬＤＤ構造をセル７アラインで実現する之めには、ゲー
ト電極４を形成した後、上述のように第２図（ｂ）のご
とく低濃度でイオン６の注入を行い、次にゲート側壁用
酸化膜８を堆積させ（第２図（ｄ））、反応性イオンエ
ツチングを行ってゲート！極側面にイオン注入のマスク
となるようにゲート側壁用酸化膜８を残し、２回目のイ
オン注入を高濃度で行い拡散層を形成する（たとえば、
アイ） ＩＪプルＪｏｕｒｎａｌ ｏｆ ５ｏｌｉｄ−
ｓｔａｔｅ Ｃ１ｒｃｕｉｔｓ、Ｖｏｌ ５ｃ−１７゜
Ｎｎ ２ Ａｐｒｉｌ １９８２ ）。In order to realize the LDD structure by aligning the cells 7, after forming the gate electrode 4, ions 6 are implanted at a low concentration as shown in FIG. A film 8 is deposited (FIG. 2(d)) and reactive ion etching is performed to form the gate! The gate sidewall oxide film 8 is left on the extreme side surface to serve as a mask for ion implantation, and a second ion implantation is performed at a high concentration to form a diffusion layer (for example,
I) IJPuru Journal of 5olid-
state C1rcuits, Vol 5c-17°Nn 2 April 1982).
（発明が解決しようとする問題点）
しかし、以上述べた従来の製造方法ではイオン注入工程
が２度行うわけであるが、２回目のイオン９の注入の前
にゲート電極側壁のゲート側４ｙ用酸化膜８を形成し、
エツチング工程が必要で、さらにこのエツチングの際に
８１基板１にエツチングによる損傷を引き起こしやすい
という問題点かあつた。(Problem to be Solved by the Invention) However, in the conventional manufacturing method described above, the ion implantation process is performed twice, but before the second implantation of ions 9, the forming an oxide film 8;
Another problem was that an etching process was required, and the 81 substrate 1 was likely to be damaged by etching during this etching.
この発明は、前記従来技術がもっている問題点のうち、
ゲート側壁用酸化膜を形成する際の工程数が増大し、か
つ８１基板が損傷するという点について解決した半導体
装置の製造方法を提供するものである。This invention solves the problems of the above-mentioned prior art.
The object of the present invention is to provide a method for manufacturing a semiconductor device that solves the problems of increasing the number of steps when forming an oxide film for gate sidewalls and damaging the 81 substrate.
（問題点を解決するための手段）
この発明は、半導体装置の製造方法において、ゲート電
極としてポリシリコン、金属シリサイド層、金属層の３
層を順次堆積してこのホ゛リシリコン層が金属シリサイ
ド層と金属層に対してサイドエツチングを施してイオン
を注入する工程を導入したものである。(Means for Solving the Problems) The present invention provides a method for manufacturing a semiconductor device in which three layers of polysilicon, a metal silicide layer, and a metal layer are used as a gate electrode.
This method introduces a process in which layers are sequentially deposited, the polysilicon layer is side-etched to the metal silicide layer and the metal layer, and ions are implanted.
（作 ｍ）
この発明によれば、半導体装置の製造方法において以上
のような工程を導入したので、３層構造のゲート電極の
最下層のポリシリコン層を最上層の金属層に対してアン
ダカットしてイオン注入し、したがって、前記問題点を
除去できる。(Production m) According to the present invention, since the above steps are introduced in the method for manufacturing a semiconductor device, the lowermost polysilicon layer of the three-layered gate electrode is undercut with respect to the uppermost metal layer. ion implantation, thus eliminating the above-mentioned problems.
（実施例）
以下、この発明の半導体装置の製造方法の実施例につい
て図面に基づき説明する。第１図（ａ）ないし第１図（
ｅ）はその一実施例の工程説明図である。(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figure 1(a) to Figure 1(
e) is a process explanatory diagram of one example.
この第１図（ａ）ないし第１図（ｅ）において、第２図
（ａ）ないし第２図（２））と同一部分に同一符号を付
して説明する。In FIG. 1(a) to FIG. 1(e), the same parts as in FIG. 2(a) to FIG. 2(2)) are given the same reference numerals and will be explained.
まず、第１図（ＩＬ）に示すように、半導体基板として
Ｐ型のＳｌ基板１を酸素雰囲気中で１００１酸化し素子
分離用酸化膜２とゲート酸化膜３を形成した後、ポリシ
リコン４をｘＳｏｏＡｃｖＤ法により堆積し、リン拡散
を行い次に同時スパッタ法によりシリコンとモリブデン
の二つのスパッタ源からシリコンとモリブデンの組成比
が約１ ： ２．５になるように蒸着し、さらに、同じ
スパッタ蒸着装置内で、モリブデンのみを１ｏｏｏ〜２
０００λ蒸着して、金属シリサイド層１１と金属層１２
を形成する。かくして、ゲート電極となる部分は最下層
のポリシリコン４と中間層の金属シリサイド層１１と最
上層の金属層１２との３層構造となる。First, as shown in FIG. 1 (IL), a P-type Sl substrate 1 as a semiconductor substrate is 1001 oxidized in an oxygen atmosphere to form an element isolation oxide film 2 and a gate oxide film 3, and then polysilicon 4 is formed. xSooAcvD method, phosphorus diffusion is performed, and then simultaneous sputtering is performed from two sputtering sources of silicon and molybdenum so that the composition ratio of silicon and molybdenum is approximately 1:2.5, and then the same sputter deposition is performed. Inside the device, only molybdenum is 1ooo~2
000λ vapor deposition to form a metal silicide layer 11 and a metal layer 12.
form. Thus, the portion that will become the gate electrode has a three-layer structure including the polysilicon layer 4 as the bottom layer, the metal silicide layer 11 as the intermediate layer, and the metal layer 12 as the top layer.
この後、ホトリソ工程により第１図（ｂ）に示すように
、レジストパターン５を形成し、第１図（Ｃ）に示すよ
うに、四塩化炭素（ＣＣ４）と６弗化硫砿（ＳＦ６ ）
ガスの混合ガスにより０．２ ｔｏｒｒ 、 ２５０Ｗ
でエツチングを行う。After that, a resist pattern 5 is formed by a photolithography process as shown in FIG. 1(b), and carbon tetrachloride (CC4) and sulfur hexafluoride (SF6) are used as shown in FIG. 1(C).
0.2 torr, 250W due to gas mixture
Perform etching with.
このとき、ポリシリコン４のエツチング速度がモリブデ
ン膜（金属シリサイド層１１）のそれより速いため、エ
ツチング後は、ポリシリコン４が金属シリサイド層１１
よりも横方向にエツチングされた（アンダカットのある
）状態となる。At this time, since the etching speed of polysilicon 4 is faster than that of the molybdenum film (metal silicide layer 11), polysilicon 4 is etched into metal silicide layer 11 after etching.
The result is a more horizontally etched state (with an undercut).
この後に、第１図（ｄ）に示すように、砒素のイオン９
の注入を行うと、金属シリサイド層１１は、蒸着後は柱
状の結晶であり、砒素イオンは一部この層を通りＳｌ基
板１に到達するので、アンダカット部分の直下は、打ち
込み不純物量が少ないｎ一層７が形成できるとともに、
Ｓｌ基板１中にはｎ＋層１０が形成され、ソース争ドレ
イン層となる。After this, as shown in FIG. 1(d), arsenic ion 9
When implantation is performed, the metal silicide layer 11 is a columnar crystal after vapor deposition, and some of the arsenic ions pass through this layer and reach the Sl substrate 1, so the amount of implanted impurities is small directly under the undercut part. While n single layer 7 can be formed,
An n+ layer 10 is formed in the Sl substrate 1 and serves as a source and drain layer.
（発明の効果）
以上詳細に説明したようにこの発明によれば、ゲート電
極部分をポリシリコン、シリコンと金属の混合した金属
シリサイド層、金属層の３層構造とし、ホトリソ・エツ
チングを行い、金属層に対しポリシリコンの層がアンダ
カットした状態にした後、イオン注入を行うことにより
、金ＭＮの結晶性を利用してイオンが金属層を通過し、
その直下のＳｔ基板上に濃度の薄い拡散層を形成し、Ｌ
ＤＤ構造としたので、ゲート電極部の側壁を形成する際
の工程を省略でき、この工程の除虫じるＳＬ基板へのプ
ラズマによる損傷を回避できる。(Effects of the Invention) As described above in detail, according to the present invention, the gate electrode portion has a three-layer structure of polysilicon, a metal silicide layer containing a mixture of silicon and metal, and a metal layer, and is etched by photolithography and etching. After the polysilicon layer is undercut with respect to the layer, by performing ion implantation, the ions pass through the metal layer using the crystallinity of gold MN.
A lightly concentrated diffusion layer is formed on the St substrate immediately below the L
Since the DD structure is adopted, the step of forming the side walls of the gate electrode portion can be omitted, and damage caused by plasma to the SL substrate during this step can be avoided.
さらに、この発明による構造を配線部分に用いると、金
属を用いたことによる抵抗値の減少により回路の高速化
にも寄与できる。Furthermore, when the structure according to the present invention is used in the wiring portion, the resistance value can be reduced due to the use of metal, which can contribute to increasing the speed of the circuit.
第１図（＆）ないし第１図（ｅ）はこの発明の半導体装
置の製造方法の一実施例の工程説明図、第２図（ａ）な
いし第２図（ロ）は従来の半導体装置の製造方法の工程
説明図である。
１・・・Ｓｔ基板、２・・・素子分離用酸化膜、３・・
・ゲート酸化膜、４・・・ポリシリコン、５・・・レジ
スト、９・・・イオン注入、７・・・ｎ一層、１０・・
・ｎ＋層、１１・・・金層シリサイド層、１２・・・金
属層。
（ｒ
二〜←し刊１ト飲直の製造わムｎ月１
第１ 図
す
（＋＠図
イ疋求Ｏ−Ｆ傳イ参老（置ｅ
第
製ｉｔ方法丙工希呈説明図
２図FIGS. 1(&) to 1(e) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device of the present invention, and FIGS. It is a process explanatory diagram of a manufacturing method. 1... St substrate, 2... Oxide film for element isolation, 3...
・Gate oxide film, 4...Polysilicon, 5...Resist, 9...Ion implantation, 7...N single layer, 10...
- n+ layer, 11...gold layer silicide layer, 12...metal layer. (r 2 ~ ← 1 publication 1 to drink fresh production time n month 1 1st figure (+ @ figure ← request O-F den ii sanro (place e) figure
Claims (1)
ンと金属シリサイド層と金属層の３層構造を形成する工
程と、 （ｂ）上記ポリシリコンが上記金属シリサイド層と金属
層に対してサイドエッチングを施す工程と、（ｃ）上記
半導体基板にイオンの注入を行う工程と、よりなる半導
体装置の製造方法。[Claims] (a) A step of forming a three-layer structure of polysilicon, a metal silicide layer, and a metal layer on a semiconductor substrate via a gate oxide film, and (b) forming the polysilicon layer with the metal silicide layer. A method for manufacturing a semiconductor device, comprising the steps of: performing side etching on a metal layer; and (c) implanting ions into the semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16743685A JPS6229168A (en) | 1985-07-31 | 1985-07-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16743685A JPS6229168A (en) | 1985-07-31 | 1985-07-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6229168A true JPS6229168A (en) | 1987-02-07 |
Family
ID=15849670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16743685A Pending JPS6229168A (en) | 1985-07-31 | 1985-07-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6229168A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521454A (en) * | 1991-07-11 | 1993-01-29 | Nec Yamagata Ltd | Manufacture of semiconductor device |
| JPH0529337A (en) * | 1991-07-25 | 1993-02-05 | Nec Yamagata Ltd | Semiconductor device |
| KR100540477B1 (en) * | 1998-06-30 | 2006-03-17 | 주식회사 하이닉스반도체 | Gate electrode formation method of semiconductor device |
-
1985
- 1985-07-31 JP JP16743685A patent/JPS6229168A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0521454A (en) * | 1991-07-11 | 1993-01-29 | Nec Yamagata Ltd | Manufacture of semiconductor device |
| JPH0529337A (en) * | 1991-07-25 | 1993-02-05 | Nec Yamagata Ltd | Semiconductor device |
| KR100540477B1 (en) * | 1998-06-30 | 2006-03-17 | 주식회사 하이닉스반도체 | Gate electrode formation method of semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5283455A (en) | Thin film field effect element having an LDD structure | |
| JPH03173480A (en) | Manufacture of semiconductor device having multilayer conduction line lying on board | |
| US5682052A (en) | Method for forming isolated intra-polycrystalline silicon structure | |
| US6271064B2 (en) | Thin film transistor and method of manufacturing the same | |
| KR20020047230A (en) | Method of manufacturing a semiconductor memory device with anti-reflective coating | |
| JPS6229168A (en) | Manufacture of semiconductor device | |
| JPH06349856A (en) | Thin-film transistor and its manufacture | |
| JPH04116846A (en) | Semiconductor device and its manufacture | |
| JPS63207177A (en) | Manufacture of semiconductor device | |
| JPH05198796A (en) | Semiconductor device and manufacture thereof | |
| JPS5923476B2 (en) | Manufacturing method of semiconductor device | |
| JPH0640549B2 (en) | Method for manufacturing MOS semiconductor device | |
| JPH01272161A (en) | Manufacture of mos type fet | |
| JPH03227024A (en) | Manufacture of semiconductor device | |
| JPH0231468A (en) | Manufacture of floating gate type semiconductor memory device | |
| KR100338090B1 (en) | Method for manufacturing semiconductor device | |
| JPH04146627A (en) | Field-effect type semiconductor device and manufacture thereof | |
| JPH01260857A (en) | Semiconductor device and manufacture thereof | |
| JPS6154661A (en) | Manufacture of semiconductor device | |
| JPH07226502A (en) | Mos transistor and manufacture thereof | |
| JPH08222736A (en) | Method of manufacturing mos transistor | |
| KR100198630B1 (en) | Structure of thin film transistor and making method of the same | |
| JPH0298173A (en) | Manufacture of semiconductor memory | |
| JPS62206873A (en) | Manufacture of semiconductor device | |
| JPH0629541A (en) | Manufacture of semiconductor device |