JPH04116846A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To prevent the occurrence of a parasitic transistor by providing an ion implanted area on the side face of the active layer of a semiconductor by continuous rotation oblique ion implantation. CONSTITUTION:A resist is applied to a semiconductor layer 2 on an insulating substrate l. Then, after making island-like patterning on the semiconductor layer 2, a P<+> area 21 is formed by implanting boron into the layer 2 by rotating the substrate l while the substrate l is inclined by 45 deg.. After the resist 3 is removed, an oxide film 4 is formed by oxidizing the surface of the semiconductor layer 2 and a gate electrode 6 is formed on the oxide film 4. Therefore, the occurrence of a parasitic transistor can be suppressed through simple processes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device formed in the shape of an insulating film and a method for manufacturing the same.

[Conventional technology]

In order to improve the performance of semiconductor devices, attempts have been made to separate circuit elements with dielectrics and manufacture semiconductor integrated circuits with less stray capacitance, and even more so-called integrated semiconductor devices in which circuit elements are stacked three-dimensionally in multiple layers. Attempts have been made to fabricate three-dimensional circuit elements.

FIG. 3 is a vertical cross-sectional view of a conventional semiconductor device formed on an insulating film. The oxide film of 200 people, 111 is the boron concentration I x 10 ''/ad.

A channel region made of single crystal silicon with a thickness of 1000 μm, 112 a source/drain diffusion region made of crystal with an arsenic concentration of I x 10 ”/al, and 103 with a thickness of 8000 μm
The electrode wiring 104 made of Af is a polycrystalline silicon gate electrode heavily doped with phosphorus. As described above, the NMo5 transistor was formed on the insulating film 101.

FIG. 4 shows the electrical characteristics of a conventional semiconductor device.

Conventional semiconductor devices use a mesa isolation structure.

This is because when stacking transistors to form a three-dimensional circuit element, the LOGO8 separation method, which requires a long heat treatment, cannot be applied.

[Problem to be solved by the invention]

The conventional method for manufacturing a semiconductor device is configured as described above, and a parasitic transistor is formed on the side wall of the active layer 112. Furthermore, since the sidewalls of the active layer 112 have a crystal plane different from the main surface, they have a different threshold voltage than the transistor formed on the main surface. As a result, as shown in FIG. 4, kinks occur in the subthreshold region, which adversely affects the characteristics of the device. Furthermore, the mesa isolation structure has the problem that the gate oxide film near the edges of the active layer 112 becomes thinner, and the gate breakdown voltage decreases due to effects such as concentration of an electric field on the edges.

In order to avoid the influence of the parasitic transistor, a method as shown in US Pat. No. 4,753,896 has been proposed.

To explain using the manufacturing process diagram in FIG. 5, as shown in FIG. 5(a), an oxide film 16 is deposited on the semiconductor 14 on the interlayer insulator 12 on the semiconductor substrate 10, and The silicon nitride film 18 (hereinafter referred to as nitride film) and the oxide film 2o are debossed, and the nitride film 1 is deposited using the resist 22 as a mask.
8 and the oxide film 16°20 are patterned. Next, the figure (
As shown in b), a resist 26 is provided, and boron ions are implanted into the portion indicated by the semiconductor layer 14' on the insulating film 12. Thereafter, as shown in step (C), after removing the oxide film 2o, the nitride film 18. A side wall 28 made of an oxide film is formed on the side surface of the oxide film 16 to form a transistor field 32 as shown in Figure Cd) to be described later. After that, the semiconductor layer 14' is patterned as shown in FIG.
Create 0. and nitride film 18. Oxide film 15. After sidewall 28 is removed, Mo3) is applied using a normal MOS process.
Form a run sister.

With the above configuration, the sidewall 30 prevents electric field concentration at the edge of the semiconductor active region 14, and the ion implantation layer 14' suppresses the generation of parasitic transistors, but this process flow requires a large number of steps. In addition, the CVD method was used to form the sidewall 28.30mm.
It has the disadvantage that it is not suitable for producing tertiary elements because it requires high-temperature heat treatment on the order of °C.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can eliminate the generation of parasitic transistors with a simple manufacturing flow.

Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can prevent electric field concentration at field edges and eliminate the generation of parasitic transistors.

[Means to solve the problem]

A method of manufacturing a semiconductor device according to the present invention is such that an ion implantation region is provided on a side surface of a semiconductor active layer using continuous rotation oblique ion implantation.

Further, the semiconductor layer is tapered to have a substantially trapezoidal cross section and patterned into an island shape, and an ion implantation region is provided on the side surface of the tapered portion using continuous rotation oblique ion implantation.

[Effect]

In this invention, since continuously rotating ions are implanted into the edge of the active layer of the semiconductor, the generation of parasitic transistors can be suppressed through a simple manufacturing process. Furthermore, by patterning the semiconductor active layer in a tapered manner, electric field concentration at the edges can be suppressed.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a cross-sectional view showing each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. In the figure, 1 is an insulating substrate;
2 is a silicon semiconductor film, 3 is a resist, 4 is an oxide film, 6
is the gate electrode.

Next, the manufacturing method will be explained.

As shown in Figure (a), a resist 3 is applied to the semiconductor layer 2 on the insulating substrate 1.

Next, as shown in Figure (b), the semiconductor layer 2 is patterned in a high position, and while the insulating substrate 1 is rotated at an angle of 45 degrees, boron (B1
) is implanted to form a P+ region 21.

As shown in FIG. 3C, after removing the resist 3, the surface of the semiconductor layer 2 is oxidized to form an oxide film 4 of about 200 layers, and a gate electrode 6 is formed thereon.

After that, follow the normal MOS process flow.
Fabricate an S transistor.

In this example, since ions were implanted into the semiconductor layer 2 at an angle of 45 degrees, the P9 region 21 can be easily formed on the side wall of the active layer 2 without heat treatment, and the generation of parasitic transistors can be controlled. .

FIG. 2 is a sectional view showing the manufacturing process of a semiconductor device according to another embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and 5 is a P+ region.

First, as shown in Figure (a), a resist 3 is applied to the semiconductor 2 on the insulating substrate 1 in the same manner as in the above embodiment.

Next, as shown in Figure (b), the resist 3 is left and the underlying semiconductor layer 2 is patterned. At this time, the semiconductor layer 2
Pattern with a taper at a 30 degree angle.

Next, tilt the substrate 1 at 45 degrees and rotate it to a voltage of 50 KeV.
Then, boron of 1 x 10 '3/aIr is implanted to form a P+ region 5 on the side wall of the tapered semiconductor layer 2.

Then, as shown in FIG. 3C, after removing the resist 3, an oxide film 4 with a thickness of about 200 layers is formed on the surface of the semiconductor layer 2, and a gate electrode 6 is further formed.

After that, follow the normal MOS process flow to complete the MOS
Fabricate a transistor.

As described above, in this embodiment, the angle of the edge portion between the semiconductor layer 2 and the substrate 1 is set to 150 degrees, and the ions are implanted into the semiconductor layer 2 at an angle of 45 degrees, so that electric field concentration can be reduced with a simple structure. Furthermore, since the P1 region is formed on the side wall of the semiconductor layer while avoiding high-temperature treatment, the generation of parasitic transistors can be suppressed without impairing device characteristics.

It has been reported that if oxidation is performed at a temperature of about 900 degrees, the oxide film thickness at the edge becomes extremely thin, but when fabricated using this process flow, the gate oxide film 4 is formed at the above temperature. Even if it is formed, the oxide film thickness will not become thinner,
A decrease in gate breakdown voltage can be avoided.

Although the above example shows an example of manufacturing NMOS, PMO3 can also be manufactured using the same method by performing diagonal continuous rotational ion implantation of impurities of the opposite conductivity type.
Furthermore, NMOS and PMOS transistors can also be manufactured on the same substrate.

It can also be applied to three-dimensional circuit elements that are laminated in large numbers.

Further, in the above embodiment, a MOS (MOS) transistor was shown as an example, but similar effects can be obtained even when applied to isolation of other elements.

〔Effect of the invention〕

As described above, according to the method for manufacturing a semiconductor device according to the present invention, since the continuous rotation oblique ion implantation technique is used, the generation of parasitic transistors can be suppressed with a simple process, and the semiconductor device layer on the insulating film can be suppressed. Since the patterning is performed with a taper so that the cross section is approximately trapezoidal, electric field concentration at the edge of the substrate and semiconductor layer is eliminated, making it possible to obtain a highly reliable semiconductor device with good device characteristics. effective.

[Brief explanation of the drawing]

1 is a step-by-step sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a step-by-step sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the invention, and FIG.
The figure is a cross-sectional view of a conventional semiconductor device, FIG. 4 is a diagram for explaining the electrical characteristics (ID-VG characteristics) of a conventional semiconductor device, and FIG. 5 is a diagram showing a method of manufacturing another conventional semiconductor device. It is a sectional view according to process. 1 is an insulating substrate, 2 is a silicon semiconductor film, 3 is a resist,
4 is an oxide film, 21 is a P1 silicon region, and 6 is a gate electrode wiring. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

[Claims] (1) In a method of manufacturing a semiconductor device in which a circuit element is formed in a semiconductor layer on an insulator, when patterning the semiconductor layer into an island shape, the semiconductor layer is patterned with a taper so that the cross section thereof is approximately trapezoidal. 1. A method of manufacturing a semiconductor device, comprising: a step of implanting an electrically active impurity obliquely into a side wall of a semiconductor layer by continuous rotational ion implantation. (2) A semiconductor device in which a circuit element is formed on a semiconductor layer on an insulator, wherein the semiconductor layer has a substantially trapezoidal cross section with tapered portions on both sides thereof. (3) In the step of patterning the semiconductor layer with a taper so that its cross section is approximately trapezoidal, the taper angle is set at 30°.
2. A method for manufacturing a semiconductor device according to claim 1, characterized in that the method comprises: (4) A method for manufacturing a semiconductor device in which a circuit element is formed in a semiconductor layer on an insulator, which includes a step of patterning the semiconductor layer into an island shape, and performing electrical activation by diagonally continuous rotational ion implantation into the sidewall of the semiconductor layer. 1. A method of manufacturing a semiconductor device, comprising the step of implanting impurities.