JPH04146627A - Field-effect type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To easily conduct etching on a second semiconductor film without requiring a specific etchant by a method wherein a buffer film is formed after a lower layer of first semiconductor film, which becomes a gate electrode, and an upper layer of second semiconductor film, which becomes a gate electrode, are formed on the buffer layer. CONSTITUTION:A first insulating film 101, an N-type polysilicon film 104 are successively formed on a P-type silicon single crystal semiconductor substrate 100. Then, a polysilicon pattern 104A is formed by etching the polysilicon film 104. Subsequently, the first semiconductor film 102 is exposed by conducting wet etching. Then, an N-type polysilicon film 10 and a silicon film 109 are deposited. Subsequently, spacers 109A and 109B are left by conducting anisotropic dry etching. Polysilicon films 102 and 110 are etched, and polysilicon patterns 102A and 110A are formed. Then, using the polysilicon pattern 104A and the spacers 109A and 109B as a mask, arsenic ions are implanted into the P-type silicon single crystal semiconductor substrate 100, and a high density N-type semiconductor regions 107A and 107B are formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a field-effect semiconductor device and a method for manufacturing the same, and in particular to improving the performance and high performance of a semiconductor device constituted by field-effect transistors for integrated circuits. This relates to a manufacturing method suitable for reliability.

[Conventional technology]

In integrated circuits composed of field-effect transistors, the miniaturization of component elements has progressed significantly, and the minimum processing size has decreased to 1.
It has reached the so-called sub-micron region. One of the factors hindering this miniaturization is problems related to reliability, such as hot carrier effects, and many improvements have been made to device structures and manufacturing methods. Among them, G is a device and its manufacturing method that can reduce the electric field strength near the drain and increase the power supply voltage as a result.

LD (Gate-Drain 0verlapped
LDD) [Co-translation, et al.] 9987 International Electron Device Meeting Technical Digest of Papers pp. 38-41 (I
ZAWA etal, International
Electron Device Meeting T
mechanical Digest of Papers
I) p, 38-41.1987). This GOLD structure field effect semiconductor device and its manufacturing method will be explained based on FIG. 2.

Figures 2 (a) to (d) show GOLD in integrated circuit devices.
FIG. 3 is a cross-sectional view illustrating a method of manufacturing a field-effect transistor portion of the structure.

First, as shown in FIG. 2fa), a gate oxide film 201 is formed on a P-type silicon single crystal semiconductor substrate 200. Thin lower polysilicon film 202. Thick upper layer polysilicon film 20
A resist pattern 208 is formed by a photolithography process in a region where a gate is to be formed of a multilayer film in which a silicon oxide film 206 and a silicon oxide film 206 are sequentially formed. Here, a thin polysilicon film 20
2 and the thick polysilicon film 204 have a thickness of 0.5 to 1.
A natural oxide film (not shown) with a thickness of 0 nm is formed.

Then, as shown in FIG. 2 fb), after forming an oxide film pattern 206A using the resist pattern 208 as a mask, dry etching with high selectivity to the oxide film is performed using the oxide film pattern 206A as a mask. Then, the thick upper polysilicon film 204 is etched. At this time, the natural oxide film on the surface of the thin lower polysilicon film 202 acts as an etching stop, and the thick upper polysilicon film 204 is isotropically etched to form a wiring-shaped polysilicon pattern 204A. . Next, using the oxide film pattern 206A and the polysilicon pattern 204A as a mask, phosphorous ions are implanted to form N-type semiconductor regions 205A and 205B that will become a source and a drain in the P-type silicon single crystal substrate 200.

Next, as shown in FIG. 2(C), the oxide film pattern 2
Oxide films 209A and 209B are left on the side surfaces of 06A and polysilicon pattern 204A. Here, the thin polysilicon film 202 is etched using these oxide films 209A and 209B as a mask to form a polysilicon pattern 202A which will essentially become a gate electrode.

Finally, as shown in FIG. 2(dl), using the remaining oxide films 209A and 209B as a mask, a part of the source and a drain are implanted into the P-type silicon single crystal semiconductor substrate 200 by ion implantation of highly concentrated arsenic. N-type semiconductor regions 207A and 207B, which will become part of the semiconductor layer, are formed.

A field effect transistor with a GOLD structure made by such a process has a polysilicon pattern 20 for a gate electrode.
2A, the N-type semiconductor region 205A at the drain end
, 205B or sufficiently overlapped (0,2
(more than microns), and this overlap has the following characteristics.

(1) Since the electric field applied near the drain is smaller than that of a field effect transistor (single drain) formed by a conventional method, generation of hot carriers is suppressed and reliability is high.

(2) The resistance of the overlap part is LDD (Light
Because it is smaller than a field effect transistor with a doped drain structure, it has superior driving power.

[Problem to be solved by the invention]

The conventional method shown in FIG. 2 has the following problems.

(1) Since an extremely thin natural oxide film is used as an etching stopper, a special etchant with a high selectivity (several hundred times) relative to the oxide film is required to etch the polysilicon film 204. be.

(2) Currently, etching with a selectivity several hundred times greater than that of an oxide film tends to become isotropic, causing thinning of the upper polysilicon pattern 204A.

(3) The thinning of the upper polysilicon pattern 204A causes an overhang of the oxide film pattern 206A, which deteriorates the coverage shape of the oxide films 209A and 209B left on the side surfaces of the polysilicon pattern 204A. , 209B is used as an etching mask for the lower polysilicon pattern 202A that will become the gate electrode, which tends to cause variations in gate width.

The purpose of the present invention is to eliminate the need for a special etchant, eliminate thinning of the conductive film serving as the gate electrode, and eliminate variations in gate width in the manufacture of field effect semiconductor devices with such a gate-drain overlap (GOLD) structure. It is an object of the present invention to provide a field-effect semiconductor device and a method for manufacturing the same, which can suppress the phenomenon.

[Means to solve the problem]

The field effect semiconductor device of the present invention is a field effect semiconductor device having a GOLD structure in which a gate and a drain overlap. a first insulating film for a gate; a flat first semiconductor film provided with a predetermined width on the surface of the first insulating film to serve as a gate electrode; The first
a second semiconductor film with a rectangular cross section that is narrower and thicker than the semiconductor film of the first semiconductor film and serves as a gate electrode; A hat-shaped third semiconductor film provided in contact with the outer surface of the film and serving as a gate electrode, and a second insulating film for a spacer provided on the upper surface of the peripheral edge of the third semiconductor film. There is.

Further, in the method for manufacturing a field effect semiconductor device of the present invention, a first insulating film for a gate is deposited on the semiconductor layer of the first conductivity type, and then a first insulating film for the gate is deposited on the semiconductor layer of the first conductivity type. A first semiconductor film that will become a gate electrode is deposited, and impurities of a second conductivity type are introduced simultaneously with the deposition. Next, a buffer film is formed on the first semiconductor film that has become the second conductivity type, and then a second semiconductor film that does not contain impurities is formed thicker than the first semiconductor film on the buffer film. A second conductivity type impurity is introduced into a second semiconductor film that does not contain impurities.

Using the buffer film as an etching stopper, the second semiconductor film is etched in the shape of a wiring to form a gate electrode, and then the buffer film is etched using the second semiconductor film in the shape of a wiring as a mask to form the first. expose the semiconductor film.

Next, by ion implantation using the wiring-shaped second semiconductor film as a mask, impurities of the second conductivity type are transmitted through the first semiconductor film and implanted into the semiconductor layer of the first conductivity type to form the source and A first semiconductor region of a second conductivity type is formed to serve as a drain.

Then, a third semiconductor film is uniformly deposited on the wiring-shaped second semiconductor film and the first semiconductor film to be thinner than the second semiconductor film, and at the same time as the deposition, a second conductivity type impurity is introduced. The upper surface of the first semiconductor film and the side surface of the second semiconductor film are connected via a third semiconductor film.

Next, a second insulating film is left on the side surface of the gate electrode formed by the second and third semiconductor films, and the remaining second insulating film and the wiring-shaped second semiconductor film are used as an etching mask. , etching the first and third semiconductor films into a wiring shape.

Then, by ion implantation using the remaining second insulating film and the wiring-shaped second semiconductor film as a mask, impurities of the second conductivity type are implanted into the semiconductor layer of the first conductivity type to partially form the source. and a second semiconductor region of the second conductivity type that becomes a part of the dowel.

[For production]

According to this invention, the following effects were obtained.

(1) Since the thickness of the buffer film can be made sufficiently large, the upper second semiconductor film can be easily etched without the need for a special etchant, and the second semiconductor film after etching can be easily etched. The cross-sectional shape of can be defined with high precision.

(2) Even if a thick buffer layer is interposed between the second semiconductor film in the upper layer and the first semiconductor film in the lower layer, and direct electrical connection cannot be obtained between the two, the second semiconductor film in the upper layer Electrical connection between the semiconductor film and the underlying first semiconductor film can be easily obtained via the third semiconductor film.

(3) Since the thickness of the buffer film can be made sufficiently large, the upper second semiconductor film can be etched even by anisotropic dry etching with poor etching selectivity. Therefore, it is possible to obtain a gate electrode with a good coverage shape and a low electrical resistance without narrowing of the pattern of the semiconductor film serving as the gate electrode.

(4) Normally] When impurities are introduced into a thin semiconductor film of 00 nm or less by ion implantation, the implanted impurities may reach the gate insulating film and cause gate breakdown, or reach the channel region and increase leakage current. . Also, POC
Even with a method of introducing impurities at high temperature using a gas such as Il3, if the semiconductor film is thin, grains will grow large and the etching will not be uniform, causing defects. Also, as in the case of ion implantation, excess phosphorus reaches the channel region and increases leakage current. In the method according to the present invention, when depositing the thin first and third semiconductor films, impurities are introduced at the same time as the deposition, so gate destruction and leakage current increase due to impurities do not occur, and excessive grain growth is less likely to occur. .

(5) If a conductor film is used as a buffer film, the resistance of the gate electrode can be reduced.

〔Example〕

FIGS. 1A to 1D are a series of process cross-sectional views showing a method for manufacturing a field effect semiconductor device according to an embodiment of the present invention.

First, as shown in FIG. 1(a), a gate oxide film with a thickness of 10 to 20 nm is formed on a P-type silicon single crystal semiconductor substrate 100 (corresponding to a semiconductor layer of the first conductivity type in the claims). (corresponds to the first insulating film in the claims) 101, 50 to 11 which becomes the first semiconductor film
N-type polysilicon film 102 with a thickness of 00n. Silicon oxide film 103 with a thickness of lO~20 nm serving as a buffer film
．． A polysilicon film 104 having a thickness of 300 to 350 nm, which will become a second semiconductor film, is successively formed. In particular, the N-type polysilicon film 102 is deposited by, for example, a CVD method using S s H4 gas, and PH3 gas is added thereto to make it N-type at the same time as the deposition.

After this, the polysilicon film 104 is exposed to POCIl at a high temperature.

Phosphorus is introduced from the gas to make it N-type.

Next, as shown in FIG. 1(b), a resist pattern (not shown) is formed in the area where the gate electrode is to be formed by a normal photolithography process, the polysilicon film 104 is etched, and the upper layer of the gate electrode is etched. Polysilicon pattern 10
Form 4A. Here, a fluorine-based gas such as SF is used as the etching gas, and the silicon oxide film 103 functions as an etching stopper. Next, the silicon oxide film 103 is selectively etched by wet etching to form an oxide film pattern, and the first semiconductor film 10
Expose 2.

Next, a polysilicon pattern 104 that will become a gate electrode is formed.
Phosphorus ions are implanted into the P-type silicon single crystal semiconductor substrate 100 by ion implantation using A as a mask to form low concentration N-type semiconductor regions 105A and 1 that will become the source and drain.
Form 05B.

Next, as shown in FIG. 1(C), an N-type polysilicon film 110, which is a third conductive film, is made to have a thickness of 50 to 1100 nm using the same method as the N-type polysilicon film 102. A silicon oxide film 109, which is a second insulating film, is deposited.
is deposited to a thickness of 200-300 nm. Next, the silicon oxide film 109 is etched by anisotropic dry etching to leave spacers 109A and 109B made of silicon oxide films on the side walls of the gate electrode.

Next, as shown in FIG. 1(d), the spacer 109
A resist pattern (not shown) is formed from A to the spacer 109B, and the polysilicon films 102 and 110 are etched using this resist pattern and the spacers 109A and 109B as masks to form polysilicon patterns 102A and 110 that will become the lower layer gate electrodes. form. Next, polysilicon pattern 1 that will become the gate electrode
Arsenic ions are implanted into the P-type silicon single crystal semiconductor substrate 100 using impurity ions using the spacers 109A and 109B on its side walls as masks to form a high concentration of N that will become part of the source and part of the drain. Type semiconductor regions 107A and 107B are formed.

In the field effect transistor having the LDD structure obtained by this manufacturing method, the gate and drain overlap, and a device with high reliability and high driving power can be obtained.

The structural features of the field effect semiconductor device manufactured by this method are as follows.

(1) Since the thick buffer film 103 is used as an etching stopper, it is easy to form the gate electrode by etching the upper layer polysilicon film 104, and the width of the lower layer gate electrode, which affects transistor characteristics, is
Since the thickness of the third insulating film is determined, the variation is small.

(2) When impurities are introduced by ion implantation into a thin semiconductor film, which is usually less than 1100 nm thick, the implanted impurities may reach the gate insulating film and cause gate breakdown, or reach the channel region and increase leakage current. There is. Also,
Even with a method of introducing impurities at high temperature using a gas such as POCl, if the semiconductor film is thin, grains will grow and etching will not be uniform, resulting in defects. Further, as in the case of ion implantation, excessive phosphorus reaches the channel region, increasing leakage current. However, in the method according to the present invention, when a thin semiconductor film is deposited, impurities are introduced at the same time as the deposition, so gate destruction and leakage current increase due to impurities do not occur, and excessive grain growth is less likely to occur.

〔Effect of the invention〕

According to the field effect semiconductor device and the manufacturing method thereof of the present invention, a buffer film is formed after forming a lower first semiconductor film which becomes a gate electrode, and a second upper semiconductor film which becomes a gate electrode is formed on the buffer film. Since a semiconductor film is formed, the buffer film has a sufficient function as an etching stopper when etching the second semiconductor film, and the semiconductor film can be easily etched without the need for a special etchant. can. Furthermore, it is possible to etch the second semiconductor film without thinning, and it is possible to improve the coverage of the second insulating film provided as a spacer on both sides of the etched second semiconductor film. 2 semiconductor film and the second semiconductor film left on both sides thereof.
Since the first conductor, which will become the underlying gate electrode, is etched using the insulating film as a mask, variations in gate radius can be reduced.

In particular, according to the manufacturing method, since impurities are simultaneously introduced when depositing the thin first and third semiconductor films, a field effect transistor with low leakage current can be obtained. Since this field-effect transistor suppresses the generation of hot carriers, there is no need to lower the power supply voltage even in integrated circuits with a minimum line width of 0.5 microns or less, and a high drive current can be obtained, making it highly suitable for miniaturization. It is something that contributes.

[Brief explanation of drawings]

FIG. 1 is a series of process cross-sectional views showing a method for manufacturing a field-effect semiconductor device according to an embodiment of the present invention, and FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a field-effect semiconductor device. . 100...P-type silicon single crystal semiconductor substrate, 101°103, 106...Silicon oxide film, 106A,
109A, 109B... Oxide film pattern, 102
, 104, 110... polysilicon film, 102A,
104A, 104B, ll0A...Polysilicon pattern, 105A, 105B, 107A, 1
07B...N-type semiconductor area patent applicant Matsushita Electric Industrial Co., Ltd. 101.103,106...Shirifu/Tohi job 106A
109A 109B...” Princess Senfu pattern 102
．． 104, 110 - polysilicon film 102A, l04
A, 104B, + IOA''・-Polysilicon pattern 105A, + 058. + 07A, 107B-
・N type 1 flight diagram (a Gatekeeper (b (C (d 05B +05A

Claims (2)

[Claims] (1) GOL with overlapping gate and drain
A field-effect semiconductor device having a D structure, comprising: a semiconductor layer having a semiconductor region serving as a source and a drain; a first insulating film for a gate provided on a surface of the semiconductor layer; a flat first semiconductor film that is provided with a predetermined width on the surface and serves as a gate electrode; and a buffer film that is narrower and thicker than the first semiconductor film with a buffer film disposed above the center of the first semiconductor film. a second semiconductor film with a rectangular cross section that serves as a gate electrode; A field-effect semiconductor device comprising: a third semiconductor film having a hat shape and serving as a gate electrode; and a second insulating film for a spacer provided on the upper surface of a peripheral portion of the third semiconductor film. (2) forming a first insulating film for a gate on a semiconductor layer of a first conductivity type; depositing a first semiconductor film to become a gate electrode on the first insulating film for a gate; a step of introducing an impurity of a second conductivity type at the same time as the deposition; a step of forming a buffer film on the first semiconductor film which has become a second conductivity type; and a step of introducing an impurity onto the buffer film. forming a second semiconductor film that does not contain the impurity to be thicker than the first semiconductor film; introducing a second conductivity type impurity into the second semiconductor film that does not contain the impurity; and using the buffer film as an etching stopper. etching the second semiconductor film in the shape of a wiring to form a gate electrode; and etching the buffer film using the second semiconductor film in the shape of the wiring as a mask to form the first semiconductor film. and ion implantation using the wiring-shaped second semiconductor film as a mask, allowing impurities of the second conductivity type to pass through the first semiconductor film and into the semiconductor layer of the first conductivity type. a step of implanting a first semiconductor region of a second conductivity type to become a source and a drain; and a step of implanting a third semiconductor uniformly over the second semiconductor film having the wiring shape and the first semiconductor film. A film is deposited thinner than the second semiconductor film, a second conductivity type impurity is introduced at the same time as the deposition, and the upper surface of the first semiconductor film and the side surface of the second semiconductor film are formed into a third semiconductor film. a step of connecting via a film; a step of leaving a second insulating film on a side surface of the gate electrode formed by the second and third semiconductor films; and connecting the left second insulating film and the wiring. etching the first and third semiconductor films into a wiring shape using the shaped second semiconductor film as an etching mask; etching the remaining second insulating film and the wiring shaped second semiconductor film; A second conductivity type impurity is implanted into the first conductivity type semiconductor layer by ion implantation using a mask as a mask to form a second conductivity type second semiconductor region which becomes a part of the source and a part of the drain. A method of manufacturing a field effect semiconductor device, comprising a step of forming a field effect semiconductor device.