JPH04294585A - Manufacture of vertical type mos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a semiconductor device by which the channel length is easily controlled and which has a short distance between a source or drain area below a gate electrode and a channel formed on the side face of a silicon pillar and a gate electrode which can be easily connected with wiring. CONSTITUTION:This manufacturing method of a vertical type MOS semiconductor device forms a gate electrode 9 by filling up a groove formed between a silicon pillar 5 and an insulator 7 surrounding the pillar 5 with a gate material after a source area 3 or drain area 10 is formed below the gate electrode 9.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical MOS semiconductor device having a channel perpendicular to the surface of a silicon substrate.

0002

2. Description of the Related Art MOS type semiconductor integrated circuits currently in practical use use planar MOS type semiconductors having channels in the horizontal direction with respect to the semiconductor surface. In order to improve the degree of integration of integrated circuits, it is necessary to reduce the area occupied by the elements, but in order to reduce the area occupied by planar MOS semiconductors, it is necessary to shorten the channel length or narrow the channel width. There is. However, it is difficult to effectively reduce the occupied area by reducing the channel length and channel width because many problems occur, such as short channel effects, deterioration due to hot carriers, and a decrease in current drive capability.

On the other hand, MOS formed on a thin film SOI substrate, etc.
It has been found that device characteristics are improved by completely depleting the substrate portion of a type semiconductor device, and research is being conducted on such fully depleted devices. Research is also underway to improve controllability of drain current using a two-gate device having two gate electrodes sandwiching a channel region.

[0004] Various methods have been attempted to realize such small-occupying-area devices, fully depleted devices, and two-gate devices. There is a method using a vertical MOS semiconductor device having the following characteristics. That is, by forming the channel in a direction perpendicular to the surface of the silicon substrate, the occupied area can be reduced without shortening the channel length or reducing the channel width. Further, a gate electrode can be easily formed around the channel region, and by making the channel region into a sufficiently thin columnar shape, the substrate portion can be completely depleted. Furthermore, a two-gate device can be easily realized by forming gate electrodes along two opposing sides of a columnar channel region.

As a specific example of a method for manufacturing a vertical MOS semiconductor device, as shown in FIG. 11(a), boron ions are implanted into the surface of a silicon substrate 1 to form a p-type impurity layer 2 at a depth of 6 μm. After forming, RIE is performed as shown in FIG. 11(b).
The p-type impurity layer 2 is partially removed using a method to form a silicon pillar 5 having a height of 1 μm and a width of 0.5 μm, and then it is heated to a thickness of 200 Å by thermal oxidation as shown in FIG. 11(c). A gate oxide film 7 of 0 is formed on it, as shown in FIG.
．． Polycrystalline silicon 8 is deposited to a thickness of 6 μm and etched back using a sidewall technique, leaving polycrystalline silicon 8 with a thickness of 0.3 μm in the horizontal direction as shown in FIG. 11(e) to form the gate electrode. 9, and as shown in FIG. 11(f), arsenic ions were implanted using the gate electrode 9 as a mask, and the thickness was 0.3μ.
A drain region 10 and source region 3 are formed at a depth of m to form a vertical MOS semiconductor device. In this case, the drain region 10 and the source region 3 may be replaced.

In this structure, a channel is formed on the side surface of the silicon pillar 5 facing the gate electrode 9 with the gate oxide film 7 in between, and the channel is perpendicular to the surface of the silicon substrate 1.

[0007]

Problems to be Solved by the Invention As shown in FIG. 11(f), the drain region 10 and the source region 3
It is formed by ion implantation using a mask as shown in FIG.
It is difficult to control the shape of the gate electrode 9 by etching back using the sidewall technique in (e), and the horizontal thickness decreases in the upper part of the gate electrode 9, so the depth of the drain region 10 varies. occurs, and as a result, it becomes difficult to control the channel length. Further, when the thickness of the gate electrode 9 is relatively large, the distance between the source region 3 located under the gate electrode 9 and the channel formed on the side surface of the silicon pillar 5 becomes large, and current controllability deteriorates. . On the other hand, if the thickness of the gate electrode 9 is relatively small, it becomes difficult to connect other wiring to the gate electrode 9.

An object of the present invention is to provide a vertical structure having a gate electrode in which the channel length is easy to control, the distance between the source region or drain region under the gate electrode and the channel formed on the side surface of the silicon pillar is small, and it is easy to connect wiring. type MOS
A method for manufacturing a semiconductor device is provided.

[0009]

Means for Solving the Problems The object of the present invention is to provide a method for manufacturing a vertical MOS semiconductor device having a channel in a direction perpendicular to the surface of a silicon substrate. forming a source or drain region on a silicon substrate; forming a silicon pillar on the source or drain region; forming an insulator on the surface of the silicon substrate surrounding the silicon pillar; The present invention provides a method for manufacturing a vertical MOS semiconductor device, which comprises a step of embedding a gate electrode in a trench formed by a silicon pillar and an insulator to form a gate electrode.

Another object of the present invention is to provide a method for manufacturing a vertical MOS semiconductor device in which the groove is formed all around the silicon pillar.

Furthermore, the present invention provides a method for manufacturing a vertical MOS semiconductor device, in which the silicon pillar has a rectangular cross section and the trench is formed along two opposing sides of the silicon pillar.

The silicon pillar has a thickness or width such that the inside is completely depleted from the surface channel region when the device is conductive.

[0013]

[Operation] In the method of manufacturing a vertical MOS semiconductor device of the present invention, the gate electrode is formed by burying the gate electrode material in the groove provided between the silicon pillar and the insulator surrounding the silicon pillar, without using the sidewall technique. Because it forms
The shape controllability of the gate electrode is good, the variation in the depth of the drain region is suppressed, and as a result, the channel length can be easily controlled.

Furthermore, since the source or drain region under the gate electrode is formed before forming the gate electrode, the distance between the source or drain region under the gate electrode and the channel formed on the side surface of the silicon pillar can be reduced. . Further, even if the thickness of the gate electrode is increased in the horizontal direction, it does not affect the source region or the drain region under the gate electrode, so that the gate electrode can be made thicker in the horizontal direction to facilitate connecting wiring to the gate electrode.

[0015]

EXAMPLES Examples of the present invention will be described in detail below with reference to the drawings, but the present invention is not limited to the following examples.

As an embodiment of the present invention, a method for manufacturing a vertical MOS semiconductor device is shown in FIGS. 1 to 9, and perspective views of two types of embodiments are shown in FIGS. 10(a) to 10(b). . Note that in FIGS. 1 to 10, the same components as those in the conventional example shown in FIG. 11 are designated by the same reference numerals.

First, as shown in FIG. 1, boron ions are implanted into the surface of a silicon substrate 1 to form a p-type impurity layer 2 to a depth of 2 μm, and then arsenic ions are implanted to a depth of 0.3 μm as shown in FIG. The source region 3 is formed at a depth of . Next, as shown in FIG. 3, a p-type single crystal silicon layer 4 is epitaxially grown to a thickness of 1 μm, and then RIE is performed as shown in FIG.
By using a method, the single crystal silicon layer 4 is partially removed until the source region 3 is exposed, thereby forming a silicon pillar 5 having a height of 1 μm and a width of 0.5 μm.

Next, after depositing a silicon oxide layer 6 to a thickness of 1 μm, as shown in FIG. A groove with a width of .5 μm is provided, and a gate oxide film 7 with a thickness of 200 Å is formed by thermal oxidation as shown in FIG. Next, as shown in FIG. 7, polycrystalline silicon 8 is deposited to a thickness of 0.5 μm to fill the groove, and etched back to deposit polycrystalline silicon 8 at a height of 0.7 μm in the groove as shown in FIG. The silicon 8 is left as a gate electrode 9, and as shown in FIG. 9, arsenic ions are implanted to form a drain region 10 to a depth of about 0.3 μm to form a vertical MOS semiconductor device. In this case, the drain region 10 and the source region 3 may be replaced.

In forming the gate electrode 9 in FIG. 8, the shape controllability of the gate electrode 9 by etchback is good, and the thickness of the gate electrode 9 in the horizontal direction is constant.
The depth of the drain region 10 is stabilized and the channel length can be easily controlled. Furthermore, since the source region 3 is formed before the electrode 9 is formed as shown in FIG. 2, the source region 3 and the silicon pillar 5 are
The channels formed on the sides of the can be brought close to each other,
Deterioration of current controllability is suppressed. In addition, the gate electrode 9
The thickness in the horizontal direction can be arbitrarily determined by changing the width of the groove formed in FIG.

Note that the grooves in FIG. 5 of this embodiment are as shown in FIG. 10 (
They may be formed all around the silicon pillar 5 as shown in a), or may be formed along two opposing sides of the silicon pillar 5 as shown in FIG. 10(b). Figure 10 (a
), the channel is formed around the silicon pillar 5, and if the silicon pillar is thin enough, the depletion layers overlap, resulting in a fully depleted device. In the case of FIG. 10(b), two channels are formed on two opposing sides of the silicon pillar 5, resulting in a two-gate device.

Furthermore, in this embodiment, arsenic ions were implanted only in the vicinity of the silicon pillar 5 in FIG. Wiring may be done. Although the grooves were formed only in the vicinity of the silicon pillars 5 in FIG. 5, grooves were also formed in other parts of the silicon oxide layer 6, and the gate electrodes 9
Wiring using the gate electrode material may be performed simultaneously with the formation of the gate electrode.

Further, in this embodiment, a p-type impurity layer is formed on the surface of the silicon substrate 1 by ion implantation, but a p-type silicon substrate may be used instead without ion implantation. Further, although the method for forming an n-type MOS semiconductor device has been described in this embodiment, a p-type MOS semiconductor device can also be formed in the same manner.

[0023]

According to the method for manufacturing a vertical MOS semiconductor device of the present invention, since the shape controllability of the gate electrode is good, the channel length can be easily controlled, and the distance between the source region or drain region under the gate electrode and the silicon pillar can be easily controlled. Since the distance from the channel formed on the side surface can be reduced, deterioration in current controllability can be suppressed, and since the gate electrode can be made thicker, wiring can be easily connected to the gate electrode.

[Brief explanation of drawings]

FIG. 1 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 2 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 3 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 4 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 5 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 6 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 7 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 8 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 9 is a process explanatory diagram according to an embodiment of the present invention.

FIG. 10 is a perspective view showing an embodiment of the present invention.

FIG. 11 is a process explanatory diagram according to a conventional example.

[Explanation of symbols]

1 Silicon substrate 2 p-type impurity layer 3 Source area 4 p-type single crystal silicon layer 5 Silicon pillar 6 Silicon oxide layer 7 Gate insulating film 8 Polycrystalline silicon 9 Gate electrode 10 Drain region

Claims (4)

[Claims] 1. A method for manufacturing a vertical MOS semiconductor device having a channel in a direction perpendicular to the surface of a silicon substrate, the method comprising: forming a source or drain region in the silicon substrate below the gate electrode before forming a gate electrode; forming a silicon pillar on the source or drain region; forming an insulator on the surface of the silicon substrate surrounding the silicon pillar; 1. A method for manufacturing a vertical MOS semiconductor device, comprising the steps of: burying a gate electrode material in a groove to form a gate electrode. 2. The vertical MO according to claim 1, wherein the groove is formed all around the silicon pillar.
S semiconductor device manufacturing method. 3. The vertical MOS according to claim 1, wherein the silicon pillar has a rectangular cross section, and the groove is formed along two opposing sides of the silicon pillar.
A method for manufacturing a semiconductor device. 4. The vertical type M according to claim 1, wherein the silicon pillar has a thickness or width such that the inside is completely depleted from the surface channel region when the device is conductive.
A method for manufacturing an OS semiconductor device.