JP2001168334A - Power field-effect transistor and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power MOS field-effect transistor equipped with a structure in which a drift region is not situated between a body region and a silicon substrate. SOLUTION: A process in which a p-type silicon layer 12 to be used as the body region is formed on an n+ type drain region formed on the silicon substrate is provided. A process in which a trench 18 extending to the n+ type drain region 10 is formed in the p-type silicon layer 12 is provided. A process in which an n-type silicon layer 22 to be used as the drift region is formed by a solid-phase epitaxial growth operation is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power field effect transistor and a method for manufacturing the same.

[0002]

FIG. 9 is a sectional view of a power MOS field effect transistor disclosed in US Pat. No. 5,216,275. First, the power MOS field effect transistor 3
Description will be made from the structure of 00. The power MOS field effect transistor 300 is a vertical type. The power MOS field effect transistor 300 is formed on a semiconductor substrate. This semiconductor substrate includes an n ⁺ type drain region 304. An n-type semiconductor layer 301 is formed on the drain region 304. The n-type semiconductor layer 301 becomes a drift region. On the drain region 304 so as to sandwich the n-type semiconductor layer 301,
A p-type semiconductor layer 302 is formed. p-type semiconductor layer 3
02 is a body region.

[0003] A p ⁺ -type semiconductor layer 303 is formed on the p-type semiconductor layer 302. The end of p ⁺ type semiconductor layer 303 is located on n type semiconductor layer 301. A gate electrode 309 is formed on the n-type semiconductor layer 301 and on the side wall of the p ⁺ -type semiconductor layer 303 via a gate insulating film 308. An n ⁺ type source region 305 is formed on the surface of the p ⁺ type semiconductor layer 303 with a space therebetween. p ⁺ type semiconductor layer 3
The source electrode 310 is formed on a region of the layer 03 between the source regions 305.

Next, the operation of the power MOS field effect transistor 300 will be described. First, the case where the power MOS field-effect transistor 300 is in the ON state will be described. When a positive voltage is applied to the gate electrode 309, a channel region is formed in a region of the p ⁺ type semiconductor layer 303 facing the gate insulating film 308. The electrons are in the source region 30
5 and the n-type semiconductor layer 301 from the channel region.
And reaches the drain region 304. In this case, the ON voltage of the power MOS field-effect transistor 300 is determined mainly by the voltage drop due to the resistance of the n-type semiconductor layer 301.

Next, the case where the power MOS field-effect transistor 300 is in the OFF state will be described. 0 V or a negative voltage is applied to the gate electrode 309. This eliminates the channel region. Assuming that the drain voltage is, for example, about 10 V, an n-type semiconductor layer portion (the n-type semiconductor layer portion is composed of the drain region 304 and the n-type semiconductor layer 301) and a p-type semiconductor layer portion (the p-type semiconductor layer portion is a depletion layer is formed along the junction constituted by the p-type semiconductor layer 302 and the p ⁺ -type semiconductor layer 303).
And spread. The n-type semiconductor layer 301 and the p-type semiconductor layer 302 have small lateral lengths. Therefore, as the drain voltage increases, the n-type semiconductor layer 301 and the p-type semiconductor layer 302 are all depleted. With this depletion layer, the breakdown voltage of the power MOS field-effect transistor 300 is maintained.

[0006]

The power MOS field-effect transistor 300 has an n-type semiconductor layer 301 between a p-type semiconductor layer 302 and a semiconductor substrate (drain region 304).
Is not located, the n-type semiconductor layer 30
1 is reduced over the entire region, thereby improving the breakdown voltage of the power MOS field-effect transistor.

The power MOS field effect transistor disclosed in US Pat. No. 5,216,275 has the above structure,
The withstand voltage of the power MOS field effect transistor is improved. However, there is a problem how to realize this structure.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a method for manufacturing a power field effect transistor having a structure in which a drift region is not located between a body region and a semiconductor substrate. It is to be.

Another object of the present invention is to provide a power field effect transistor and a method for manufacturing the same, which can reduce the difference in thermal expansion.

[0010]

According to the present invention, there is provided a method of manufacturing a power field effect transistor, comprising: a semiconductor substrate; a first source / drain region of a first conductivity type located on a surface of the semiconductor substrate; And a first conductive type first semiconductor layer serving as a current path, a second conductive type second semiconductor layer positioned on the semiconductor substrate, and a first conductive type positioned on the surface of the second semiconductor layer. A second source / drain region of a mold, a gate electrode located on a second semiconductor layer between the second source / drain region and the first semiconductor layer via a gate insulating layer, and a semiconductor substrate and A method for manufacturing a power field effect transistor having a structure in which a first semiconductor layer is not located between two semiconductor layers, comprising: (a) forming a first source / drain region in a semiconductor substrate; ,
(B) forming a second semiconductor layer on the semiconductor substrate;
(C) forming a trench in the second semiconductor layer reaching the semiconductor substrate; and (d) forming a first semiconductor layer in the trench by solid phase epitaxial growth;
(E) forming a gate insulating layer and a gate electrode on the second semiconductor layer; and (f) forming a second source / drain region on the surface of the second semiconductor layer.

According to the manufacturing method of the present invention including the above steps, the first semiconductor layer is formed in the trench by solid phase epitaxial growth, so that the first semiconductor layer is provided between the semiconductor substrate and the second semiconductor layer. A structure that is not located is realized.

If the depth of the trench is too large, the entire amorphous semiconductor layer embedded in the trench cannot be monocrystallized by solid phase epitaxial growth. Therefore, the depth of the trench is determined in consideration of this. As this depth, for example, the depth of the trench is 4 μm or less. The same applies to the following trenches.

The temperature of the solid phase epitaxial growth is as follows:
500 ° C to 650 ° C is preferred. If it is higher than 650 ° C,
Nucleus growth in the amorphous semiconductor layer is promoted, and a good single crystal cannot be obtained. As a result, the performance of the device deteriorates. The same applies to the following solid phase epitaxial growth temperatures.

Here, as the power field effect transistor, for example, there are a MOS type and a MIS type. The power field effect transistor may be either a vertical type or a horizontal type. The same applies to the meaning of the following power field effect transistors.

Further, the source / drain region means a region functioning only as a source region, a region functioning only as a drain region, or a region functioning as a source region and a drain region. The same applies to the following source / drain regions.

In the method of manufacturing a power field effect transistor according to the present invention, instead of the steps (b) to (d), (g) forming a third semiconductor layer of a first conductivity type on a semiconductor substrate. (H) forming a trench in the third semiconductor layer reaching the semiconductor substrate, (i) forming a second semiconductor layer in the trench by solid phase epitaxial growth, and (j) solid phase. Forming a first semiconductor layer on the second semiconductor layer in the trench by epitaxial growth.

According to this method, since the first and second semiconductor layers are formed by solid phase epitaxial growth, the thickness and the impurity concentration of the first and second semiconductor layers can be controlled accurately.

In the method for manufacturing a power field effect transistor according to the present invention, (k) the thermal expansion of the first semiconductor layer and the second thermal expansion may be formed on the side wall of the trench between the steps (c) and (d). It is preferable to include a step of forming a buffer layer for reducing a difference between the semiconductor layer and the thermal expansion.

According to this method, even if the first and second semiconductor layers are thermally expanded by the heat treatment during the manufacturing process of the power field effect transistor, the first semiconductor layer and the second semiconductor layer are separated by the buffer layer. It is possible to prevent a gap from being generated between them.

In order to achieve this effect, the buffer layer has good adhesion to the first and second semiconductor layers and has a coefficient of thermal expansion of 5 × 10 ⁻⁷ / ° C. to 2.6 × 10 ⁻⁶ /. Materials that are at ° C. are preferred. Specifically, for example, there is a silicon oxide film.

According to a method of manufacturing a power field effect transistor according to the present invention, a semiconductor substrate, a first source / drain region of a first conductivity type located on a surface of the semiconductor substrate, a current path located on the semiconductor substrate, The first of the first conductivity type
A semiconductor layer, a second conductivity type second semiconductor layer located on the semiconductor substrate, a first conductivity type second source / drain region located on the surface of the second semiconductor layer, and a second source / drain A gate electrode located on the second semiconductor layer between the region and the first semiconductor layer via the gate insulating layer, wherein the first semiconductor layer is located between the semiconductor substrate and the second semiconductor layer; A method for manufacturing a power field effect transistor having a structure not performed, comprising: (a) forming a first source / drain region on a semiconductor substrate; and (b) forming a first semiconductor layer on the semiconductor substrate. And (c) forming a first semiconductor layer on the first semiconductor layer;
Forming a trench reaching the semiconductor substrate;
(D) forming the second semiconductor layer in the trench by solid-phase epitaxial growth, and (e) forming a gate insulating layer and a gate electrode on the second semiconductor layer.
(F) forming a second source / drain region on the surface of the second semiconductor layer.

According to the manufacturing method of the present invention including the above steps, the first semiconductor layer is formed between the semiconductor substrate and the second semiconductor layer by forming the second semiconductor layer in the trench by solid phase epitaxial growth. A structure that is not located is realized.

A power field effect transistor according to the present invention is a semiconductor substrate, a first source / drain region of a first conductivity type located on a surface of the semiconductor substrate, and a first source / drain region located on the semiconductor substrate and serving as a current path. A first conductivity type first semiconductor layer, a second conductivity type second semiconductor layer located on the semiconductor substrate, and a first semiconductor layer located between the first semiconductor layer and the second semiconductor layer; A buffer layer that reduces a difference between expansion and thermal expansion of the second semiconductor layer, and a buffer layer that is located on the surface of the second semiconductor layer.
A second source / drain region of a first conductivity type; a gate electrode located on the second semiconductor layer between the second source / drain region and the first semiconductor layer via a gate insulating layer; It has a structure in which the first semiconductor layer is not located between the substrate and the second semiconductor layer.

A power field effect transistor according to the present invention is a power field effect transistor manufactured by a method including the step of forming the buffer layer.

[0025]

[First Embodiment] FIG. 1 (d)
1 is a cross-sectional view of a power field effect transistor manufactured according to a first embodiment of the present invention. This power field effect transistor is a vertical power MOS transistor 1
It is. First, the structure of the power MOS transistor 1 will be described. The power MOS transistor 1 has a gate electrode 2
6, n ⁺ type source regions 28 a and 28 b and an n ⁺ type drain region 10.

The n ⁺ type drain region 10 is formed on a silicon substrate. An n-type silicon layer 22 is located on n ⁺ -type drain region 10. The n-type silicon layer 22 becomes a drift region, that is, a current path. The p-type silicon layers 12a and 12b are located on the n ⁺ -type drain region 10 so as to sandwich the n-type silicon layer 22 therebetween. p
The mold silicon layers 12a and 12b become body regions. The junction 30 is formed by the p-type silicon layer 12a and the n-type silicon layer 22.
a is formed. The junction 30b is formed by the p-type silicon layer 12b and the n-type silicon layer 22. The junctions 30a and 30b extend to the n ⁺ type drain region 10.

Source regions 28a and 28b are located on the surfaces of the p-type silicon layers 12a and 12b, respectively. an n-type silicon layer 22 and a p-type silicon layer 12a,
The gate electrode 2 is formed on the gate electrode 12b via a gate oxide layer 24.
6 is located. A portion of the p-type silicon layer 12a between the n ⁺ -type source region 28a and the n-type silicon layer 22 under the gate electrode 26 is a channel forming region 32a.
Becomes n ⁺ type source region 28b and n type silicon layer 22
And the vicinity of the p-type silicon layer 12b below the gate electrode 26 is a channel formation region 32b.

Next, the operation of the power MOS transistor 1 will be described. First, the power MOS transistor 1 is turned on
The description starts from the state. When a positive voltage is applied to the gate electrode 26, a channel is formed in each of the channel formation regions 32a and 32b. The electrons are supplied from the n ⁺ -type source regions 28 a and 28 b, pass through the channel and the n-type silicon layer 22, and reach the n ⁺ -type drain region 10.

Next, the power MOS transistor 1
The case of the F state will be described. 0 is applied to the gate electrode 26.
V or a negative voltage is applied. As a result, there is no channel region, and no current flows. Since a voltage of about 10 V is applied to the n ⁺ -type drain region 10, the depletion layer is formed near the junctions 30a and 30b from the n-type silicon layer 22.
It spreads to. The n-type silicon layer 22 has a small lateral dimension. Therefore, the n-type silicon layer 22 is completely depleted. With this depletion layer, the power MOS transistor 1
Withstand pressure. Note that power MOS transistors according to other embodiments of the invention described later perform the same operation.

Next, a manufacturing method according to the first embodiment of the present invention will be described with reference to FIG. Note that the concentration and thickness of the epitaxial layer change depending on the breakdown voltage of the device. In the first embodiment, the device withstand voltage is 100 V to 250 V.
It is an explanation for the case of.

As shown in FIG. 1A, a silicon substrate including an n ⁺ type drain region 10 is prepared. The concentration of the drain region 10 is 5 × 10 ¹⁸ / cm ³ to 2 × 10 ¹⁹ / cm ³
It is.

A p-type silicon layer 12 is formed on the drain region 10 by, for example, solid phase epitaxial growth. p
The concentration of the silicon layer 12 is 5 × 10 ¹⁴ / cm ³ -1 ×
A 10 ^{1 6} / cm ^3. The thickness of the p-type silicon layer 12 is
It is 15 μm or less.

A mask layer 14 is formed on the p-type silicon layer 12 by using thermal oxidation or CVD. The mask layer 14 is made of a silicon oxide layer.

The mask layer 14 is patterned by photolithography and etching. This allows
An opening 16 is formed in the mask layer 14. An n-type silicon layer serving as a drift region is formed below opening 16.

Using the mask layer 14 as a mask, the p-type silicon layer 12 is selectively etched to form a trench 18 below the opening 16. The trench 18 is formed in the drain region 10
Has been reached. The depth d of the trench 18 is 15 μm or less, and the width w is 2 μm or less. Drain region 1
Of the zeros, the part exposed by the trench 18 becomes the seed crystal part 20. The seed crystal part 20 becomes a seed crystal at the time of solid phase epitaxial growth described later. The p-type silicon layer 12 is separated into the p-type silicon layer 12a and the p-type silicon layer 12b by this etching.

As shown in FIG. 1B, the thickness is 1 to 2 μm.
Is formed so that the trench 18 is filled. Examples of the n-type impurity include phosphorus. As a method for forming the amorphous n-type silicon layer 22, for example, there is a CVD method.

Using the seed crystal portion 20 as a seed crystal, the amorphous n-type silicon layer 22 is monocrystallized by solid phase epitaxial growth. The n-type silicon layer 22 in the trench 18 becomes a drift region. The conditions for solid phase epitaxial growth are 550-620 ° C.

As shown in FIG. 1C, the mask layer 14 is removed by etching back the n-type silicon layer 22 and the mask layer 14.

As shown in FIG. 1D, the n-type silicon layer 22 and the p-type silicon layer 12a,
A stacked structure of the gate oxide layer 24 and the gate electrode 26 is formed on 12b. Then, n ⁺ -type source regions 28a and 28b are formed in p-type silicon layers 12a and 12b, respectively, using a known method. Note that the n ⁺ -type source regions 28a and 28b may be formed first, and a stacked body of the gate oxide layer 24 and the gate electrode 26 may be formed later. This also applies to the later embodiments. Through the above steps,
The power MOS transistor 1 is completed.

According to the manufacturing method of the first embodiment of the present invention, the n-type silicon layer 22 is formed by solid phase epitaxial growth, so that the silicon substrate (the n ⁺ -type drain region 10) and the p-type silicon layer The power MOS transistor 1 having a structure in which the n-type silicon layer 22 is not located between the power MOS transistor 1 and 12a is realized.

[Second Embodiment] FIG. 2E is a sectional view of a power field effect transistor manufactured according to a second embodiment of the present invention. This power field effect transistor is a vertical power MOS transistor 3. Of the components of the power MOS transistor 3, the same components as those of the power MOS transistor 1 are denoted by the same reference numerals, and description thereof is omitted.

The structure of the power MOS transistor 3 is shown in FIG.
The difference from the structure of the power MOS transistor 1 shown in (d) is that n-type silicon layers 36a and 36b are formed in part of the formation regions of the p-type silicon layers 12a and 12b, respectively.

The n-type silicon layer 36a and the n-type silicon layer 3
6b, the n-type silicon layer 36
Only the structure of a will be described. n-type silicon layer 36a
Is n ⁺N-type silicon layer located on the drain region 10
22 and the p-type silicon layer 12a.
You. A p-type silicon layer 38a is formed on the n-type silicon layer 36a.
Is located.

Next, a manufacturing method according to a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2A, a silicon substrate including an n ⁺ type drain region 10 is prepared. An n-type silicon layer 36 is formed on the drain region 10 by, for example, solid phase epitaxial growth. The concentration of the n-type silicon layer 36 is 5 × 10 ¹⁴ / cm ³ to 1 × 1
0 ¹⁶ / cm ³ . The thickness of the n-type silicon layer 36 is 1
5 μm or less.

The mask layer 14 is formed on the n-type silicon layer 36 by using thermal oxidation or CVD. The mask layer 14 is made of a silicon oxide layer.

The mask layer 14 is patterned by photolithography and etching. This allows
An opening 16 is formed in the mask layer 14.

Using the mask layer 14 as a mask, the n-type silicon layer 36 is selectively etched to form a trench 18 below the opening 16. The trench 18 is formed in the drain region 10
Has been reached. The depth d of the trench 18 is 15 μm or less, and the width w is 2 μm or less. Drain region 1
Of the zeros, the part exposed by the trench 18 becomes the seed crystal part 20. The seed crystal part 20 becomes a seed crystal at the time of solid phase epitaxial growth described later. The n-type silicon layer 36 is separated into an n-type silicon layer 36a and an n-type silicon layer 36b by this etching.

As shown in FIG. 2B, a p-type silicon layer 12 is formed on the side wall of the trench 18 and on the seed crystal portion 20. The p-type silicon layer 12 is in an amorphous state.
As a method for forming the p-type silicon layer 12, for example, CV
There is the D method.

Using the seed crystal portion 20 as a seed crystal, the amorphous p-type silicon layer 1 is formed by solid phase epitaxial growth.
2 is single crystallized. The conditions for solid phase epitaxial growth are 550-620 ° C.

Next, an n-type silicon layer 2 having a thickness of 2 μm or less
2 and the p-type silicon layer 12 so that the trench 18 is filled.
Form on top. The n-type silicon layer 22 is in an amorphous state. As a method for forming the n-type silicon layer 22, for example,
There is a CVD method.

Using the p-type silicon layer 12 as a seed crystal, the amorphous n-type silicon layer 22 is monocrystallized by solid phase epitaxial growth. The n-type silicon layer 22 in the trench 18 becomes a drift region. The conditions for solid phase epitaxial growth are 550-620 ° C.

As shown in FIG. 2C, the heat treatment of the silicon substrate causes the n ⁺
The impurity is diffused into the p-type silicon layer 12. Thereby, the n ⁺ -type drain region 10 and the n-type silicon layer 22 are brought into contact.

As shown in FIG. 2D, the mask layer 14 is removed by etching back the n-type silicon layer 22 and the mask layer 14.

As shown in FIG. 2E, p-type silicon layers 38a and 38b are formed on the n-type silicon layers 36a and 36b, respectively, using a known method.

Next, the n-type silicon layer 22 and the p-type silicon layers 12a, 12b, 38a,
A laminate of the gate oxide layer 24 and the gate electrode 26 is formed on 38b. Then, n ⁺ -type source regions 28a and 28b are formed in p-type silicon layers 38a and 38b, respectively, using a known method. Through the above steps, the power MOS transistor 3 is completed.

[Third Embodiment] FIG. 3D is a cross-sectional view of a power field effect transistor manufactured according to a third embodiment of the present invention. This power field effect transistor is a vertical power MOS transistor 5. The structure of the power MOS transistor 5 is different from the structure of the power MOS transistor 1 shown in FIG. 1D in that a silicon oxide layer 40a serving as a buffer layer is provided between the p-type silicon layer 12a and the n-type silicon layer 22. The point is that a silicon oxide layer 40b serving as a buffer layer is located between the p-type silicon layer 12b and the n-type silicon layer 22.

The thickness of the silicon oxide layers 40a and 40b is 10 μm or less. This thickness is large enough to cause a tunnel effect. Thereby, at the time of the ON operation of the power MOS transistor 5, the n ⁺ type source regions 28a, 28
Electrons from b pass through the silicon oxide layers 40a and 40b and can reach the n-type silicon layer 22. Power M
When the OS transistor 5 is turned off, the depletion layer can spread in the n-type silicon layer 22.

The other structure of the power MOS transistor 5 is the same as the structure of the power MOS transistor 1, and the description thereof will be omitted by using the same reference numerals.

Next, a manufacturing method according to a third embodiment of the present invention will be described with reference to FIG. 3 and FIG.
The structure shown in FIG. 1A is manufactured by using the same method as the manufacturing method according to the first embodiment of the present invention.

Next, as shown in FIG.
A silicon oxide layer 40 having a thickness of not more than nm is formed on the structure shown in FIG. The silicon oxide layers 40 located on the side walls of the trench 18 are referred to as silicon oxide layers 40a and 40b. As a method for forming the silicon oxide layer 40, for example,
There are CVD and thermal oxidation methods. Then, for example, the silicon oxide layer 40 on the seed crystal part 20 is removed using reactive ion etching.

The thermal expansion coefficients of the silicon oxide layers 40a and 40b are 5 × 10 ⁻⁷ / ° C. to 2.6 × 10 ⁻⁶ / ° C. For this reason, the silicon oxide layers 40a and 40b
During the manufacture of the S transistor 5, the n-type silicon layer 2
2 functions as a buffer layer for reducing the difference between the thermal expansion of the p-type silicon layers 12a and 12b. Thereby, the n-type silicon layer 22 and the p-type silicon layers 12a, 12a
It is possible to prevent the generation of a gap between b and b.

As shown in FIG. 3B, n in the amorphous state
The mold silicon layer 22 is formed so as to fill the trench 18. The conditions for forming the n-type silicon layer 22 are the same as the conditions for forming the n-type silicon layer 22 shown in FIG.

Using the seed crystal portion 20 as a seed crystal, the amorphous n-type silicon layer 2 is formed by solid phase epitaxial growth.
2 is single crystallized. During the solid phase epitaxial growth, since the silicon oxide layers 40a and 40b are present, there is no solid phase epitaxial growth from the p-type silicon layers 12a and 12b, but only from the seed crystal part 20. Therefore, the n-type silicon layer 22 having a single crystal structure with few crystal defects can be obtained. That is, without the silicon oxide layers 40a and 40b, during the solid phase epitaxial growth, the solid phase epitaxial growth also occurs from the p-type silicon layers 12a and 12b, which causes crystal defects. The conditions for solid phase epitaxial growth are 550-620 ° C.

As shown in FIG. 3C, the mask layer 14 is removed by etching back the n-type silicon layer 22 and the mask layer 14.

As shown in FIG. 3D, the n-type silicon layer 22 and the p-type silicon layer 12a,
A stacked structure of the gate oxide layer 24 and the gate electrode 26 is formed on 12b. Then, n ⁺ -type source regions 28a and 28b are formed in p-type silicon layers 12a and 12b, respectively, using a known method. Through the above steps, the power MOS transistor 5 is completed.

[Fourth Embodiment] FIG. 5D is a cross-sectional view of a power field effect transistor manufactured according to a fourth embodiment of the present invention. This power field effect transistor is a vertical power MOS transistor 7. The structure of the power MOS transistor 7 is different from the structure of the power MOS transistor 3 shown in FIG.
40b, 42a, and 42b are provided.

The silicon oxide layers 40a, 40b, 42a,
42b will be described in detail. Silicon oxide layer 40a
Is located between the p-type silicon layer 12a and the n-type silicon layer 22, and the silicon oxide layer 40b is
And the silicon oxide layer 42a is located between the p-type silicon layer 12a and the n-type silicon layer 36a.
And the silicon oxide layer 42b is located between the p-type silicon layer 12b and the n-type silicon layer 36b.

The silicon oxide layers 40a, 40b, 42a,
The thickness of 42b is several nm to several tens nm. This thickness is large enough to cause a tunnel effect. Thus, when the power MOS transistor 7 is turned on, electrons from the n ⁺ -type source regions 28a and 28b can pass through the silicon oxide layers 40a, 40b, 42a and 42b and reach the n + -type silicon layer 22. Further, when the power MOS transistor 7 is turned off, the depletion layer becomes the n-type silicon layer 22.
Can spread inside.

The other structure of the power MOS transistor 7 is the same as the structure of the power MOS transistor 3, and the description thereof will be omitted by using the same reference numerals.

Next, a manufacturing method according to a fourth embodiment of the present invention will be described with reference to FIGS. 2 (a), 4 and 5. FIG. The structure shown in FIG. 2A is manufactured using the same method as the manufacturing method according to the second embodiment of the present invention.

Next, as shown in FIG.
A silicon oxide layer 42 of nm or less is formed on the structure shown in FIG. The silicon oxide layers 42 located on the side walls of the trench 18 are referred to as silicon oxide layers 42a and 42b. As a method for forming the silicon oxide layer 42, for example,
There are CVD and thermal oxidation methods. Then, for example, the silicon oxide layer 42 on the seed crystal part 20 is removed using reactive ion etching.

As shown in FIG. 4 (b), a p-type silicon layer 12 having a thickness of 2 μm or less is formed on silicon oxide layers 42a and 42a.
b and on the seed crystal part 20. The p-type silicon layer 12 on the seed crystal part 20 is replaced with the p-type silicon layer 12.
c. The p-type silicon layer 12 is in an amorphous state. p
As a method of forming the mold silicon layer 12, for example, CVD
There is a law.

Using the seed crystal part 20 as a seed crystal, the amorphous p-type silicon layer 1 is formed by solid phase epitaxial growth.
2 is single crystallized. The conditions for solid phase epitaxial growth are 550-620 ° C. A silicon oxide layer 42a,
42b prevents solid-phase epitaxial growth from the n-type silicon layers 36a and 36b, whereby the p-type silicon layer 12 with few crystal defects can be obtained.

As shown in FIG. 4C, a silicon oxide layer 40 having a thickness of 10 nm or less is formed on the p-type silicon layer 12. The silicon oxide layer 40 extending vertically in the trench 18 is referred to as silicon oxide layers 42a and 42b. As a method for forming the silicon oxide layer 42, for example, there are a CVD method and a thermal oxidation method. Then, the silicon oxide layer 40 on the p-type silicon layer 12c is removed using, for example, reactive ion etching.

As shown in FIG. 5A, an n-type silicon layer 22 having a thickness of 2 μm or less is formed so as to fill the trench 18. As a method for forming the n-type silicon layer 22, for example, there is a CVD method.

Drain region 10 and p-type silicon layer 1
Using 2c as a seed crystal, the amorphous n-type silicon layer 22 is monocrystallized by solid phase epitaxial growth. The n-type silicon layer 22 in the trench 18 becomes a drift region.
The conditions for solid phase epitaxial growth are 550 to 620
° C. The silicon oxide layers 40a and 40b can prevent solid-phase epitaxial growth from the p-type silicon layer 12, and thereby, the n-type silicon layer 22 with few crystal defects can be formed.
Can be obtained.

As shown in FIG. 5B, by heat-treating the silicon substrate, the n ⁺ -type drain region 10
The impurity is diffused into the p-type silicon layer 12c. Thereby, the n ⁺ -type drain region 10 and the n-type silicon layer 22 are brought into contact.

As shown in FIG. 5C, the mask layer 14 is removed by etching back the n-type silicon layer 22, the silicon oxide layer 40, the p-type silicon layer 12, the silicon oxide layer 42 and the mask layer 14. I do.

As shown in FIG. 5D, p-type silicon layers 38a and 38b are formed on the n-type silicon layers 36a and 36b, respectively, using a known method.

Next, the n-type silicon layer 22 and the p-type silicon layers 12a, 12b, 38a,
A laminate of the gate oxide layer 24 and the gate electrode 26 is formed on 38b. Then, n ⁺ -type source regions 28a and 28b are formed in p-type silicon layers 38a and 38b, respectively, using a known method. Through the above steps, the power MOS transistor 7 is completed.

[Fifth Embodiment] FIG. 6C is a sectional view of a power field effect transistor manufactured according to a fifth embodiment of the present invention. This power field effect transistor is a vertical power MOS transistor 9. The structure of the power MOS transistor 9 differs from the structure of the power MOS transistor 1 shown in FIG. 1D in that an SOI substrate is used. Therefore, the silicon oxide layer 44a is located between the silicon substrate (n ⁺ -type drain region 10) and the p-type silicon layer 12a, and is located between the silicon substrate (n ⁺ -type drain region 10) and the p-type silicon layer 12b. The silicon oxide layer 44b is located at the bottom.

The other structure of the power MOS transistor 9 is the same as the structure of the power MOS transistor 1, and the description thereof will be omitted by using the same reference numerals.

Next, a manufacturing method according to a fifth embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 6A, the SOI substrate 46
Prepare The SOI substrate 46 has n ⁺Drain region 1
0, silicon oxide layer 44, p-type silicon
It has a structure in which the concrete layers 12 are sequentially laminated.

As shown in FIG. 6B, a trench 18 exposing the n ⁺ -type drain region 10 is formed by using the same method as in FIG. 1A. After the trench 18 is formed, the remaining silicon oxide layer 44 is replaced with silicon oxide layers 44a and 44b.
And

The subsequent manufacturing steps are shown in FIGS. 1 (b) to 1 (d).
This is the same as the process described above.

According to the manufacturing method of the fifth embodiment of the present invention, since the silicon oxide layers 44a and 44b are provided, the n-type impurity in the n ⁺ -type drain region 10 is removed during the manufacturing process by the p-type silicon layer 12a. , 12b. The same can be said for the manufacturing method according to the sixth embodiment of the present invention described below.

[Sixth Embodiment] FIG. 7 is a sectional view of a power field effect transistor manufactured according to a sixth embodiment of the present invention. This power field effect transistor is a vertical power MOS transistor 2. The difference between the structure of the power MOS transistor 2 and the structure of the power MOS transistor 3 shown in FIG.
That is, a substrate is used. For this reason, the silicon substrate (n ⁺ type drain region 10) and the p-type silicon layer 12a,
The silicon oxide layer 44a is located between the silicon substrate (n ⁺ type drain region 10) and the p-type silicon layer 36a.
A silicon oxide layer 44b is located between the type silicon layer 12b and the n-type silicon layer 36b.

The other structure of the power MOS transistor 2 is the same as the structure of the power MOS transistor 3, and the description thereof will be omitted by using the same reference numerals.

[Seventh Embodiment] In a method for manufacturing a power field effect transistor according to a seventh embodiment of the present invention, an n-type silicon layer serving as a drift region is not formed by solid-phase epitaxial growth, and a body is formed. The point is that the p-type silicon layer serving as a region is formed by solid phase epitaxial growth. This will be described below with reference to FIG.

As shown in FIG. 8A, the drain region 1
On n 0, for example, an n-type silicon layer 22 is formed by solid phase epitaxial growth. A mask layer 48 is formed on the n-type silicon layer 22 by using thermal oxidation, CVD, or the like. The mask layer 48 is made of a silicon oxide layer.

The mask layer 48 is patterned by photolithography and etching. This allows
A predetermined opening is formed in the mask layer 48. A p-type silicon layer serving as a body region is formed below the opening.

Using mask layer 48 as a mask, n-type silicon layer 22 is selectively etched to form trenches 50a,
0b is formed. The trenches 50a and 50b reach the drain region 10. Portions of the drain region 10 exposed by the trenches 50a and 50b become seed crystal portions 54a and 54b. Seed crystal parts 54a, 54
b is a seed crystal at the time of solid phase epitaxial growth described later.

As shown in FIG. 8B, p in the amorphous state
The mold silicon layer 12 is formed so as to fill the trenches 50a and 50b. As the p-type impurity, for example, there is boron. As a method for forming the amorphous p-type silicon layer 12, for example, there is a CVD method.

Using the seed crystal portions 54a and 54b as seed crystals, the amorphous p-type silicon layer 12 is monocrystallized by solid phase epitaxial growth. The conditions for solid phase epitaxial growth are 550-620 ° C.

The subsequent manufacturing steps are shown in FIGS. 1 (c) to 1 (d).
This is the same as the process described above.

[Brief description of the drawings]

FIG. 1 shows a power MO according to a first embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 2 shows a power MO according to a second embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 3 shows a power MO according to a third embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 4 shows a power MO according to a fourth embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 5 shows a power MO according to a fourth embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 6 is a diagram illustrating a power MO according to a fifth embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 7 is a cross-sectional view of a power field effect transistor manufactured according to a sixth embodiment of the present invention.

FIG. 8 shows a power MO according to a seventh embodiment of the present invention.
FIG. 9 is a process chart for describing the method for manufacturing the S transistor.

FIG. 9 is a sectional view of a power MOS transistor disclosed in US Pat. No. 5,216,275.

[Explanation of symbols]

1, 2, 3, 5, 7, 9 Power MOS transistor 10 n ⁺ -type drain region 12a, 12b p-type silicon layer 14 mask layer 16 opening 18 trench 20 seed crystal part 22 n-type silicon layer 24 gate oxide layer 26 gate Electrodes 28a, 28b n ⁺ type source regions 30a, 30b Junction portions 32a, 32b Channel formation regions 36a, 36b n type silicon layers 38a, 38b p type silicon layers 40a, 40b silicon oxide layers 42a, 42b silicon oxide layers 44 silicon oxide layers 46 SOI substrate 48 Mask layer 50a, 50b Trench 52a, 52b Opening 54a, 54b Seed crystal part

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Tsutomu Uesugi 41-41, Yokomichi, Nagakute-cho, Aichi-gun, Aichi Prefecture

Claims (5)

[Claims] A first conductive type first source / drain region located on a surface of the semiconductor substrate; a first conductive type first source / drain region located on the semiconductor substrate and serving as a current path; A semiconductor layer; a second conductive type second semiconductor layer located on the semiconductor substrate; and a first conductive type second semiconductor layer located on the surface of the second semiconductor layer.
A source / drain region; and a gate electrode located on the second semiconductor layer between the second source / drain region and the first semiconductor layer via a gate insulating layer. A method for manufacturing a power field effect transistor, wherein the first semiconductor layer is not located between the first semiconductor layer and the second semiconductor layer, wherein (a) the first source / drain region is formed in the semiconductor substrate. Forming; (b) forming the second semiconductor layer on the semiconductor substrate; (c) forming a trench in the second semiconductor layer that reaches the semiconductor substrate; and (d). Forming the first semiconductor layer in the trench by solid phase epitaxial growth; (e) forming the gate insulating layer and the gate electrode on the second semiconductor layer; Power production method of the field effect transistor having a step of forming a second source / drain region in a surface of the second semiconductor layer. 2. The method according to claim 1, wherein, instead of the steps (b) to (d), (g) forming a third semiconductor layer of a first conductivity type on the semiconductor substrate; Forming a trench in the third semiconductor layer to reach the semiconductor substrate; (i) forming the second semiconductor layer in the trench by solid phase epitaxial growth; and (j) solid phase epitaxial growth. Forming the first semiconductor layer on the second semiconductor layer in the trench, thereby producing a power field effect transistor. 3. The method according to claim 1, wherein, between the step (c) and the step (d), (k) a thermal expansion of the first semiconductor layer and a thermal expansion of the second semiconductor layer on sidewalls of the trench. A method for manufacturing a power field effect transistor, comprising a step of forming a buffer layer for reducing a difference from thermal expansion. 4. A semiconductor substrate, a first source / drain region of a first conductivity type located on a surface of the semiconductor substrate, and a first source / drain region of a first conductivity type located on the semiconductor substrate and serving as a current path. A semiconductor layer; a second conductive type second semiconductor layer located on the semiconductor substrate; and a first conductive type second semiconductor layer located on the surface of the second semiconductor layer.
A source / drain region; and a gate electrode located on the second semiconductor layer between the second source / drain region and the first semiconductor layer via a gate insulating layer. A method for manufacturing a power field effect transistor having a structure in which the first semiconductor layer is not located between the first semiconductor layer and a second semiconductor layer, wherein (a) forming the first source / drain region in a semiconductor substrate (B) forming the first semiconductor layer on the semiconductor substrate; (c) forming a trench in the first semiconductor layer that reaches the semiconductor substrate; Forming the second semiconductor layer in the trench by phase epitaxial growth; (e) forming the gate insulating layer and the gate electrode on the second semiconductor layer; and (f) forming the second semiconductor layer. Method of manufacturing a power field effect transistor having a step of forming a second source / drain regions on the surface of the conductor layer. 5. A semiconductor substrate, a first conductivity type first source / drain region located on a surface of the semiconductor substrate, and a first conductivity type first source / drain region located on the semiconductor substrate and serving as a current path. A semiconductor layer, a second semiconductor layer of a second conductivity type located on the semiconductor substrate, located between the first semiconductor layer and the second semiconductor layer,
A buffer layer for reducing a difference between a thermal expansion of the first semiconductor layer and a thermal expansion of the second semiconductor layer; and a second conductive type second layer located on a surface of the second semiconductor layer.
A source / drain region; and a gate electrode located on the second semiconductor layer between the second source / drain region and the first semiconductor layer via a gate insulating layer. A power field effect transistor having a structure in which the first semiconductor layer is not located between the transistor and a second semiconductor layer.