JP2713940B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a complementary MOS transistor which does not have a latch-up problem and is therefore suitable for high integration.

[Conventional technology]

In a conventional complementary MOS transistor (hereinafter, referred to as CMOS), a structure aimed at improving the latch characteristic by a parasitic bipolar effect is disclosed in, for example, IEE International Electron Devices Meeting 15.2 (1985). Years pp. 403-406 (IE
EE International Electron Devices Meeting 15.2 (19
85) as discussed in pp. 403-406 and having the structure shown in FIG. 2 (a). In the figure, 100 is an n-type S
The i-substrate 200 is a p-type well diffusion region, and has a P + buried region 181 formed by high-energy ion implantation below. N + source diffusion layer 11, N + drain diffusion layer 12, gate electrode 8, and P + ground power supply Vss diffusion layer in P-type well 200
N-channel MOS transistor consisting of 15 (referred to as NMOS)
Is configured. In the N-type well 101, a P + drain diffusion layer 13, a P + source diffusion layer 14, an N + power supply Vcc diffusion layer 18
A P-channel MOS transistor (referred to as a PMOS) composed of 0 and a gate electrode 81 is configured. Gate electrodes 8 and 81
Are connected and act as inputs for the inverter. N
+ Drain diffusion layer 12 and P + drain diffusion layer 13 are metal electrodes
Connected by 22 and works as inverter output. Second
FIG. 2B is an equivalent circuit diagram corresponding to the sectional view of FIG.

[Problems to be solved by the invention]

In the above prior art, the P + buried layer 181 is formed by high-energy ion implantation, or an epitaxial wafer is used as the Si substrate 1 to suppress the occurrence of the latch-up phenomenon due to the parasitic bipolar effect. In order to suppress the parasitic bipolar effect, the current amplification factor of the parasitic transistor may be reduced by lowering the resistance in the lower part of the well region serving as the current path of the parasitic element. However, in the formation of a high-concentration P + diffusion layer by the high-energy ion implantation method, there is a problem that crystal defects generated during ion implantation cannot be eliminated under ordinary heat treatment conditions, and a low-resistance buried layer cannot be realized. In the case of forming an epitaxial layer on the N-type well, the resistance of the well bottom can be reduced by the Sb diffusion layer. However, there is a problem that the epitaxial process is unsuitable for mass processing and is expensive.

An object of the present invention is to form a low-resistance layer at the bottom of a well region with good controllability and low cost without the problem of crystal defects. Another object of the present invention is to completely insulate the well region from the semiconductor substrate and completely eliminate the latch-up phenomenon.

[Means for solving the problem]

In order to achieve the above object, in the present invention, a vertical shaft is formed in the well potential supply region in a direction perpendicular to the main surface, and a horizontal shaft parallel to the main surface is formed by anisotropic etching depending on the crystal plane orientation from the bottom of the vertical shaft. Form a pit. In order to determine the end point of the shaft, the well region is surrounded by the deep groove insulating film. The vertical shaft and the horizontal shaft are filled with an impurity-added semiconductor film. To insulate the well region from the substrate, an insulating film may be formed at least on the bottom of the shaft. In order to form a horizontal shaft parallel to the semiconductor main surface, the (111) main surface is used and the horizontal shaft direction is set to <11.
Set in the <110> direction perpendicular to 1>. If N ₂ H ₄ or K ₀ H is used for anisotropic etching, the <111> direction and SiO
The progress of the etching of the _two films and the Si ₃ N ₄ film can be ignored. Since As, P or the like can be used as the impurity added to the filling semiconductor film, the resistance can be reduced to 1/3 or less as compared with the conventional Sb buried layer below the epitaxial layer.

[Action]

According to the present invention, a buried layer can be formed at the bottom of the well region after forming an NMOS, a PMOS, etc. in the semiconductor main surface region, so that the buried expansion layer is not subjected to an extra heat treatment, and is therefore rapid and highly doped. A buried layer having a concentration distribution can be realized. Further, since the matching is determined in the deep groove insulating film region that defines the buried layer region well region, there is no problem in controllability. The buried layer depth (thickness) depends only on the control of the amount of shaft etching, and the impurity concentration is independent of the above thickness.
A desired low resistance value can be set accurately. Therefore, since the well potential is fixed at the power supply voltage, a parasitic transistor path does not occur, and the occurrence of a latch is suppressed even when the well interval is set to 3 μm or less.

In the present invention, in the case of a structure in which an insulating film is provided below the buried semiconductor layer, the well is completely isolated from the semiconductor substrate and the adjacent well, so that the occurrence of the latch is completely eliminated regardless of the well interval. Therefore, miniaturization and high integration of CMOS are realized.

〔Example〕

Hereinafter, the present invention will be described in more detail with reference to Examples. For convenience of explanation, the explanation will be made with reference to the drawings. In addition, for simplicity of description, the material of each part, the conductivity type of the semiconductor layer, and the manufacturing conditions are defined and described, but the material, the conductivity type of the semiconductor layer, and the manufacturing conditions are not limited thereto. Needless to say.

Embodiment 1 FIGS. 3 to 5 are cross-sectional views showing a first embodiment of a semiconductor device according to the present invention in the order of manufacturing steps.

In FIG. 3, the acceleration energy is 125 KeV and the implantation amount is 1.5 × 10 ¹³ cm through a 30 nm thick SiO ₂ film in a desired region of a Si substrate 1 having a P conductivity type, a resistivity of 10 Ω · cm, and a main surface of (111). P ions were selectively implanted under the condition of ^-2 , and an N ^- type well region 2 having a surface concentration of 7 × 10 ¹⁶ cm ^-3 and a junction depth of about 2.5 μm was formed by a subsequent heat treatment. Thereafter, the formation of a 20 nm thick silicon oxide film (denoted as SiO ₂ ) 300 by thermal oxidation and the formation of a silicon nitride film (denoted as a Si ₃ N ₄ film) 4 by a 120 nm thick chemical vapor reaction (denoted as COD) The patterning was performed. In the above patterning, the Si substrate 1 was also 3 μm deep (width 1
μm) to form a deep groove. Subsequently, ion implantation of BF _{2 is performed on} the bottom of the deep groove under the conditions of an acceleration energy of 60 KeV and a dose of 3.5 × 10 ¹³ cm ⁻² , and after the activation heat treatment, the Si ₃ N ₄ film 4 is used as an oxidation prevention mask to form a deep groove surface. 0.3μm thick S by wet thermal oxidation
An iO ₂ film 6 was formed. Thereafter, a 0.5 μm-thick polycrystalline (or amorphous) Si thin film 7 is deposited on the entire surface by CVD, and the Si thin film 7 on the main surface filling the deep groove voids is removed by microwave etching. It was selectively left in the deep groove space. Next, after removing a desired portion of the Si ₃ N ₄ film 4 by patterning again, ion implantation and activation heat treatment are performed under the same conditions as the above-described deep groove portion ion implantation, and then 0.5 μm by wet thermal oxidation is performed.
A μm-thick field insulating film 5 was formed (FIG. 3).

After removing the Si ₃ N ₄ film 4 and the SiO ₂ film 300 from the state shown in FIG. 3, the exposed Si substrate 1 is 18 nm thick in accordance with a normal CMOS manufacturing process.
Thick gate SiO ₂ film 3, polycrystalline Si film gate electrode 8 and
81, gate protection insulating film 9, gate side wall insulating film 10, N + source diffusion layer 11 and N + drain diffusion layer 12 by As ion implantation, and P + drain diffusion layer 13, P + source diffusion layer 14 by B ion implantation and P + ground potential The supply diffusion layer 15 was formed. A so-called LDD structure or the like in which N ⁻ and P ⁻ diffusion layers are also provided in the drain diffusion layer of the CMOS may be used. Next, a Si ₃ N ₆ film 16 having a thickness of 12 nm was deposited on the entire surface, and then the Si ₃ N ₆ film 16 was selectively removed on the well potential supply scheduled area, and a shaft (2 μm deep) was formed on the Si substrate 1.
From this state, a 20 μm thick SiO ₂ film 17 is formed on the side wall of the shaft by thermal oxidation using the Si ₃ N ₄ film 16 as an oxidation preventing film, and then the bottom of the shaft is dug further to a depth of 0.5 μm, and the side wall of the shaft is removed. In Si
The surface was exposed. Next, an etching solution obtained by mixing 80% hydrazine hydrate (N ₂ H ₄ ), isopropate, and 1% Triton X (trade name: surfactant) at a ratio of 200: 20: 1 was heated to 60 ° C. By processing for about 2 hours, a shaft having a depth of about 5 μm reaching the deep groove insulating film 6 was formed. In the above processing, etching did not proceed in the <111> direction, and a horizontal shaft parallel to the main surface was formed in the entire region surrounded by the deep groove insulating film 6.
The above-mentioned etching does not need to be performed by hydrazine, but may be based on an etching solution such as an aqueous solution of potassium hydroxide (KOH) whose etching speed strongly depends on the crystal plane orientation, or a gas phase etching method (FIG. 4). .

From the state shown in FIG. ₄ , a polycrystalline (or amorphous) Si film 18 to which P was added at a high concentration was deposited to a thickness of 1 μm by introducing pH ₃ in a low-pressure pyrolysis method of SiN ₄ , and a horizontal shaft and a vertical shaft were formed. The well was filled. Thereafter, the polycrystalline Si film 18 on the main surface was removed by micro liquid dry etching, and was selectively left only in the horizontal shaft and the vertical shaft. The layer resistance of the polycrystalline Si film 18 at a thickness of 0.5 μm was 25Ω / □. Next, after forming a shallow N + diffusion layer 19 by heat treatment, the Si ₃ N ₄ film 16 was removed. Thereafter, in accordance with the normal CMOS manufacturing process sequence, the ground voltage line 21, the output electrode 22, and the power supply voltage are deposited by depositing the surface stabilizing film 20 and opening holes at desired locations, depositing and patterning a metal film mainly composed of Al. The wiring including the line 23 and the electrode were formed. Although not shown, the gate electrodes 8 and 81 are connected by the above-mentioned metal wiring and form an input line (FIG. 5).

Through the above-described manufacturing process, the semiconductor device of this embodiment
A MOS transistor is manufactured. According to this embodiment, the well region 2 is completely separated from the Si substrate 1 by the deep trench insulating film 6 and the high impurity concentration polycrystalline Si film 18, and the polycrystalline Si
The layer resistance of the film 18 was as low as 25 Ω / □, and the entire well region 2 could be fixed at the power supply potential. Ie adjacent NM
Even though there is only an isolation region between the OS and the deep trench insulating film 6 having a width of 1 μm, the ratchet-up phenomenon did not occur quickly. The above shows that the separation interval can be improved by three times or more as compared with the conventional structure, in which the separation region interval is required to be 3 to 5 μm or more for suppressing the latch-up phenomenon.

The layer resistance value of the buried polycrystalline Si film 18 according to the present embodiment is reduced to about で with the same layer thickness as that of the Sb buried diffusion layer below the epitaxial layer of the conventional device. In this embodiment, an example in which the polycrystalline Si film 18 is formed by a low-pressure pyrolysis method of monosilane (SiH ₄ ) has been described, but the above description is based on disilane (Si ₂ H ₆ ), dichlorosilane (SiH ₂ Cl ₂ ), or trichloro. Other raw materials such as silane may be used, and the added impurities may be based on As or the like without being limited to P.

Embodiment 2 FIGS. 6 to 7 and FIG. 1 are sectional views showing another embodiment of the present invention in the order of manufacturing steps. In the first embodiment, the shaft initially formed had a depth of 2 μm, but in the present embodiment, it was set to 1.8 μm. Shaft shaft S
After the second vertical shaft formation after the formation of the iO ₂ film 17 was performed at a depth of 0.4 μm, the Si ₃ N ₄ film 271 was deposited again to a thickness of 5 nm, and then, in a direction perpendicular to the main surface by reactive ion etching. Then, the Si ₃ N ₄ film 241 was selectively left on the side wall of the shaft.
Subsequently, the bottom of the shaft was 0.4μ by microwave etching.
According to the first embodiment, a horizontal shaft reaching the deep trench insulating film 6 from the bottom of the vertical shaft after etching by m depths was formed over the entire lower region of the well region 2. Next, high-pressure thermal oxidation is applied to the exposed bottom of the shaft and the ceiling, and a 50 nm thick SiO ₂ film 2
Polycrystalline Si film 181 to which As is added after forming 4 and 25
Was filled by 0.5 μm to fill the shaft. At this stage, since the polycrystalline Si film is also filled in the shaft, the polycrystalline Si film in the shaft was removed by microwave ion etching until the entire surface of the Si ₃ N ₄ film 271 was exposed (FIG. 6). .

From the state shown in FIG. 6, the exposed surface of the polycrystalline Si film 181 is oxidized using the Si ₃ N ₄ film 271 on the shaft wall as an oxidation mask to form a thin SiO ₂ film. Thereafter, the Si ₃ N ₄ film 271 on the side wall of the shaft was removed,
After exposing the Si surface in a part of the side wall of the vertical shaft, the horizontal shaft was formed again by the method shown in the first embodiment using the SiO ₂ films 25 and 26 as an etching mask (FIG. 7).

By removing the exposed SiO ₂ film 25 from the state of FIG. 7 to expose the polycrystalline Si film 181 and then depositing the polycrystalline Si film 18 to which As is added again to a thickness of 1 μm, And the inside of the shaft was completely filled. Then, the polycrystalline on the main surface
The Si film 18 was removed by microwave etching and selectively left only in the horizontal shaft and the vertical shaft, and then the Si ₃ N ₄ film 27 was also removed.
Subsequent manufacturing steps were performed according to the first embodiment (FIG. 1).

The semiconductor device and the CMOS transistor of this embodiment are manufactured by the above manufacturing steps. According to this embodiment, the N-type well 2 is completely insulated from the Si substrate 1 by the SiO ₂ films 24 and 6, and a latch-up phenomenon occurs. The parasitic transistor is completely extinguished. That is, the latch-up phenomenon does not occur regardless of the distance between adjacent transistors. Further, since the well potential is fixed to the entire surface of the well region 2 by providing the buried polycrystalline Si film 18 having a low resistance, the influence of a small number of carriers generated by the high voltage operation is suppressed, so that the threshold voltage changes and the transistor deteriorates. Was also reduced.

In this embodiment, the buried polycrystalline Si film 18 is
Although an example of formation at the bottom is shown, in a CMOS using a P-type well, a P + -type buried polycrystalline layer or a polycrystalline semiconductor layer to which an impurity is not added as required may be formed at the bottom of the P-type well.

〔The invention's effect〕

According to the present invention, the side surface of the well region can be isolated from the Si substrate by the insulating film, the bottom surface can be isolated from the Si substrate by the low-resistance buried layer, and furthermore, the insulating film can completely eliminate the latch-up phenomenon. That is, in the conventional CMOS, a gap of 3 to 5 μm was required between wells or between elements in order to suppress a latch-up phenomenon. However, according to the present invention, the minimum dimension required for forming an element isolation insulating film is reduced to 1 μm or less. Can be set. Accordingly, the miniaturization of the complementary MOS transistor is remarkably advanced.

Further, according to the present invention, the well potential can be uniformly maintained over the entire well region by the low-resistance buried layer, and the influence of a small number of carriers, that is, fluctuation of the threshold voltage value and deterioration of the transistor can be reduced.

According to the present invention, the low resistance buried layer can be provided after forming the upper active region. Therefore, the use of a metal film as the low resistance buried layer does not depart from the spirit of the present invention. Furthermore, the insulating film on the bottom of the shaft is not limited to SiO _2, but is also Si ₃ N ₄ , Al ₂ O ₃ , Ta
Another insulating layer such as ₂ O ₅ may be used.

[Brief description of the drawings]

1 and FIGS. 6 and 7 are cross-sectional views showing a second embodiment of the present invention in the order of manufacturing steps. FIG. 2 (a) is a cross-sectional view showing a conventional semiconductor device. b) is its equivalent circuit diagram,
FIG. 3 to FIG. 5 are views showing manufacturing steps of the first embodiment of the present invention.

Claims (2)

(57) [Claims] 1. A pair of regions having a first conductivity type are provided in a first region having a second conductivity type, and a pair of regions having a second conductivity type have a first conductivity type. In the semiconductor device provided in the second region, a lower portion of the first region is configured to be in contact with a single crystal semiconductor substrate via a polycrystalline or amorphous semiconductor layer having a second conductivity type. A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be in contact with the semiconductor substrate from the semiconductor layer via an insulating film.