JPS62156873A - Semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate accumulation of charge under side walls and avoid degradation of gain margin even if a device is miniaturized by a method wherein a predetermined potential is given to the side walls for forming an LDD structure. CONSTITUTION:A channel region is provided between a drain region 7 and a source region 8 which are N<+> type regions formed near the surface of a silicon substrate 1 surrounded by a field oxide film 2. A gate electrode 4 and spacers 11 and 12 are formed above the channel region with a gate oxide film 3 between and a low concentration drain region 5 and a low concentration source region 6, which are N<-> type regions, are formed beneath the spacers 11 and 12 respectively. The spacers 11 and 12 are insulated and separated from the substrate 1 and the gate 4 by an insulating film 10 and made of impurity doped polycrystalline silicon and connected to the drain region 7 and the source region 8 respectively. With this constitution, a predetermined potential is given to the side walls so that charge accumulation which creates a floating gate can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a short channel structure.

[Technical background of invention m]

With the miniaturization of semiconductor devices, in conventional configurations, the shortening of the gate length causes a decrease in vth due to a short channel structure in which the drain side depletion layer tends to come into contact with the source side, and a decrease in mutual conductance gm due to the pot carrier effect. quality has deteriorated.

This hot carrier effect occurs when electrons accelerated by the electric field in the channel collide with the silicon lattice and generate electron-hole pairs. It is attracted and captured in the gate oxide film, remains as a charge, and deteriorates the quality of the interface, thereby lowering the mutual conductance gm, which is particularly a problem in the miniaturization of n-channel MoS transistors.

As a structure for preventing such a hot carrier effect, one having the cross-sectional structure shown in FIGS. 4 and 5 is known.

Figure 4 shows a low concentration drain (hereinafter referred to as IDD).
ly Doped Drain), in which a low concentration layer in the nl region is formed on the side of the channel region under the gate 4 between the drain region 7, which is the n region, and the source region 8, which are formed in the substrate 1. drain territory ia5
and a low concentration source region 6.

FIG. 5 shows another structure that has been proposed in the past.
ain ) or G D D (Graded Di
This is a cross-sectional view showing what is called a suspended drain, in which a high concentration source region 15 and a high concentration source region 16, which are n-regions, are included in a low-concentration drain region 13 and a low-concentration source region 14, which are n-regions. They were formed respectively.

In both of these, the electric field concentration associated with the n + p junction due to arsenic, which is an n-type impurity, and boron in the channel part, is reduced by n
This is intended to be alleviated by creating -n+ disasters and to prevent the occurrence of hot carrier effects.

[Problems with background technology]

However, in the G D I) structure shown in Figure 5, n
Since the n+ layer is surrounded by one layer, the aforementioned short channel effect is likely to occur. For this reason, an LDD structure is often used, but the LDD structure also has the problem of easily causing a decrease in the mutual conductance gm of the element.

That is, since the n-layer functions as a direct current resistance for the source and drain regions, it causes a decrease in gm of the device.

The spacer for forming the above-mentioned LDD structure is CV
It is formed by etching an insulating film such as a silicon oxide film formed by D iA using anisotropic etching such as RIE, but this spacer is in a floating state and is not electrically connected to anything. Ori,
When electrons, mainly among hot carriers, are injected and captured, negative charges accumulate on the n-region, forming a depletion layer or a P-type inversion layer on the surface of the n-region, leading to an increase in the DC resistance of the device. , a phenomenon has been observed that further reduces gm. This depends on the trap level for electrons in the insulating film serving as a spacer.

[Purpose of the invention]

The present invention was made to solve these problems, and an object of the present invention is to provide a semiconductor device having an LDD structure with high mutual conductance.

(Summary of the Invention) A semiconductor device according to the present invention includes a gate electrode formed on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a gate electrode formed around the gate electrode, insulated and separated from the surroundings, and at a predetermined potential. a conductive side wall portion given a conductive side wall portion, a low concentration first opposite conductivity type impurity diffusion region formed in the semiconductor substrate under the conductive side wall portion, and a first opposite conductivity type impurity diffusion region formed in the semiconductor substrate outside the conductive side wall portion. and highly-concentrated second opposite conductivity type impurity diffusion regions that serve as source and drain regions. This prevents the accumulation of hot carrier charges and prevents a decrease in Qm.

[Embodiments of the invention]

Hereinafter, some embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cross-sectional structural diagram showing one embodiment of a semiconductor device according to the present invention, in which, as in the case of FIG. A gate electrode 4 is formed on the channel region side between the drain region 7 and source region 8 with a gate oxide film 3 interposed therebetween. Spacers 11J3 are provided on the drain region side and the source region side of the gate electrode 4, respectively.
and 12 are formed below, respectively, an n-region low concentration drain region 5 and a low temperature source region 1Ii.
16 are formed. These spacers 11 and 12 are conventionally insulating materials, but here they are insulated from the substrate 1 and the gate 4 by an insulating film 10, are made of impurity-doped polycrystalline silicon, and are made of impurity-doped polycrystalline silicon.
17 and source region 8 . The reason why a predetermined potential is applied to the side wall portion in this way is to prevent charges from being accumulated there and forming a floating gate since the side wall portion is conductive.

FIG. 2 is a top-to-bottom view showing another embodiment of the semiconductor device according to the present invention, and has basically the same structure as FIG. 1. The difference is insulation! It is at this point that the conductive side 7, isolated by J10, is connected to a power source.

In such a configuration, when the side wall is connected to the power supply, the low aii! Since a large number of electrons, which are movable charged particles, are always present on the surface of the n layer, no charge is accumulated and the parasitic resistance of the source and drain does not increase. Moreover, since these mobile electrons move due to an increase in the drain electric field, the drain electric field is not increased, and an increase in the parasitic resistance can be stably suppressed.

However, if a voltage is constantly applied, the margin against breakdown of the insulating film may be reduced to some extent.

In the embodiment shown in FIG. 1, since the sidewall portions 11.12 are connected to the source and drain, hot electrons generated near the drain reach the substrate-glue-insulating film interface near the n-n interface. Even if the electric field flows into the side wall portion due to the vertical electric field, it immediately flows into the train, so there is no accumulation of charge, and no increase in parasitic resistance is caused. Moreover, since the 'H pressure is not always applied, the margin against insulation film breakdown does not change.

FIG. 3 is a cross-sectional view of an element by step, showing the process of manufacturing a semiconductor device according to the present invention.

First, a field oxide film 2 for element isolation is formed in a predetermined region on the surface of a semiconductor substrate 1 by a known method, and a gate oxide film 3 is formed by oxidizing the surface of the substrate 1. Next, a polycrystalline silicon film is deposited over the entire structure by the CVD method, impurities are implanted and diffused, and then this is patterned to form the gate electrode 4. Next, using gate electrode 4 as a mask, shallow, low-concentration n- diffusion layers 5 and 6 are formed on the surface of substrate 1 using phosphorus or hydrogen. Subsequently, oxidation is performed to form an insulating film 10 around the goo 1-electrode 4 and on the surface of the substrate 1.
is formed, and a polycrystalline silicon layer 9 is deposited thereon by the CVD method (FIG. 3(a)).

Next, the entire surface is etched by reactive ion etching (RrE> method) so that the surface d3 of the gate electrode 4 and the surface of the substrate are exposed (FIG. 3(b)). Sidewall portions 11 and 12 separated and insulated by the insulating film 10 remain.

Next, by using this side wall portion 11 and 12 as an ion implantation mask, phosphorus or arsenic is implanted at a high concentration and then diffused, thereby forming a high concentration and deep n-ion that will become the drain and source.
1M7 and 8 are formed (Fig. 3C)). At this time, impurities are also diffused into the side walls 11 and 12, making them conductive.

Thereafter, an insulating film is formed over the entire surface, predetermined holes are formed, and aluminum or the like is vapor-deposited and patterned to form the side wall portion 10.
11 can be given a predetermined potential.

(Effects of the Invention) As described above, according to the present invention, since a predetermined potential is applied to the sidewall portion for forming the LDD structure, this sidewall nI
It is possible to provide a highly reliable semiconductor device in which there is no charge accumulation underneath, which does not cause an increase in source and drain parasitic resistance, and whose gm does not decrease even when miniaturized to 1111.

[Brief explanation of drawings]

FIG. 1 is a sectional structural diagram showing one embodiment of a semiconductor device according to the present invention, FIG. 2 is a sectional structural diagram showing another embodiment of the present invention, and FIG. 4 and 5 are cross-sectional views showing the structure of a conventional short chisel element. 1... Semiconductor substrate, 4... Gate electrode, 5, 6・・・
・n single layer, 7, 8...n+ layer, 1o...insulating film, 1
1.12...Side wall part. Applicant's agent Mr. Sato Figure 1

Claims (1)

[Claims] 1. A gate electrode formed on the surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a gate electrode formed around this gate electrode, insulated and separated from the surroundings, and given a predetermined potential. a conductive sidewall, a first low concentration reverse conductivity type impurity diffusion region formed in the semiconductor substrate under the sidewall;
A semiconductor device comprising: a second opposite conductivity type impurity diffusion region of high concentration, which is formed in the semiconductor substrate outside the lower part of the conductive sidewall and serves as a source and drain region. 2. The semiconductor device according to claim 1, wherein a power supply potential is applied to the conductive sidewall portion. 3. The semiconductor device according to claim 1, wherein the conductive sidewall portion is connected to the second opposite conductivity type impurity diffusion region.