JPS6249665A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the deterioration in current driving capability by a method wherein, after a low density region is formed, a second gate electrode is self- matchingly formed on the side wall of a first gate electrode, and a high density source and drain region is formed by performing an ion implantation. CONSTITUTION:After a thermally oxided film 2 is formed on a P-type Si substrate 1, a first gate electrode 3 of N<+> polysilicon film is formed. Then, phosphorus ions 4 are ion-implanted, and a low density N<-> layer 5 is formed. Subsequently, a polysilicon film 6 is deposited on the whole surface using a chemical vapor deposition (CVD) technique. Then, an anisotropic etching, which is a reactive etching, is performed on the polysilicon film 6, the film 6 is left on the side wall part of the first gate electrode 3, and a second gate electrode is formed. Subsequently, arsenic ions 7 are ion-implanted, and the transistor of LDD structure is formed by obtaining a high density N<-> layer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing an MO8 field effect transistor, and more particularly to a method for manufacturing a transistor in which electric field concentration inside the transistor is alleviated.

[Technical background of the invention and its problems]

Currently, the dimensions of MO8 type field effect transistors are being reduced due to higher integration, but one of the problems caused by this is the influence of electric field concentration near the drain. This occurs because the power supply 11EE is not reduced even though the element size is reduced. Electrons accelerated near the drain are one of the causes of hot electrons and hot carriers. The electrons trapped in the gate oxide film cause a shift in threshold value, reducing the reliability of the 1M08) transistor.

Various device structures have been proposed as methods for alleviating such electric field concentration near the drain, weakening the generation of hot electrons and hot carriers, and further reducing threshold fluctuations. One of them is L as shown in Figure 2.
It has a DD (Lightly Doped Drain) structure. This is to form an n layer with a low impurity concentration in the direction of the gate of the drain, thereby attempting to alleviate the electric field near the drain. This is done by ion-implanting impurities using the gate electrode 5 as a mask to form a low-concentration layer 3, and then implanting impurity ions using the insulating film 4 formed on the side wall of the gate electrode 5 as a mask to form a high-concentration layer 3. Forms a leaf layer. When creating an LDD structure in this manner, an insulating film such as an oxide film is generally used as a mask material for ion implantation on the sidewall of the gate electrode.

However, even this LDD structure cannot completely suppress the generation of hot electrons.
Electrons 6 are injected into the interface.

The injected electrons 6 cause the layer 3 and the sidewall insulating film 4 to
Since the interface is negatively charged, electrons flowing through the channel are repelled by Ni and cannot flow near the interface. Therefore, the resistance in one layer increases, causing problems such as a decrease in current driving ability. Therefore, in a transistor using an LDD structure, the sidewall insulating film and the n
There is a need for a method of manufacturing an LDD structure that reduces or eliminates the effects of electrons injected and trapped at layer interfaces.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that makes it possible to obtain a gate electrode structure that suppresses a decrease in the current driving ability of a transistor in a process for manufacturing a transistor using an LDDq structure.

[Summary of the invention]

In the present invention, as shown in FIG.
In this method, the source and drain 8 are formed in a self-aligned manner, and impurity ions are implanted using the eleventh second gate electrode as a mask to form the source and drain 8 in the high concentration region.

〔Effect of the invention〕

According to this invention, since the gate electrode is also formed on the low concentration region, the electric field generated between the hot electrons injected and captured at the interface between the low concentration region and the insulating film thereon and the substrate is relaxed. This allows carriers flowing through the channel to flow near the interface even in the lightly doped layer, and can prevent the current driving ability of the transistor from deteriorating.

[Embodiments of the invention]

An embodiment of the present invention will be explained using Figure @1.

First, for example, as shown in FIG. 1(a), a P-type main thermal oxide film 2 of about 200 to 400 A is formed, and then a first gate electrode 3 made of a polysilicon film is formed. Next, as shown in Figure 1 Φ), phosphorus ions (P+
-)4 for example, oszii2X with an acceleration voltage of 35Kev
l O"Crrr' degree ion implantation, <FHI degree (
7) Form n layer 5. Next, as shown in FIG. 1 (Q), a polysilicon film 6 is deposited on the entire surface using CVD technology.Next, the polysilicon film 6 is anisotropically etched by reactive ion etching. As shown in FIG. 1(d), arsenic ions (As) are left on the side walls of the first gate electrode 3 to form a second gate electrode.Next, as shown in FIG. ') 7re example,
tGi power supply EE50Kev, DO8IC amount 1.8×1
By implanting ions to the extent of 'atf' and forming a highly concentrated 'atf' layer 8, an LDD structure transistor can be formed.In the LDD structure transistor formed in this way, the first gate electrode 3 and the Since two gate electrodes 6 are formed of the same polysilicon film, electrically one
Facultative.

Therefore, when the transistor is in the ON state,
A positive voltage is also applied to the second gate 1 pole 6, and the electric field generated between the hot electrons injected and captured at the interface between the 11 layer 5 and the gate bulging film 2 and the n layer 5 is relaxed. Therefore, the electrons flowing through the channel part can flow near the interface without being repelled by the captured hot electrons even within the layer 5, and good transistor characteristics can be obtained without reducing the current drive ability. can.

Here, the deposited polysilicon film 6 is used as it is, but phosphorus ions (P+) may be introduced into the polysilicon film 6 by diffusion or ion implantation after deposition to form n+ polysilicon.

In this way, the resistance of the second gate ('1t8R) can be lowered, and the access time of the LSI can also be shortened. Further, after using W, Mo, etc., which have a slow oxidation rate, as the first gate electrode and implanting phosphorus ions (P+) 4, the temperature is heated at, for example, 900'C.

Oxidation may be performed in dry oxygen.

Thereafter, the oxide film may be etched to the extent that the extremely thin oxide film on the surface of the first gate is exposed.

The purpose of this is to increase the thickness of the oxide film 2 that was etched and thinned when the gate electrode 3 was processed by RIB, and thereby the second gate electrode 6
It is possible to improve the withstand voltage of the underlying acid film, further increasing reliability.

[Brief explanation of the drawing]

FIGS. 1(a) to 1(e) are cross-sectional views showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the conventional LI, D structure. In the figure, 1...Si substrate, 2...Oxide film, 3...Total polysilicon, 4-degree bioion 5..."layer, 6...Polysilicon, 7...As ~, On, 8...n1 agent Patent attorney Nori Chika Ken Yudo Takehana Kikuo~ -~ ＼

Claims (2)

[Claims] (1) forming a gate insulating film on a semiconductor substrate, forming a first gate electrode thereon using a first conductive film;
Next, using the gate electrode as a mask, there is a step of ion-implanting an impurity of conductivity type opposite to that of the substrate, and then, after laminating a second conductive film, the second conductive film is anisotropically etched to form the first gate electrode. forming a second gate electrode by leaving it on the side wall of the first gate electrode in a self-aligned manner;
and a step of ion-implanting an impurity of conductivity type opposite to that of the substrate using the second gate electrode as a mask to form a source and a drain. (2) After ion-implanting an impurity having a conductivity type opposite to that of the substrate using the first gate electrode as a mask, the source and drain are thermally oxidized to form an oxide film. A method for manufacturing a semiconductor device according to section 1.