JPH0519979B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an insulated gate (MOS) field effect semiconductor device having a Lightly Doped Drain (hereinafter referred to as LDD) structure. It is related to.

[Prior Art] FIGS. 2a to 2c are cross-sectional views showing the main stages of a conventional method for manufacturing a semiconductor device of this type. First, as shown in FIG. 2a, a gate insulating film 2 and a gate electrode 3 are formed on a p-type silicon substrate 1, and using this gate electrode as a mask, a low concentration of n-type impurity is ion-implanted as shown by the arrow in the figure. By doing so, the low concentration n-type region 4 of the source/drain
form. Next, as shown in Figure 2b, the pressure is reduced.
CVD (Low Pressure Chemical Vapor)
An oxide film 9 is deposited using a method (deposition). Furthermore, as shown in Figure 2c, RIE (Reactive Ion)
The oxide film 10 is left only on the gate side wall by anisotropic etching (etching), and then, using the gate electrode and the remaining gate side wall 10 as a mask, as shown by the arrow in the figure, a high concentration n-type oxide film is formed. By ion-implanting impurities and forming the high concentration n-type region 5, the low concentration n-type region 4 and the high concentration n-type region 4 having a desired width are formed.
An LDD structure having a shaped region 5 is formed.

[Problem that the invention seeks to solve]

In the conventional LDD structure, an oxide film 1 is placed on the gate sidewalls.
0 was used, so during MOSFET operation, hot carriers were transferred to the oxide film 1 on the sidewall of the gate on the drain side.
0, thereby creating a low concentration n-type (n ^-
There was a problem in that the n - type region 4 became depleted, the resistance of the n ^- type region 4 increased, and the transconductance of the MOSFET deteriorated.

This invention was made to solve the above-mentioned problems, and an object thereof is to provide a manufacturing method for obtaining a MOS field-effect semiconductor device in which the transconductance does not decrease even when hot carriers are injected into the gate sidewall. It is said that

[Means for solving problems]

The method for manufacturing a semiconductor device according to the present invention includes:
The ion implantation mask to obtain the LDD structure is
It consists of a gate electrode and a sidewall made of a high melting point metal or its silicide, and the sidewall is left to remain after ion implantation.

[Effect]

In this invention, since a side wall made of a high melting point metal or its silicide is left on the side wall of the gate electrode, the gate electrode and the low impurity concentration region overlap, resulting in a structure in which the resistance value of the low impurity concentration region is reduced. It changes depending on the gate voltage and can improve the current driving ability of the LDD.

〔Example〕

FIGS. 1A to 1D are cross-sectional views showing the main stages of a method according to an embodiment of the present invention. First, as shown in FIG. A gate electrode layer 11 consisting of a crystalline silicon gate electrode 3 is formed, and this gate electrode 3
For example, using phosphorus ions (p ⁺ ) as a mask,
1× through the gate insulating film 2 at an accelerating voltage of 50 keV.
10 ¹³ (pcs/cm ² ) n ^- type area 4 by implanting
form. Next, as shown in FIG. 1b, a tungsten layer 12, which is a high melting point metal, is deposited to a thickness of 4000 Å by, for example, sputtering. Next, as shown in FIG. 1c, RIE anisotropic etching is performed to leave the remaining gate sidewall portion 13 of tungsten only on the gate sidewall. Then, the exposed portion of gate oxide film 2 is removed. As shown in FIG. 1c, this gate sidewall remaining portion 13 has a smooth conformal shape, and the vertical step of the gate electrode is reduced. After that, using the gate electrode layer 11 and the remaining tungsten gate sidewall portion 13 as a mask, arsenic ions (As ⁺ ) are added at 4×10 ¹⁵ (pieces/cm ² ) at an accelerating voltage of 50 keV.
The LDD structure is obtained by implanting and forming an n ⁺ type region 5.
Thereafter, as shown in FIG. 1d, a protective insulating film 14 is formed, required contact holes are formed therein, and then electrode wirings 15 are formed to complete the device.

In the above embodiments, the case of an n-channel MOS field-effect semiconductor device has been described, but of course the present invention can also be applied to the manufacture of a p-type channel MOS field-effect semiconductor device in which p-type impurity ions are implanted using an n-type substrate. Moreover, the silicide may be used instead of the high melting point metal in the embodiment.

〔Effect of the invention〕

As described above, according to the present invention, the remaining part of the gate sidewall for obtaining the LDD structure is formed of a high melting point metal or its silicide and left to remain, so that the gate electrode and the low impurity concentration region overlap. With this configuration, a part of the hot carrier can be drawn out from the gate electrode side, and a MOS field effect semiconductor device can be obtained in which the transconductance does not decrease due to injection of the hot carrier.

[Brief explanation of the drawing]

1A to 1D are cross-sectional views showing the main process steps of a method according to an embodiment of the present invention, and FIGS. 2A to 2C are main process steps of a conventional method for manufacturing a MOS field effect semiconductor device having an LDD structure. FIG. In the figure, 1 is a silicon substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a low impurity concentration source/drain region, 5 is a source/drain high impurity concentration region, 11 is a gate electrode layer, 12 is a high impurity concentration region The layer of melting point metal or its silicide, 13, is the gate sidewall remainder of the refractory metal or its silicide. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] 1. A first step of forming a gate insulating film and a gate electrode on a silicon substrate of a first conductivity type; using the gate electrode as a mask, impurities of a second conductivity type are formed on the surface of the silicon substrate; a second step of ion-implanting to form source/drain regions with low impurity concentration; a third step of forming a layer of a high melting point metal or its silicide on the entire surface of the silicon substrate; a third step of forming a layer of the high melting point metal or its silicide; A fourth step of performing anisotropic etching on the silicide layer to form a sidewall forming a part of the gate electrode on the gate insulating film, and etching a second conductivity type using the gate electrode and the sidewall as a mask. a fifth step of ion-implanting impurities to form high impurity concentration regions in the source/drain regions.