JPS60113472A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60113472A JPS60113472A JP22097683A JP22097683A JPS60113472A JP S60113472 A JPS60113472 A JP S60113472A JP 22097683 A JP22097683 A JP 22097683A JP 22097683 A JP22097683 A JP 22097683A JP S60113472 A JPS60113472 A JP S60113472A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- mask
- ion implantation
- impurity region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000012535 impurity Substances 0.000 claims abstract description 48
- 238000000034 method Methods 0.000 claims abstract description 24
- 238000005468 ion implantation Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000002844 melting Methods 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 229910021332 silicide Inorganic materials 0.000 claims 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 15
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052721 tungsten Inorganic materials 0.000 abstract description 13
- 239000010937 tungsten Substances 0.000 abstract description 13
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 4
- 239000011574 phosphorus Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000001947 vapour-phase growth Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 230000001133 acceleration Effects 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 4
- 229910021342 tungsten silicide Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229920000642 polymer Polymers 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特にＭＯ８半導
体装置の製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an MO8 semiconductor device.
近年、ＬＳＩの集積度は年々向上し、回路を構成する素
子の寸法は益々小さくなっている。ところが、ＭＯ８半
導体装置ではチャネル長が短くなるにつれ、いわゆるシ
ョートチャネル効果によりトランジスタのスレッショル
ド電圧が著しく低下する等の欠点が生じてくる。これは
主としてドレイン電圧による空乏層がチャネル領域に侵
入することにより、チャネル領域での電荷がゲート電圧
のみならず、ドレイン電圧によつても影響されるからで
ある。In recent years, the degree of integration of LSIs has improved year by year, and the dimensions of elements constituting circuits have become smaller and smaller. However, as the channel length of the MO8 semiconductor device becomes shorter, drawbacks arise such as a significant drop in the threshold voltage of the transistor due to the so-called short channel effect. This is mainly because the charge in the channel region is affected not only by the gate voltage but also by the drain voltage, as a depletion layer due to the drain voltage invades the channel region.
こうしたショートチャネル効果を防ぐ方法としてチャネ
ル領域へ基板さ同導電型の不純物をイオン注入してチャ
ネル領域の基板濃度を高くするとともにソース、ドレイ
ン領域の接合深さくＸ】）を浅くする技術が矧られてい
る。しかし、ｘｊを浅くすることはドレイン近傍での電
界強度を大きくし、ドレイン耐圧の低下を招くたけでな
く、ホットキャリアの発生率を高め、スレッショルド電
圧の不安定性を増し、信頼性を低下させる原因となる。As a method to prevent such short channel effects, a technique has been developed to increase the substrate concentration in the channel region by ion-implanting impurities of the same conductivity type as the substrate into the channel region, and to reduce the junction depth of the source and drain regions. ing. However, making xj shallower not only increases the electric field strength near the drain and lowers the drain breakdown voltage, but also increases the generation rate of hot carriers, increases the instability of the threshold voltage, and reduces reliability. becomes.
才だ、基ｇ濃度を高くすることはチャネル領域の静電容
量を太きくし、サブスレッショルド特性と基板バイアス
特性を悪化させる原因となる。However, increasing the group concentration increases the capacitance of the channel region, which causes deterioration of subthreshold characteristics and substrate bias characteristics.
上述したような欠点を解消するために、最近の新しい技
術としてＰ（あるいはＮ）ポケット形成技術が矧らｎて
いる（例えば、Ｓ、 Ｏｇｕｒａｅｔ ａ＋ 、 ’
Ａ ｈａｌｆ ｍ１ｃｒｏｎ ＭＯＳＦＥＴ ｕｓｉｎ
ｇｄｏｕｂｌｅ １ｍｐｌａｎｔｅｃｊ ＬＤＤ、 ”
ＩｎｔｅｒｎａｔｉｏｎａｌＥｌｅｃｔｒｏｎ Ｄｅ
ｖｉｃｅｓ Ｍｅｅｔｉｎｇ Ｔｅｃｈｎｉｃａｌ Ｄ
ｉｇｅｓｔ７１８、（１９８２））。この方法を第１図
（，１〜（ｃ）を参照して説明する。In order to overcome the above-mentioned drawbacks, there are many new P (or N) pocket formation techniques recently (for example, S, Oguraet a+, '
A half m1cron MOSFET usin
gdouble 1plantecj LDD, ”
International Electron De
vices Meeting Technical D
igest718, (1982)). This method will be explained with reference to FIGS.
まず、例えばＰ型シリコン基板、１表面にフィールド酸
化膜２を形成した後、フィールド酸化膜２によって囲す
れた基板１表面にゲート酸化膜３を形成する。次に、全
面に多ｆと晶シリコン膜を堆積した後、パターニングし
てゲート′電極４を形成する。つづいて、ゲート電極４
をマスクとしてｎ型不純物をイオン注入してソース。First, a field oxide film 2 is formed on the surface of a P-type silicon substrate, for example, and then a gate oxide film 3 is formed on the surface of the substrate 1 surrounded by the field oxide film 2. Next, a polycrystalline silicon film is deposited on the entire surface and then patterned to form a gate' electrode 4. Next, gate electrode 4
Using this as a mask, n-type impurity ions are implanted into the source.
ドレイン領域の一部となる浅いｎ−型不純物領域５．５
を形成する。つづいて、ゲート電極４をマスクとしてｐ
型不純物をイオン注入してｐポケットとなるｐ型不純物
領域６，６を形成する（第１図（ａ１図示）。Shallow n-type impurity region 5.5 which becomes part of the drain region
form. Next, using the gate electrode 4 as a mask, p
P-type impurity regions 6, 6 which will become p-pockets are formed by ion implantation of type impurities (FIG. 1 (a1 diagram)).
次いで、全面に例えばＣＶＤ酸化膜７を堆積する（同図
（ｂ１図示）。つづいて、異方性ドライエツチングによ
りＣＶＤ酸化膜７をエツニングし、ゲート電極４の側壁
にＣＶＤ酸化膜７／ 、 ７１を残存させる。つづいて
、ゲート電極４及び残存したＣＶＤ酸化膜７’、７′を
マスクとしてｎ型不純物をイオン注入して深いｎ 型不
純物領域８，８を形成する。この結果、チャネル領域近
傍の浅いｎ”−型不純物領域５，５とこれらの領域【こ
隣接する深い層型不純物領域８．８とからなるソース。Next, for example, a CVD oxide film 7 is deposited on the entire surface (as shown in FIG. Next, using the gate electrode 4 and the remaining CVD oxide films 7', 7' as masks, n-type impurity ions are implanted to form deep n-type impurity regions 8, 8. As a result, deep n-type impurity regions 8, 8 are formed near the channel region. A source is made up of shallow n''-type impurity regions 5, 5 and an adjacent deep layer impurity region 8.8.
ドレイン領域９，１０及びチャネル領域近傍の浅Ｇ）ｎ
−型不純物価域５，５の下部に位置するｐ型不純物領域
（ポケット領域）６，６が形成される（同図（ｃ）図示
）。Shallow G)n near drain regions 9, 10 and channel region
P-type impurity regions (pocket regions) 6, 6 located below the --type impurity regions 5, 5 are formed (as shown in FIG. 13(c)).
第１図（ｃ）図示のＭＯ３Ｉ−ランジスタはｐ型不純物
領域（ポケット領域）６，６の存在によりショートチャ
ネル効果を低減することができ、またｐ型不純物領域（
ポケット領域）６，６の上部の浅いｎ−型不純物領域５
，５によりドレイン耐圧の低下を防止し、ホットキャリ
アの発生を低減することができる。更に、チャネル領域
の不純物濃度を通常行なわｎるチャネルイオン注入によ
る濃度程＃に低くすることができるので、サブスレッシ
ョルド特性と基板バイアス特性も同上する。The MO3I-transistor shown in FIG. 1(c) can reduce the short channel effect due to the presence of p-type impurity regions (pocket regions) 6, 6, and the p-type impurity regions (
Shallow n-type impurity region 5 on top of pocket region) 6, 6
, 5 can prevent a decrease in drain breakdown voltage and reduce the generation of hot carriers. Furthermore, since the impurity concentration in the channel region can be made as low as the concentration by channel ion implantation which is normally performed, the subthreshold characteristics and substrate bias characteristics are also the same.
しかしながら、この方法では第１図（ｃ）の工程でゲー
ト電極４の側壁に残存させるＣＶＤ酸化膜ｙＬ、ｙＬの
寸法制御が極めて困難であるという欠点を有している。However, this method has the drawback that it is extremely difficult to control the dimensions of the CVD oxide films yL, yL left on the side walls of the gate electrode 4 in the step shown in FIG. 1(c).
すなわち、ＣＶＤ酸化［７’ 。That is, CVD oxidation [7'].
７１の寸法精度にはＣＶＤ酸化膜７の膜厚、ＣＶＤ酸化
膜７のエツチング速度、エツチングＭ度等の均一性、エ
ツチング前後の表面処理による酸化膜の後退等が影響す
るため、寸法の制御性が低下する。特に、ウェハの大口
径化に伴い、ウェハ面内のＣＶＤ酸化膜７の膜厚のバラ
ツキや、異方性エツチング時のエツチング速度の面内分
布は増大する傾向にある。したがって、残存させるＣＶ
Ｄ酸化膜７／、ｙ／の寸法が太きすぎる場合にはｎ−型
不純物領域５，５の抵抗が必要以上に大きくなり、電流
増幅率を低下させる。一方、残存させるＣＶＤ酸化膜７
／、７／の寸法が小さすぎる場合にはｎ−型不純物領域
５，５の幅が小さくなり、ドレイン耐圧の低下を抑制す
る効果が充分でなくなる。The dimensional accuracy of 71 is affected by the thickness of the CVD oxide film 7, the etching rate of the CVD oxide film 7, the uniformity of the etching M degree, etc., and the recession of the oxide film due to surface treatment before and after etching, so the controllability of the dimension is affected. decreases. In particular, as the diameter of the wafer becomes larger, the variation in the thickness of the CVD oxide film 7 within the wafer surface and the in-plane distribution of the etching rate during anisotropic etching tend to increase. Therefore, the remaining CV
If the dimensions of the D oxide films 7/, y/ are too large, the resistance of the n-type impurity regions 5, 5 will become larger than necessary, reducing the current amplification factor. On the other hand, the CVD oxide film 7 to remain
If the dimensions of / and 7/ are too small, the widths of n-type impurity regions 5 and 5 will become small, and the effect of suppressing a decrease in drain breakdown voltage will not be sufficient.
また、異方性ドライエツチングを用いているので、エツ
チング時に基板１表面０こダメージ層が発生したり、用
いるガス（例えばＣＦ、）の反応により基依１上にポリ
マーが堆積され、素子特性を劣化させる原因となる。In addition, since anisotropic dry etching is used, a damaged layer may be generated on the surface of the substrate 1 during etching, and polymer may be deposited on the substrate 1 due to the reaction of the gas used (for example, CF), which may affect the device characteristics. This may cause deterioration.
本発明は上記事情に鑑みてなさｎたものであり、簡便な
工程で上記３種の不純物領域を精度よく形成し、素子特
性の良好な半導体装置を製造し得る方法を提供しようと
するものである。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device with good element characteristics by forming the three types of impurity regions with high precision using a simple process. be.
本発明の半導体装置の製造方法は、第１導電型の半導体
基板表面にゲート絶縁膜を形成し、ゲート絶傍膜上にゲ
ート電極を形成した後、ゲート電極をマスクとするイオ
ン注入によりポケット領域となる第１導電型の不純物領
域と、ソース、ドレインの一部となる第２導電型の低濃
度不純物領域を形成し、更にゲート電極の少なくとも側
壁に被膜（例えば金属、金属半導体化合物又は半導体）
を選択成長させた後、ゲート電極及び被膜をマスクとす
るイオン注入によりソース、ドレインとなる第２導電型
の高濃度不純物領域を形成することを骨子とするもので
ある。In the method of manufacturing a semiconductor device of the present invention, a gate insulating film is formed on the surface of a semiconductor substrate of a first conductivity type, a gate electrode is formed on a gate insulating film, and then pocket regions are formed by ion implantation using the gate electrode as a mask. An impurity region of a first conductivity type is formed, and a low concentration impurity region of a second conductivity type is formed, which becomes a part of the source and drain, and a film (for example, a metal, a metal semiconductor compound, or a semiconductor) is formed on at least the sidewalls of the gate electrode.
The gist of this method is to selectively grow the oxide and then perform ion implantation using the gate electrode and film as a mask to form highly concentrated impurity regions of the second conductivity type that will become the source and drain.
このような方法ζこよれば、ポケット領域及びソース、
ドレインの低濃度不純物領域をゲート電極の少なくとも
側壁に被膜を選択成長させた後の第２導電型の不純物の
イオン注入により自己整合的に形成することができ、こ
れらの寸法を被膜の膜厚のみζこよって決定できるので
寸法の制御性が極めて良好となる。しかも、工程が簡便
で、異方性ドライエツチングを用いないので素子特性を
劣化させることがない。According to such a method, pocket areas and sources,
The low-concentration impurity region of the drain can be formed in a self-aligned manner by selectively growing a film on at least the sidewalls of the gate electrode and then implanting impurities of the second conductivity type, and these dimensions can be adjusted only by the thickness of the film. Since it can be determined by ζ, the controllability of dimensions is extremely good. Furthermore, the process is simple, and since anisotropic dry etching is not used, there is no deterioration of device characteristics.
以下、本発明をｎチャネルＭＯ８Ｉ−ランジスタの製造
に適用した実施例を第２図（ａｌ〜（ｄ）を参朋して説
明する。Hereinafter, an embodiment in which the present invention is applied to the manufacture of an n-channel MO8I-transistor will be described with reference to FIGS.
まず、比抵抗１０〜２０Ω・備のｐ型シリコン基板１１
表面に厚さ１，２μｍのフィールド酸化膜１２を形成し
た後、フィールド酸化膜１２によって囲まれた基板１１
表面に膜厚２５０Ｘのゲート酸化膜１３を形成する。次
に、しきい値制御のためにＢ＋を加速エネルギー２５
ＫｅＶ 、ドーズｆ９ Ｘ １０””２の条件でチャネ
ルイオン注入する。つづいて、全面に膜厚０．４μｍ
、 ／５＝２０Ω／口の多結晶シリコン膜を堆積した後
、写真蝕刻法によりパターニングしてゲート電極１４を
形成する。つづいて、ゲート電標１４をマスクとしてリ
ンを加速エネルギー８０ ＫｅＶ 。First, a p-type silicon substrate 11 with a specific resistance of 10 to 20Ω
After forming a field oxide film 12 with a thickness of 1 to 2 μm on the surface, the substrate 11 surrounded by the field oxide film 12 is
A gate oxide film 13 with a thickness of 250× is formed on the surface. Next, for threshold control, accelerate B+ with energy 25
Channel ions are implanted under the conditions of KeV and dose f9 x 10''2. Next, a film thickness of 0.4 μm was applied to the entire surface.
After depositing a polycrystalline silicon film of . Next, using the gate voltage mark 14 as a mask, phosphorus was accelerated to an energy of 80 KeV.
ドーズ量５ｘｌＯａｎ の条件でイオン注入してソース
、ドレインの一部となる浅いｎ−型不純物領域１５．１
５を形成する。更に、ゲート電極１４をマスクとしてボ
ロンを加速エネルギー８０ ＫｅＶ 、 ドーズ量５Ｘ
１０１２Ｃ１２の条件でイオン注入してポケット領域と
なるｐ型不純物領域１６．１６を形成する（第２図（ａ
）図示）。Shallow n-type impurity regions 15.1 are implanted at a dose of 5xlOan to become part of the source and drain.
form 5. Further, using the gate electrode 14 as a mask, boron was accelerated at an energy of 80 KeV and a dose of 5X.
Ion implantation is performed under the conditions of 1012C12 to form a p-type impurity region 16.16 which will become a pocket region (see Fig. 2(a)).
).
次いで、Ｎ２中、９５０℃で２０分間アニールした後、
表面を洗浄する。つづいて、ＷＦ６ガスを用い、流量５
ＣＣ／ａｎ 、真空度０．００５ Ｔｏｒ、 。Then, after annealing at 950° C. for 20 minutes in N2,
Clean surfaces. Next, using WF6 gas, flow rate 5
CC/an, degree of vacuum 0.005 Tor.
温度５００℃の条件で気相成長を行ない、前記・デート
電極１４の表（２）にのみ選択的ｌこ膜厚０．３μｍの
タングステン膜１７を形成する。この際、多結晶シリコ
ンからなるゲート電極１４以外の絶縁膜上にはタングス
テン膜１７は形成さ几ない（同図（ｂ１図示）。Vapor phase growth is carried out at a temperature of 500° C., and a tungsten film 17 having a thickness of 0.3 μm is selectively formed only on the table (2) of the date electrode 14. At this time, the tungsten film 17 is not formed on the insulating film other than the gate electrode 14 made of polycrystalline silicon (as shown in the figure (b1)).
次いで、ゲート電極１４及びタングステン膜１５をマス
クとして例えばリンを加速エネルギ１００ ＫｅＶ 、
ドーズ量３ｘｌＯｃｍ の条件でイオン注入してソース
、ドレインとなる深いｎ＋型不純物領域１８．１８を形
成する。、この結果、チャネル領域近傍の浅いｎ−型不
純物領域１５．１５とこれらの領域に隣接するｎ 型不
純物領域Ｉｌｌ、１８とからなるソース、ドレイン領域
１９．２０及びチャネル領域近傍のＩ−型不純物領域１
５．１５下部に位置するｐ凰不純物領域（ポケット領域
）１６．１６（ボロン濃度Ｉ Ｘ １０１６〜５ｘｔｏ
１７ｍ−”）が形成される（同図（ｃ１図示）。Next, using the gate electrode 14 and the tungsten film 15 as a mask, for example, phosphorus is accelerated at an energy of 100 KeV,
Deep n+ type impurity regions 18.18 which will become sources and drains are formed by ion implantation at a dose of 3xlOcm. , As a result, the source and drain regions 19.20 consisting of shallow n-type impurity regions 15.15 near the channel region and the n-type impurity regions Ill and 18 adjacent to these regions and the I-type impurity near the channel region. Area 1
5.15 p-type impurity region (pocket region) located at the bottom 16.16 (boron concentration I
17m-'') is formed (shown in the same figure (c1)).
つづいて、全面にＣＶＤ酸化膜２１を堆積し、アニール
を行なった後、コンタクトホールを開孔する。つづいて
、全面にＡｌ膜を蒸着した後、パターニングしてｈｌｌ
配線２２．２２を形成し、。Subsequently, a CVD oxide film 21 is deposited on the entire surface, annealed, and then contact holes are formed. Next, after depositing an Al film on the entire surface, patterning is performed to form hll
Wires 22.22 are formed.
チャネルＭＯ８Ｉ−ランジスタを製造する（同図（ｄ）
図示）。Manufacture channel MO8I-transistor (Figure (d))
(Illustrated).
しかして上記方法によれば、第２図（ｂ）の工程でゲー
ト電極１４の表面に選拒成長させるタングステン膜１７
の膜厚のみによって同図（ｄ１図示のｎ−型不純物領域
１５．１５及びｎ型不純物領域（ポケット領域）１６，
１６の寸法が決定されるので、寸法の制御性が極めて良
好となる。According to the above method, the tungsten film 17 selectively grows on the surface of the gate electrode 14 in the step shown in FIG. 2(b).
The n-type impurity region 15.15 and the n-type impurity region (pocket region) 16,
Since 16 dimensions are determined, the controllability of the dimensions is extremely good.
したがって、ショートチャネル効果やドレイン耐圧の低
下を有効に防止することができる。また、気相成長法と
異方性エツチングとによりゲート１１Ｌ極の側壁に絶縁
膜を残存させる従来の方法き比較して工程が簡略さなる
。更に、異方性ドライエツチングを用いることがないの
で、基板表面にダメージ層を形成することがなく、ポリ
マーの堆積に伴う素子特性の劣化を起こすこともない。Therefore, short channel effect and reduction in drain breakdown voltage can be effectively prevented. Further, the process is simplified compared to the conventional method of leaving an insulating film on the side wall of the gate 11L using vapor phase growth and anisotropic etching. Furthermore, since anisotropic dry etching is not used, no damage layer is formed on the substrate surface, and there is no deterioration of device characteristics due to polymer deposition.
なお、上記実施例ではｎ−型不純物領域１５を形成する
ためのリンイオン注入とｎ型不純物領域１６を形成する
ためのボロンイオン注入とを第２図（ａ）の工程でゲー
ト電極１４形成後に行なったが、これらのイオン注入は
同図（ｄ）の工程でタングステン膜１７を除去した後に
行なってもよい。In the above embodiment, phosphorus ion implantation to form the n-type impurity region 15 and boron ion implantation to form the n-type impurity region 16 are performed after the gate electrode 14 is formed in the process shown in FIG. 2(a). However, these ion implantations may be performed after the tungsten film 17 is removed in the step shown in FIG.
才だ、上記実施例では第２図（ｄ）の工程でタングステ
ン模１７はアニール工程時にゲート電極１４を構成する
多結晶シリコンと反応するので、ゲート電極１４の表面
にはタングステンシリサイド膜２３が形成される。この
ようにゲート電極１４の表面にタングステンシリサイド
膜２３を形成すれば、ゲート電極（配線）を低抵抗化す
ることができる。In the above embodiment, the tungsten pattern 17 reacts with the polycrystalline silicon constituting the gate electrode 14 during the annealing process in the process shown in FIG. 2(d), so a tungsten silicide film 23 is formed on the surface of the gate electrode 14. be done. By forming the tungsten silicide film 23 on the surface of the gate electrode 14 in this manner, the resistance of the gate electrode (wiring) can be reduced.
また、上記実施例では第２図（ｂ）の工程でゲート電極
１４の側壁だけでなく上面にもタングステン膜１７を選
択成長させたが、第２図（ａ）に対応する工程でゲート
に極１４上に絶縁膜（例えばＣＶＤ酸化膜）を形成して
おけば、第２図（ｂ＞に対応する工程ではゲート電極１
４の側壁にのみタングステン膜が選択成長する。この結
果、第４図に示すようにゲート電極１４上Ｏこは絶縁膜
、例えばＣＶＤ酸化膜２４が形成され、ゲート電極１４
の側壁には例えばタングステンシリサイド膜２５．２５
が形成された構造となる。Furthermore, in the above embodiment, the tungsten film 17 was selectively grown not only on the sidewalls of the gate electrode 14 but also on the top surface in the process shown in FIG. 2(b), but in the process corresponding to FIG. If an insulating film (for example, a CVD oxide film) is formed on the gate electrode 14, the process corresponding to FIG.
A tungsten film is selectively grown only on the sidewalls of 4. As a result, as shown in FIG. 4, an insulating film, for example, a CVD oxide film 24, is formed on the gate electrode 14.
For example, a tungsten silicide film 25.25 is placed on the side wall of the
The structure is formed.
更に、以上の説明ではゲート電極を多結晶シリコンで形
成し、被膜としてタングステン膜を用いた場合について
述べたが、ゲート電極は金属でもよいし、被膜はタング
ステン以外の金属、金属半導体化合物あるいは半導体で
もよい。また、本発明はｎチャネルのＭＯＳトランジス
タに限らず、ｐチャネルのものにも同様に適用できるこ
とは勿論である。Further, in the above explanation, the gate electrode is formed of polycrystalline silicon and a tungsten film is used as the coating, but the gate electrode may be made of metal, and the coating may be made of a metal other than tungsten, a metal-semiconductor compound, or a semiconductor. good. Furthermore, the present invention is of course applicable not only to n-channel MOS transistors but also to p-channel MOS transistors.
以上詳述した如く、本発明の半導体装置の製造方法にま
れば、素子の微細化に伴うショートチャネル効果等を有
効に防止し得る半導体装置を極めて制御性よく、しかも
簡便な工程で製造できるものである。As detailed above, by using the method for manufacturing a semiconductor device of the present invention, it is possible to manufacture a semiconductor device that can effectively prevent short channel effects caused by miniaturization of elements, with extremely good controllability, and in a simple process. It is.
第１図（ａ）〜（ｃ）は従来のＭＯＳトランジスタの製
造方法を示す断面図、第２図（ａ）〜（ｄ）は本発明の
実施例におけるＭＯ８Ｉ−ランジスタの製造方法を示す
断面図、第３図及び第４図はそれぞれ本発明の他の実施
例において製造されるＭＯ８ｈランジスタの断面図であ
る。
１１・・・ｐ型シリコン基板、１２・・・フィールド酸
化膜、１３・・・ゲート酸化膜、１４・・・ゲート電極
、１５・・・ｎ−型不純物領域、１６・・・ｎ型不純物
領域（ポケット領域）、１７・・・タングステン膜、１
８・・・ｎ型不純物領域、１９．２０・・・ソース。
ドレイン領域、２ノ・・・ＣＶＤ酸化膜、２２・・・ｈ
ｅ配線、２３．２５・・・タングステンシリサイド膜、
２４・・・ＣＶＤ酸化膜。FIGS. 1(a) to (c) are cross-sectional views showing a conventional method of manufacturing a MOS transistor, and FIGS. 2(a) to (d) are cross-sectional views showing a method of manufacturing an MO8I-transistor in an embodiment of the present invention. , 3 and 4 are cross-sectional views of MO8h transistors manufactured in other embodiments of the present invention, respectively. DESCRIPTION OF SYMBOLS 11... P-type silicon substrate, 12... Field oxide film, 13... Gate oxide film, 14... Gate electrode, 15... N- type impurity region, 16... N-type impurity region (pocket region), 17... tungsten film, 1
8...n-type impurity region, 19.20...source. Drain region, 2no...CVD oxide film, 22...h
e wiring, 23.25...tungsten silicide film,
24...CVD oxide film.
Claims (2)
成する工程と、該ゲート絶縁膜上にゲート電極を形成す
る工程と、該ゲート電極をマスクとして第１導電型の不
純物をイオン注入して第１導電型不純物領域を形成し、
第２導電型の不純物をイオン注入して浅い第２導電型の
低濃度不純物領域を形成する工程と、前記ゲート電極の
少なくとも側壁に被膜を選択成長させる工程と、前記ゲ
ート電極及び被成する工程とを具備したことを特徴とす
る半導体装置の製造方法。(1) A step of forming a gate insulating film on the semiconductor base surface of the first conductivity type, a step of forming a gate electrode on the gate insulating film, and a step of forming an impurity of the first conductivity type using the gate electrode as a mask. forming a first conductivity type impurity region by ion implantation;
A step of ion-implanting a second conductivity type impurity to form a shallow second conductivity type low concentration impurity region, a step of selectively growing a film on at least the sidewalls of the gate electrode, and a step of forming the gate electrode and the gate electrode. A method for manufacturing a semiconductor device, comprising:
ト電極の少なくとも側壁に高融点金属からなる被膜を選
択成長させた後、ゲート電極及び被膜をマスクとする第
２導電型の不純物のイオン注入を行ない、更に熱処理Ｏ
こよりゲート電極を構成する多結晶シリコンと被膜を構
成する高融点金属とを反応させてシリサイド化させるこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
の製造方法。(2) After forming a gate electrode with polycrystalline silicon and selectively growing a film made of a high-melting point metal on at least the sidewalls of the gate electrode, ion implantation of impurities of a second conductivity type is performed using the gate electrode and the film as a mask. and further heat treatment O
2. The method of manufacturing a semiconductor device according to claim 1, wherein the polycrystalline silicon constituting the gate electrode and the high melting point metal constituting the coating are reacted to form a silicide.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22097683A JPS60113472A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor device |
| US06/670,010 US4597824A (en) | 1983-11-11 | 1984-11-09 | Method of producing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22097683A JPS60113472A (en) | 1983-11-24 | 1983-11-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60113472A true JPS60113472A (en) | 1985-06-19 |
Family
ID=16759513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22097683A Pending JPS60113472A (en) | 1983-11-11 | 1983-11-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60113472A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61241974A (en) * | 1985-04-18 | 1986-10-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPS62122273A (en) * | 1985-11-22 | 1987-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS62224974A (en) * | 1986-03-27 | 1987-10-02 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63244884A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5543340A (en) * | 1993-12-28 | 1996-08-06 | Samsung Electronics Co., Ltd. | Method for manufacturing offset polysilicon thin-film transistor |
| US5677207A (en) * | 1995-10-17 | 1997-10-14 | Lg Electronics Inc. | Method for fabricating a thin film transistor using silicide layer |
| KR100317642B1 (en) * | 1999-05-27 | 2001-12-22 | 구본준, 론 위라하디락사 | Method for manufacturing a Thin Film Transistor using a metal plating |
| KR20030001942A (en) * | 2001-06-28 | 2003-01-08 | 동부전자 주식회사 | Semiconductor Device And Manufacturing Method For the Same |
-
1983
- 1983-11-24 JP JP22097683A patent/JPS60113472A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61241974A (en) * | 1985-04-18 | 1986-10-28 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
| JPH0519979B2 (en) * | 1985-04-18 | 1993-03-18 | Mitsubishi Electric Corp | |
| JPS62122273A (en) * | 1985-11-22 | 1987-06-03 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS62224974A (en) * | 1986-03-27 | 1987-10-02 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63244884A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5543340A (en) * | 1993-12-28 | 1996-08-06 | Samsung Electronics Co., Ltd. | Method for manufacturing offset polysilicon thin-film transistor |
| US5677207A (en) * | 1995-10-17 | 1997-10-14 | Lg Electronics Inc. | Method for fabricating a thin film transistor using silicide layer |
| KR100317642B1 (en) * | 1999-05-27 | 2001-12-22 | 구본준, 론 위라하디락사 | Method for manufacturing a Thin Film Transistor using a metal plating |
| KR20030001942A (en) * | 2001-06-28 | 2003-01-08 | 동부전자 주식회사 | Semiconductor Device And Manufacturing Method For the Same |
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