JP2904081B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device.
More particularly, the present invention relates to a method for forming a gate electrode structure of an insulated gate field effect transistor.

[0002]

2. Description of the Related Art A conventional LDD (Lightly Dop) is known.
In an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor) having a source / drain having a ed Drain structure, the gate is turned off (MO
A method for preventing the leakage current due to the formation of a surface inversion layer in the drain region below the gate electrode which occurs when the S transistor is in a non-conducting state and the resulting hand-to-hand tunneling of electrons between the valence band and the conduction band. As a technique for changing the work function of the gate electrode, Japanese Patent Laid-Open No. 26426/1995
No. 4 publication. In this method, a gate electrode covering a channel region of a MOS transistor via a gate insulating film and a gate electrode covering source / drain regions via a gate insulating film are formed of different kinds of conductor materials. Here, the work functions of these different kinds of conductive materials are selected so as to be different from each other.

[0003] The technique described in Japanese Patent Application Laid-Open No. 1-264264 will be described below with reference to the drawings.
FIG. 6 shows an n-channel M to which such a conventional technique is applied.
FIG. 3 is a cross-sectional view of an OS transistor.

As shown in FIG. 6, a gate insulating film 102 of a silicon oxide film having a thickness of about 10 nm is formed on a surface of a silicon substrate 101 having a P-type conductivity by a thermal oxidation method. Then, the first gate electrode 103 is formed of tungsten, molybdenum, or the like. Further, a second gate electrode 104 is formed on a side wall of the first gate electrode 103. Here, second gate electrode 104 is made of N-type polycrystalline silicon containing a phosphorus impurity.

Then, an n ⁻ diffusion region 105 forming a part of the source / drain is formed on the surface of the silicon substrate 101 under the second gate electrode 104 via the gate insulating film 102. Further, an n ⁺ diffusion region 106 is formed to form a source / drain region of the MOS transistor.

Here, for the second gate electrode 104, a conductor material whose work function is smaller than that of the first gate electrode 103 is selected.

In the above case, the first gate electrode 103 whose Fermi level is located in the middle region of the band gap of the silicon substrate covers the channel region of the MOS transistor, and the Fermi level is at a level close to the conduction band. The second
Gate electrode 104 covers the source / drain of the MOS transistor. That is, the work function of the second gate electrode 104 is set to be smaller than that of the first gate electrode 103. By doing so, the amount of band bending (hereinafter referred to as band bending) on the surface of n ⁻ diffusion region 105 when the gate of the MOS transistor is off is relaxed, and the above-described leakage current due to band tunneling is generated. Is reduced.

On the other hand, when the MOS transistor is of the p-channel type, the conductivity type of the source / drain diffusion region is P-type, so that the second gate electrode is of a conductivity type with respect to the first gate electrode. Is a conductor material having a large work function such as P-type polycrystalline silicon.

[0009]

However, when the semiconductor device is highly integrated and becomes, for example, a 256-Mbit DRAM, the thickness of the gate insulating film of the MOS transistor used becomes about 6 nm. Then, for example, when the gate is off in the case of an n-channel MOS transistor, that is, 0 V is applied to the gate electrode, and 3 V is applied to the drain.
When a voltage of about V is applied, the voltage of 3 V is applied to the surface of the source / drain diffusion region as it is. This voltage easily causes band bending on the surface of the diffusion region, and the tunnel current between the bands increases. This is due to the capacitance and band
This is because, when the capacitance due to the gate insulating film becomes larger than the capacitance of the bending portion, the voltage applied in series with these becomes almost consumed by band bending due to capacitance division.

As described above, when the MOS transistor is miniaturized, it is difficult to prevent such a band-to-band tunnel with the conventional technology.

An object of the present invention is to make it possible to suppress the band-to-band tunneling even when the MOS transistor is miniaturized.

[0012]

In an insulated gate field effect transistor relating to the present invention, in order to solve the problems], it is composed of a first gate electrode and second gate electrode having a gate electrode well-connected to each other, said first gate electrode Is located above the channel portion via a gate insulating film, the second gate electrode is located above the source / drain region via the insulating film, and the second gate electrode is located above the source / drain region. Is formed of a polycrystalline semiconductor film having a conductivity type opposite to the conductivity type.

Alternatively, there is a third gate electrode which covers the first gate electrode and the second gate electrode and is electrically connected to these gate electrodes.

Here, the polycrystalline semiconductor film is a polycrystalline silicon film or a polycrystalline silicon / germanium film. Further, the insulating film is a gate insulating film.

Here, the method of manufacturing a semiconductor device according to the present invention includes the steps of:
Forming a gate insulating film on the surface of the semiconductor substrate, forming a one-conductivity-type polycrystalline silicon film covering the gate insulating film, and depositing a protective insulating film on the polycrystalline silicon film to form a gate electrode. And processing the oblique ion-implanted impurities of the opposite conductivity type by using the patterned protective insulating film as a mask and overlapping the polycrystalline silicon film so as to overlap with the end of the patterned protective insulating film. Forming a region of the opposite conductivity type, processing the polycrystalline silicon film into a pattern shape of the gate electrode using the patterned protective insulating film as an etching mask, and forming the patterned protective insulating film and polycrystalline When a source / drain region is formed by introducing an impurity of one conductivity type into the surface of the semiconductor substrate using a silicon film as a mask, Said opposite conductivity type region and said source and drain regions so and a step to overlap through the gate insulating film.

Alternatively, a method of manufacturing a semiconductor device according to the present invention comprises the steps of:
Forming a gate insulating film on the surface of the semiconductor substrate, forming a one-conductivity-type polycrystalline silicon film covering the gate insulating film, and laminating the polycrystalline silicon film on the polycrystalline silicon film.
Forming a refractory metal silicide film, said refractory
Masks and steps, a protective insulating film and the refractory metal silicide film the patterning of processing and the refractory metal silicide film and the protective insulating film is deposited a protective insulating layer on the metal silicide layer upper to the pattern of the gate electrode And ion-implanted impurities of the opposite conductivity type and patterned
Forming a region of the opposite conductivity type in the polycrystalline silicon film so as to overlap with an end of the refractory metal silicide film; and forming the polycrystalline silicon film using the patterned protective insulating film as an etching mask. Processing a gate electrode into a pattern shape, and introducing one conductivity type impurity into the surface of the semiconductor substrate using the patterned protective insulating film, high melting point metal silicide film and polycrystalline silicon film as a mask, and forming source / drain regions. Forming and the step of overlapping the region of the opposite conductivity type and the source / drain region via the gate insulating film,
Will be included.

[0017]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of an n-channel MOS transistor for explaining a first embodiment of the present invention. As shown in FIG. 1, a gate insulating film 2 is formed on a surface of a silicon substrate 1 having a P-type conductivity. Then, a first gate electrode 3 and a second gate electrode 4 are formed on the gate insulating film 2. Here, the first gate electrode 3 is formed of a polycrystalline silicon film containing a phosphorus impurity. The second gate electrode is formed of a polycrystalline silicon film containing boron impurities. The content of the phosphorus impurity is about 10 ¹⁹ atoms / cm ³ , and the content of the boron impurity is about 10 ¹⁸ atoms / cm ³ . Here, an arsenic impurity may be used instead of the phosphorus impurity.

Then, n ⁺ diffusion regions 5 and 6 serving as the source and drain of the MOS transistor are formed as shown in FIG. That is, n ⁺ diffusion regions 5 and 6 and the gate electrode, that is, second gate electrode 4 overlap each other via gate insulating film 2. And
These n ⁺ diffusion regions 5 and 6 are formed so as not to overlap with first gate electrode 3. here,
The content of arsenic impurity in the n ⁺ diffusion region is 10 ²⁰ atoms / cm.
It is set to about ³ . Note that the source / drain diffusion region may have an LDD structure.

Next, a first embodiment of the present invention will be described specifically with reference to FIG. Here, FIG.
FIG. 15 is a cross-sectional view of a MOS transistor according to the embodiment in a manufacturing process order;

As shown in FIG. 2A, an element isolation region is formed of a field oxide film (not shown) on the surface of a P-type silicon substrate 1 to form an active region of the silicon substrate 1. A gate insulating film 2 is provided on the surface. Here, the gate insulating film 2 is a SiON insulating film formed by thermally nitriding a silicon oxide film having a thickness of about 6 nm formed by a known thermal oxidation method. Alternatively, the gate insulating film 2 is a SiON insulating film formed by thermal oxidation in an atmosphere gas containing nitrogen such as nitrous oxide.

Next, an N-type polycrystalline silicon film 3 'covering the gate insulating film 2 is deposited by a known chemical vapor deposition (CVD) method. Here, the thickness of this N-type polycrystalline silicon film 3 'is set to about 200 nm. The N-type polycrystalline silicon film 3 ′ contains a phosphorus impurity at a concentration of about 1 × 10 ¹⁹ atoms / cm ³ .

Next, a protective insulating film 7 having a pattern of a gate electrode of a MOS transistor is provided on the surface of the N-type polycrystalline silicon film 3 '. Here, the protective insulating film 7 is a silicon oxide film formed by a CVD method, and its thickness is set to about 300 nm. The pattern size is the size of the gate electrode and is 0.3
It is set to about μm.

Next, as shown in FIG. 2B, a sidewall insulating film 8 is formed on the side wall of the protective insulating film 7. Here, the sidewall insulating film 8 has a thickness of 100 nm.
Of silicon nitride film. The sidewall insulating film 8 is formed by a CVD method to a thickness of 120 n.
An about m silicon nitride film is deposited, and subsequently, the entire surface of the silicon nitride film is etched by an anisotropic reactive ion etching (RIE) method.

Next, as shown in FIG. 2C, boron ions 9 are implanted. Here, the boron ions 9 are obliquely implanted, and the inclination angle is set to about 45 degrees. The implantation energy of this ion implantation is 50 to 100 keV, and the dose is 3 × 10 ¹⁴ ions /
Each is set to about cm ² . The range of boron ions in this ion implantation is about 200 nm, and the ions reach the vicinity of the gate insulating film 2. And
Further heat treatment is applied. Thus, a P-type polycrystalline silicon film 4 'is formed.

This P-type polycrystalline silicon film 4 'has a phosphorus impurity of 1 × 10 ¹⁹ atoms / cm ³ and 1.5 × 1
0 ¹⁹ atoms / cm ³ of boron impurities are mixed, and apparently 5 × 10 ¹⁸ atoms / cm ³ of P-type impurities are contained.

Next, the sidewall insulating film 8 is selectively removed by etching. The etch in g is carried out in a chemical solution such as a hot phosphoric acid. Then, using the protective insulating film 7 as an etching mask, the above-described N-type polycrystalline silicon film 3 'is formed.
Then, P-type polycrystalline silicon film 4 'is dry-etched by RIE.

Thus, as shown in FIG. 2D, the first gate electrode 3 is formed in the region of the N-type polycrystalline silicon film 3 'described above, and the P-type polycrystalline silicon film 4' The second gate electrode 4 is formed in the region.

Next, arsenic impurity ions are implanted into the entire surface and heat treatment is performed to form n ⁺ diffusion regions 5 and 6. Here, n ⁺ diffusion regions 5 and 6 overlap with second gate electrode 4 via gate insulating film 2.

Finally, the protective insulating film 7 is removed, and the MOS transistor described with reference to FIG. 1 is completed.

Next, the second embodiment of the present invention will be described with reference to FIGS.
An embodiment will be described. FIG. 3 is a cross-sectional view of an n-channel MOS transistor similar to that described in the first embodiment.

As shown in FIG. 3, a gate insulating film 2 is formed on the surface of a silicon substrate 1 having a P-type conductivity. Then, a first gate electrode 3 and a second gate electrode 4 are formed on the gate insulating film 2. Here, the first gate electrode 3 is formed of a polycrystalline silicon film containing a phosphorus impurity. The second gate electrode is formed of a polycrystalline silicon film containing boron impurities. In this case, the second gate electrode 4 is formed along the side wall of the first gate electrode 3. The content of the phosphorus impurity is about 102 ⁰ atoms / cm ^3, the content of boric impurities is about 10 ¹⁸ atoms / cm ^3.

Then, a third gate electrode 10 electrically connected to the first gate electrode 3 and the second gate electrode 4 is formed. Here, the third gate electrode 10 is formed of a refractory metal silicide film such as tungsten silicide or titanium silicide.

Then, n ⁺ diffusion regions 5 and 6 serving as the source and drain of the MOS transistor are formed as described in the first embodiment. That is, n ⁺
The diffusion regions 5 and 6 and the gate electrode, that is, the second gate electrode 4 overlap each other via the gate insulating film 2. The n ⁺ diffusion regions 5 and 6 are connected to the first
Is formed so as not to overlap with the gate electrode 3. Here, the content of the arsenic impurity in the n ⁺ diffusion region is set to about 10 ²⁰ atoms / cm ³ .

[0034] Next, a second embodiment of the present invention based on concrete Fig. Here, FIG. 4, the second
FIG. 15 is a cross-sectional view of a MOS transistor according to the embodiment in a manufacturing process order;

As shown in FIG. 4A, an element isolation region is formed of a field oxide film on the surface of a P-type silicon substrate 1 in the same manner as described in the first embodiment. A gate insulating film 2 is provided on a surface of an active region of a silicon substrate 1. Here, the gate insulating film 2 is a SiON insulating film having a thickness of about 6 nm.

Next, an N-type polycrystalline silicon film 3 'covering the gate insulating film 2 is deposited by a CVD method. Here, the thickness of this N-type polycrystalline silicon film 3 'is set to about 150 nm. The N-type polycrystalline silicon film 3 ′ contains a phosphorus impurity at a concentration of about 1 × 10 ²⁰ atoms / cm ³ .

Next, on the surface of the N-type polycrystalline silicon film 3 ', a third gate electrode 10 having a pattern of a gate electrode of a MOS transistor and a protective insulating film 7 are provided in a laminated manner. Here, the third gate electrode 10 is a titanium silicide layer, and the protective insulating film 7 is a silicon oxide film formed by a CVD method. The thickness of the third gate electrode 10 is set to 150 nm, and the thickness of the protective insulating film is set to about 300 nm. Also,
This pattern dimension is set to about 0.3 μm.

Next, boron difluoride ions 11 are implanted to form a boron impurity implanted layer 12. Here, the implantation energy of this ion implantation is 50 keV, and the dose is 2 × 10 ¹⁵ ions / cm ² .
Then, a heat treatment at a temperature of about 800 ° C. is performed, and FIG.
A P-type polycrystalline silicon film 4 'as shown in FIG. In this case, the dimension of the overlapping region between the P-type polycrystalline silicon film 4 ′ and the third gate electrode 10 is 0.1 μm. The apparent amount of the boron impurity after mixing the phosphorus impurity and the boron impurity is 5 × 10
It is set to be ¹⁸ atoms / cm ³ .

Next, as shown in FIG. 4C, the P-type polycrystalline silicon film 4 'is dry-etched by RIE using the protective insulating film 7 and the third gate electrode 10 as an etching mask. Thus, the first gate electrode 3 is formed in the region of the N-type polycrystalline silicon film 3 'described above, and the second gate electrode 4 is formed in the region of the P-type polycrystalline silicon film 4'. become.

Next, arsenic impurity ions are implanted into the entire surface and heat treatment is performed to form n ⁺ diffusion regions 5 and 6. Finally, the protective insulating film 7 is removed, and the MOS transistor having the structure described with reference to FIG. 3 is completed.

Next, the effect of the present invention will be described in detail with reference to FIG. FIG. 5 (a) is formed by the method of the present invention.
Is a schematic cross-sectional view where an enlarged MOS transistor with, FIG. 5 (b) shows the energy band structure between A-B that describes in Figure 5 (a). In addition, FIG.
This is a similar energy band structure in the case of a conventional MOS transistor.

As shown in FIG. 5A, a gate insulating film 2, a first gate electrode 3, and a second gate electrode 4, n of an n-channel MOS transistor are formed on a surface of a silicon substrate 1 having a P-type conductivity. ⁺ Diffusion regions 5 and 6 are formed. Here, n ⁺ diffusion region 5 becomes a source region, and n ⁺ diffusion region 6 becomes a drain region.

Here, the first gate electrode 3 and the second gate electrode 4 of such a MOS transistor, the n ⁺ diffusion region 5 and the silicon substrate 1 are set to the ground potential, and the n ⁺ diffusion region 6 has a voltage of about 3 V. A case where a positive voltage is applied will be described. This case is the above-mentioned MOS transistor off state.

As described above, when a voltage is applied to the MOS transistor, the voltage between the first gate electrode 3 and the second gate electrode 4 and the n ⁺ diffusion region 6 as the drain region is increased.
A voltage of about V is applied. Therefore, a depletion region 4a is formed in second gate electrode 4 made of P-type polycrystalline silicon. Further, a PN junction formed between the first gate electrode 3 formed of N-type polycrystalline silicon and the second gate electrode 4 is applied in a forward direction. In this way, most of the voltage between the first gate electrode 3 and the n ⁺ diffusion region 6 is applied to the depletion region 4a.

This situation will be described with reference to FIG. FIG.
As shown in (b), the energy band 24 of the second gate electrode 4 is reduced in electron energy in the depletion region 4a to become the energy band 24a. Then, the energy band 22 of the gate insulating film 2 slightly lowers to the right. Then, n ⁺ energy band 26a slight right edge of the n ⁺ diffusion region 6 surface by the band bending on the surface of the diffusion region 6 is formed. Then, an energy band 26 of the n ⁺ diffusion region 6 and an energy band 21 of the silicon substrate 1 having high electron energy are formed.

As described above, the gate insulating film 2 is made thinner with the miniaturization of the MOS transistor, and the impurity in the n ⁺ diffusion region 6 is increased in concentration. And the gate insulating film 2
And the capacitance formed in the band-bending region increases. Therefore, the depletion region 4a
Are relatively small, and if they are connected in series, a voltage drop occurs in the depletion region 4a. Then, the bending of the energy band 24a in the depletion region described above increases, and the amount of band bending decreases.

In this manner, the film was formed by the method of the present invention .
In the MOS transistor , the above-mentioned band bending amount is reduced, and the band-to-band tunnel phenomenon of electrons is prevented.

On the other hand, for comparison, in the case of the prior art
Will be described with reference to FIG. In this case, the gate electrode
Since no depletion region is formed as in the present invention, the gate
The pole energy band 24 is not bent. For this,
As shown in FIG.⁺ Energy of diffusion surface 6
The change of the band 26a becomes large. That is, the band
-The bending amount is increased. And this
From electron conduction band to valence band in band bending part
The band-to-band tunnel phenomenon becomes remarkable.

In the above embodiment, the n-channel MOS
Although the case of a transistor has been described, it should be noted that a p-channel MOS transistor can be similarly formed only by reversing its conductivity type.

Although a polycrystalline silicon film is used as a first gate electrode material of a MOS transistor,
In addition, a refractory metal or a silicide film thereof can be similarly formed. Further, a polycrystalline silicon-germanium film may be used as the second gate electrode material.

In the MOS transistor formed according to the present invention, the second gate electrode and the source / drain region may overlap with each other via a gate insulating film, or the insulating film may be thicker than other gate insulating films. It may overlap through a membrane.

Here, the second gate electrode and the channel region are formed so as not to overlap. This is because the presence of such an overlap increases the threshold voltage of the MOS transistor and deviates from the set value.

[0053]

In an insulated gate field effect transistor formed in the method of the present invention, is composed of a first gate electrode and second gate electrode having a gate electrode well-connected to each other, said first gate The electrode is present on a channel portion via a gate insulating film, the second gate electrode is present on a source / drain region via an insulating film, and the second gate electrode is provided on the source / drain region. The region is formed of a polycrystalline semiconductor film having a conductivity type opposite to that of the region.

Here, when a voltage is applied between the gate electrode and the drain region so that the insulated gate field effect transistor is turned off, a depletion region is formed in the second gate electrode. Most of the voltage is applied.

Therefore, as described above, the band-to-band tunnel phenomenon caused by band bending in the drain region is eliminated. Then, the leak current in the drain region is greatly reduced.

Thus, miniaturization of the insulated gate field effect transistor and high density or high integration of the semiconductor device are facilitated.

[Brief description of the drawings]

M for explaining the first embodiment of the invention; FIG
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 2 is a sectional view of the MOSFET in the order of the manufacturing process.

M for explaining the second embodiment of the present invention; FIG
FIG. 3 is a cross-sectional view of an OSFET.

FIG. 4 is a sectional view in the order of the manufacturing steps of the MOSFET.

FIG. 5 is a cross-sectional view and a band diagram for explaining an effect of the present invention.

FIG. 6 is a cross-sectional view of a MOSFET for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 101 Silicon substrate 2, 102 Gate insulating film 3, 103 First gate electrode 3 'N-type polycrystalline silicon film 4, 104 Second gate electrode 4a Depletion region 4' P-type polycrystalline silicon film 5, 6, 106 n ⁺ diffusion region 7 protective insulating film 8 side wall insulating film 9 boron ion 10 third gate electrode 11 boron difluoride ion 12 boron impurity implanted layer 21, 22, 24, 24a, 26, 26a energy band 105 n ⁻ Diffusion area

Claims (2)

(57) [Claims] In forming an insulated gate field effect transistor , a gate insulating film is formed on a surface of a semiconductor substrate.
Process and one-conductivity-type polycrystal covering the gate insulating film
Forming a silicon film; and forming a silicon film on the polycrystalline silicon film.
Deposit a protective insulating film on the gate to form a gate electrode pattern
Processing and masking the patterned protective insulating film.
In the polycrystalline silicon film to form impurities of the opposite conductivity type.
Edge of protective insulating film patterned by oblique ion implantation
Area of the opposite conductivity type of the polycrystalline silicon film overlapping the part
Forming a region and the patterned protective insulating film
Is used as an etching mask and the polycrystalline silicon film is
Processing the gate electrode into a pattern shape;
Turned protective insulating film and polycrystalline silicon film
The surface of the semiconductor substrate with impurities of one conductivity type.
To form source / drain regions and
A gate region between the source region and the source / drain region;
Overlapping through an insulating film.
A method for manufacturing a semiconductor device, comprising: 2. The formation of an insulated gate field effect transistor.
Forming a gate insulating film on the surface of the semiconductor substrate
Process and one-conductivity-type polycrystal covering the gate insulating film
Forming a silicon film; and forming a silicon film on the polycrystalline silicon film.
Forming a refractory metal silicide film by laminating
A protective insulating film is deposited on the refractory metal silicide film.
The protective insulating film and the refractory metal silicide film.
Processing into a pattern shape of the gate electrode;
Protected insulating film and refractory metal silicide film
In the polycrystalline silicon film to form impurities of the opposite conductivity type.
Ion-implanted and patterned high melting point metal silicide
Of polycrystalline silicon film overlapping the edge of doped film
Forming a conductive region; and storing the patterned region.
The polycrystalline silicon using the protective insulating film as an etching mask.
Forming a gate electrode film into a pattern shape of the gate electrode
And the protective insulating film patterned
Using the side film and the polycrystalline silicon film as masks,
Introduce one conductivity type impurities into the surface of
Forming a rain region and the region of the opposite conductivity type;
The source / drain regions are connected via the gate insulating film.
And a step of overlapping.
Manufacturing method of body device .