JPH06267972A - Manufacture of mos transistor - Google Patents

Abstract

PURPOSE:To enable a high withstanding voltage and a microstructure to be provided by implanting ions with a mask film for oxidation and ion implantation as a mask to form a low concentration region, oxidizing the side wall of a polysilicon layer at a specified temperature, and implating ions with the oxide film as a mask to form a high concentration region, thereby to reduce the electric field concentration on the gate end. CONSTITUTION:On a silicon substrate 1, a gate oxide film 2 is formed, and on the surface thereof, a polysilicon layer 3 is deposited. The polysilicon layer 3 is undoped undoped or doped with an impurity to deposit a SiN film 4 on the polysilicon layer 3 as a mask film for oxidation and ion implantation. Ions are implanted with the SiN film 4 as a mask to form a low concentration source 10 and a low concentration drain 5. Then, the side wall of the polysilicon layer 3 is oxidized at 700 deg.C to 1200 deg.C, and with the oxide film 6 as a mask ions are implanted to form a high concentration source 11 and a high concentration drain 7. As a result, the low concentration drain 5 can be formed in self alignment in the drain end, and a fine gate can thus be formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS transistor, which constitutes a semiconductor integrated circuit, and in particular, one which requires a high breakdown voltage.

[0002]

2. Description of the Related Art FIG. 3 shows a structure of a normal MOS transistor and a conventional MOS transistor in which electric field concentration is relaxed for higher breakdown voltage. In the figure, 1 is a silicon substrate,
2 is a gate oxide film, 3 is a polysilicon gate, 5 is a low concentration drain, 7 is a high concentration drain, 8 is a side spacer, and 9 is an LDD (Lightly doped drain).
in).

FIG. 3A shows a normal MOS transistor. FIG. 3B shows a MOS transistor having an offset gate structure, in which a low concentration drain 5 is provided at the drain end to relax electric field concentration at the gate end, and FIG. 3C shows the gate oxide film 2 at the drain end. FIG. 3 shows a MOS transistor that is thickened to reduce electric field concentration at the gate end.
(D) shows a MOS transistor in which a LDD 9 is provided in a self-aligned manner and a side spacer 8 is provided on the side wall of the polysilicon gate 3 to form a high-concentration drain.

[0004]

FIG. 3B of the prior art,
The MOS transistor shown in (c) has a problem that mask alignment is required to form an offset structure, and miniaturization is limited due to this mask alignment. The conventional MOS transistor shown in FIG. 3D can be formed in a self-aligned manner, but the dimension of the LDD 9 in the lateral direction is substantially equal to the dimension of the side spacer 8 in the lateral direction, so that the application is relatively low voltage. However, there is a problem that the electric field concentration at the drain end becomes large with the miniaturization, and the short channel effect appears. The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of forming a low-concentration drain at a drain end in a self-aligning manner to enable a high breakdown voltage and miniaturization.

[0005]

According to the manufacturing method of the present invention, a polysilicon layer is deposited on a gate oxide film formed on the surface of an element forming region of a silicon substrate, and the polysilicon layer is non-doped or doped with impurities. Alternatively, a first polysilicon layer is deposited on the gate oxide film and the first polysilicon layer is deposited.
Of phosphorus or arsenic in the polysilicon layer of 5 × 10 ²⁰ / cm ³
Impurities are implanted as described above, a second polysilicon layer is deposited on the first polysilicon layer, and the second polysilicon layer is non-doped or has an impurity concentration of 1 × 10 ²⁰ / cm ³ kept below, and further depositing a film of SiN or the like to be used as oxidation and ion implantation mask the polysilicon layer or two-layer polysilicon layer of the single layer performs patterning of the gate region, was patterned SiN Ion implantation is performed using a film or the like as a mask to form a low-concentration region, and sidewall oxidation of the polysilicon layer is performed.
This is a method characterized in that a high concentration drain is formed by performing ion implantation using an oxide film formed on the side wall of the polysilicon layer whose volume is expanded by oxidation as a mask.

[0006]

Embodiment 1 FIG. 1 is one of the embodiments of the present invention. After forming a field oxide film on the silicon substrate 1, a gate oxide film 2 is formed on the surface of the element formation region [FIG. 1 (a)].
Next, a polysilicon layer 3 is deposited on the surface by 1000 to 3000 liters. This polysilicon layer may be non-doped or may be doped with impurities, but is implanted at about 5 × 10 ²⁰ / cm ³ to reduce the gate resistance [FIG.
(B)]. An SiN film 4 as a mask film for oxidation and ion implantation is deposited thereon by 1000 Å [FIG. 1 (c)]. At this time, a structure may be adopted in which a SiO ₂ film is formed on the polysilicon layer 3 and a SiN film is formed thereon. Subsequently, the polysilicon layer 3 in the gate region is etched with SF ₆ + C ₂ F ₆ Cl-based gas [FIG. 1 (d)], and boron or boron fluoride is used as a mask with the patterned SiN film as a mask.
Implantation is performed under the conditions of ˜100 keV and 2˜8 × 10 ¹³ / cm ² to form the low concentration source 10 and the low concentration drain 5 [FIG. 1 (e)]. At this time, although normal ion implantation may be used, rotary ion implantation does not require drive-in in a later step, and the low-concentration source and drain can overlap the polysilicon gate.
Further, by performing the implantation from the drain side toward the source side by oblique implantation, the lateral dimension of the low concentration source can be made smaller than the lateral dimension of the low concentration drain. Next, wet oxidation is performed at 900 ° C. for 20 minutes [FIG. 1
(F)]. The oxide film thickness formed at this time is about 2400Å. Subsequently, the SiN film is removed, and drive-in is performed in a N ₂ atmosphere at 900 to 1100 ° C. so that the low-concentration source 10 and the low-concentration drain 5 overlap the polysilicon gate 3 [FIG. 1 (g)]. Next, using the oxide film 6 formed by the previous oxidation as a mask, boron or boron fluoride is ion-implanted at 30 to 80 keV and 1 to 8 × 10 ¹⁵ / cm ² to form the high concentration source 11 and the high concentration drain 7. It is formed [FIG. 1 (h)]. After that, an interlayer insulating film is formed by a normal IC manufacturing process, and an electrode and a protective film are formed. With this manufacturing method, it is possible to form a MOS transistor having a withstand voltage higher than that of a normal MOS transistor by about 5V.

[0007]

Second Embodiment FIG. 2 shows another embodiment of the present invention. After forming the field oxide film on the silicon substrate 1, the gate oxide film 2 is formed on the surface of the element formation region [FIG. 2 (a)], and then the first polysilicon layer 3a is formed on the surface of 1000 to 3000.
Å Accumulate. The first polysilicon layer 3a is doped with phosphorus or arsenic at 5 × 10 ²⁰ / cm ³ [FIG. 2 (b)], and the second polysilicon layer 3b is deposited on the first polysilicon layer 3a at 1000 to 3000.
Å Accumulate. This second polysilicon layer is non-doped or has a concentration of 1 × 10 ²⁰ / cm ³ even if impurities are implanted.
It suppresses below (FIG.2 (c)). An SiN film 4 is deposited thereon as a 1000 Å mask film for oxidation and ion implantation [FIG. 2 (d)]. At this time, a structure in which a SiO ₂ film is formed on the second polysilicon layer 3b and a SiN film is formed thereon may be adopted. Then, the polysilicon layer in the gate region is etched with SF ₆ + C ₂ F ₆ Cl-based gas [FIG.
(E)], with the patterned SiN film as a mask, boron or boron fluoride is added at 30 to 100 keV, 2 to 8 ×
Low-concentration source 1 is implanted under the condition of 10 ¹³ / cm ^2.
0, the low concentration drain 5 is formed [FIG. 2 (f)]. At this time, although normal ion implantation may be used, rotary ion implantation does not require drive-in in a later step, and the low-concentration source and drain can overlap the polysilicon gate. Further, by performing the implantation from the drain side toward the source side by oblique implantation, the lateral dimension of the low concentration source can be made smaller than the lateral dimension of the low concentration drain. Next, wet oxidation is performed at 900 ° C. for 20 minutes [FIG. 2 (g)]. Polysilicon layer 3
Sidewall oxidation of a and 3b has a phosphorus or arsenic impurity concentration of 5 ×
The thickness of the oxide film formed depends on the impurity concentration between 10 ²⁰ / cm ^{3 and} above and 1 × 10 ²⁰ / cm ^{3 and} below, and the oxidation formed on the side wall of the first polysilicon layer 3a. Since the thickness of the film is thicker than the thickness of the oxide film formed on the side wall of the second polysilicon layer 3b, the second polysilicon layer 3b is formed on the side wall of the first polysilicon layer 3a.
An oxide film 6 which is twice or more thicker than the oxide film formed on the side wall of is formed [FIG. 2 (h)]. Under the above oxidizing conditions, the first polysilicon layer 3a is 2400Å the second polysilicon layer 3a.
For b, an oxide film thickness of 600Å can be obtained. The thickness ratio of the oxide film depending on the impurity concentration of phosphorus or arsenic is 700
The first polysilicon layer 3a is formed by wet oxidation up to 900 ° C.
Is 4 to 5 times thicker than the second polysilicon layer 3b.
Wet oxidation at 0 to 1200 ℃ 3 to 4 times, 900 to 1
It is approximately doubled at 200 ° C. dry oxidation, and this concentration dependency is remarkable in wet oxidation at 700 to 900 ° C. However, in the manufacturing method of the present invention, if the ratio of the oxide film thickness to be formed is twice or more, the effect of increasing the withstand voltage is sufficiently exhibited, and therefore any oxidation method can be applied. Then Si
The N film 4 is removed, and drive-in is performed in an N ₂ atmosphere at 900 to 1100 ° C. so that the low concentration drain 5 overlaps the first polysilicon layer 3a of the T-shaped structure gate [FIG. 2 (h)]. ]. The overlapping structure is superior in terms of reliability. If the rotary ion implantation is used in the low concentration drain and low concentration source forming process, this drive-in is not necessary. Next, using the oxide film 6 formed by the previous oxidation as a mask, boron or boron fluoride is added at 30 to 80 keV, 1 to 8 × 10 ¹⁵ /
Ion implantation is performed at a cm ² to form a high concentration source 11 and a high concentration drain 7 [FIG. 2 (i)]. After that, an interlayer insulating film and a protective film are formed by a normal IC manufacturing process. Since phosphorus or arsenic diffuses from the first polysilicon layer 3a into the second polysilicon layer 3b by the heat treatment after the step shown in FIG. 2H, a good ohmic contact is obtained. With this manufacturing method, it is possible to form a MOS transistor having a breakdown voltage higher than that of a normal MOS transistor by 10 V or more. Further, since the mask alignment is unnecessary, the gate length can be easily shortened, and a 0.1 μm gate can be formed.

[0009]

As described above, according to the present invention, since a low concentration drain can be formed at the drain end in a self-aligning manner, mask alignment is eliminated and a fine gate can be formed.
In addition, a thick oxide film is formed between the polysilicon gate and the low concentration drain in a self-aligned manner to alleviate the electric field concentration at the gate end to increase the withstand voltage and suppress the generation of hot electrons, and further downsize the high withstand voltage structure MOS transistor. can do. Also, by obliquely implanting when forming the low concentration drain, the lateral dimension of the low concentration region on the source side can be made smaller than that of the low concentration region on the drain side, and an offset gate structure can be formed and the source resistance can be reduced. There is also an effect that it can be reduced.

[Brief description of drawings]

FIG. 1 is an explanatory view showing a manufacturing method of the present invention.

FIG. 2 is an explanatory view showing another manufacturing method of the present invention.

FIG. 3 is an explanatory diagram showing a structure of a normal MOS transistor and a conventional MOS transistor in which electric field concentration is relaxed for high breakdown voltage.

[Explanation of symbols]

 1 Silicon Substrate 2 Gate Oxide Film 3 Polysilicon Layer 3a First Polysilicon Layer 3b Second Polysilicon Layer 4 SiN Film 5 Low Concentration Drain 6 Oxide Film 7 High Concentration Drain

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[Procedure amendment]

[Submission date] July 27, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 3]

Claims (2)

[Claims] 1. A polysilicon layer is deposited on a gate oxide film formed on the surface of an element formation region of a silicon substrate, and the polysilicon layer is undoped or doped with impurities, and the polysilicon layer is oxidized and ionized. An implantation mask film is deposited, the gate region is patterned, ions are implanted using the oxidation and ion implantation mask film as a mask to form a low concentration region, and the sidewall of the polysilicon layer is oxidized at 700 to 1200 ° C. A method of manufacturing a MOS transistor, characterized in that a high concentration region is formed by ion-implanting the oxide film as a mask. 2. A first polysilicon layer is deposited on a gate oxide film formed on the surface of an element formation region of a silicon substrate, and phosphorus or arsenic is added to the first polysilicon layer in an amount of 5 × 10 5.
Impurities are implanted to ²⁰ / cm ³ or more and a second polysilicon layer is deposited on the first polysilicon layer, and the second polysilicon layer is undoped or 1 × 10 ²⁰ / cm ³
Then, impurities are implanted, an oxidation and ion implantation mask film is deposited on the second polysilicon layer, a gate region is patterned, and the oxidation and ion implantation mask film is ion-implanted as a mask to reduce the concentration. Area to form 700-
The sidewalls of the first and second polysilicon layers are oxidized at 1200 ° C. so that the oxide film thickness of the first polysilicon layer is twice or more the oxide film thickness of the second polysilicon layer. And a high-concentration region is formed by ion implantation using the oxide film of the first polysilicon layer as a mask.
Manufacturing method of S-transistor.