JPH11307774A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the inside of furnace from being contaminated with tungsten and titanium, etc., which are generated from a silicide layer in a thermal oxidation process, for allowing a gate oxide film near both ends of a polycide gate to be thickened for improved transistor characteristics. SOLUTION: A polycide gate 100 is subjected to thermal oxidation, while being covered with a chemical vapor-phase growth(CVD) oxide film 9 so that a gate oxide film 3 near both end parts of the polycide gate 100 is made thicker. After that, the CVD oxide film 9 is anisotropically-etched to form a sidewall oxide film 9a, with a cap oxide film formed at a polycide gate, thermal oxidation process may be performed after the sidewall oxide film has been formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a metal silicide layer formed on a polycrystalline (poly) silicon layer.
The present invention relates to a semiconductor device provided with a gate electrode wiring having a so-called polycide structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the concentration of an electric field at the end of a gate electrode of a MOS transistor, a thermal oxidation process is performed after patterning of a gate electrode wiring to form a thick gate oxide film near the end of the gate electrode. Is being done.

On the other hand, in recent years, a so-called polycide wiring in which a refractory metal silicide layer such as tungsten (W) or titanium (Ti) is laminated on a polysilicon layer has been used for a gate electrode wiring of a MOS transistor. Are increasing.

[0004]

However, if a thermal oxidation treatment is performed with the metal silicide layer bare after patterning the gate electrode wiring using the polycide wiring as described above, the W generated from the metal silicide layer will be reduced. And Ti
There is a problem that the inside of the furnace is contaminated by such metal vapor.

Although the purpose is different, as a conventional technique for performing a thermal oxidation treatment after forming a gate electrode by a polycide wiring, for example, JP-A-5-190535, JP-A-8-116055 and JP-A-8-16055 There is one described in 274320.

Japanese Patent Application Laid-Open No. Hei 5-190535 discloses a technique for preventing a metal silicide in a metal silicide layer from being abnormally oxidized when a CVD (chemical vapor deposition) oxide film is formed on a polycide gate. The surface of the polycide gate is previously thermally oxidized by an RTO (rapid thermal oxidation) method.

In Japanese Patent Application Laid-Open No. Hei 8-116055, in order to prevent a gate electrode end portion from jumping up in an oxidation step after forming a polycide gate, the polycide gate is left on a gate oxide film on both sides thereof. The deposited polysilicon layer is thermally oxidized simultaneously with the thermal oxidation of the polycide gate surface.

In Japanese Patent Application Laid-Open No. Hei 8-274320, for the purpose of recovering etching damage of a gate oxide film,
The gate oxide film on the source / drain formation scheduled region is thermally oxidized simultaneously with the polycide gate surface.

However, in each of the above publications, there is a problem that the furnace is contaminated because the thermal oxidation treatment is performed in a state where the metal silicide layer is exposed to the outside.

Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, in which the furnace inside is not contaminated by metal vapor from a metal silicide layer when a gate electrode is formed by polycide wiring and thermal oxidation is performed. It is to provide.

[0011]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate oxide film on a surface of an element forming region of a semiconductor substrate of a first conductivity type; A step of forming a laminated film composed of a polycrystalline silicon layer and a metal silicide layer thereon, a step of patterning the laminated film into a shape of a gate electrode wiring, on the film, Introducing a second conductivity type impurity into a surface region of the semiconductor substrate;
Forming a silicon oxide film on the entire surface so as to cover the gate electrode wiring, and performing heat treatment to increase the thickness of the gate oxide film near both ends of the gate electrode wiring covered with the silicon oxide film And

In one embodiment of the present invention, after the heat treatment, the silicon oxide film is anisotropically etched to form a sidewall oxide film mainly composed of the silicon oxide film on a side surface of the gate electrode wiring. And the relatively thin second
After the entire surface is covered with the silicon oxide film, a step of introducing a second conductivity type impurity into the surface region of the semiconductor substrate outside the sidewall oxide film of the gate electrode wiring at a relatively high concentration.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a gate oxide film on a surface of an element forming region of a semiconductor substrate of a first conductivity type; Forming a laminated film including a crystalline silicon layer, a metal silicide layer thereon, and a cap insulating layer thereon, processing the laminated film into a gate electrode wiring pattern, and forming both sides of the gate electrode wiring pattern. Introducing a second conductivity type impurity into the surface region of the semiconductor substrate at a relatively low concentration, forming a silicon oxide film over the entire surface so as to cover the gate electrode wiring pattern, Forming a sidewall oxide film mainly composed of the silicon oxide film on the side surface of the gate electrode wiring pattern, The thickness of the gate oxide film near both ends of the gate electrode wiring pattern covered with the silicon film is increased, and a thermal oxide film is formed on the surface of the semiconductor substrate outside the sidewall oxide film of the gate electrode wiring pattern. Forming, and introducing a second conductivity type impurity to the surface region of the semiconductor substrate outside the sidewall oxide film of the gate electrode wiring pattern at a relatively high concentration.

In one embodiment of the present invention, the cap insulating layer is a silicon oxide layer.

Further, the semiconductor device of the present invention has a gate electrode wiring constituted by a laminated film composed of a polycrystalline silicon layer and a metal silicide layer thereon, and a gate oxide near both ends of the gate electrode wiring. The film is formed to be thicker than the gate oxide film at the center of the gate electrode wiring, and the thickness of the thick portion of the gate oxide film is 200 to 3
00 °.

In one embodiment of the present invention, the thick film portion is formed in a region having a width of 0.03 to 0.1 μm near both ends of the gate electrode wiring.

In one aspect of the present invention, a sidewall oxide film having a thickness of 2 to 4 times the thickness of the thick film portion is formed on a side surface of the gate electrode wiring.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

[First Embodiment] First, a first embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 1A, for example,
In the surface region of the p-type silicon semiconductor substrate 1, for example, L
The field oxide film 2 is selectively formed by the OCOS method to perform element isolation. Next, the field oxide film 2
Is thermally oxidized in, for example, a high-temperature oxygen (O ₂ ) atmosphere to form a gate oxide film 3 having a thickness of about 100 to 150 °.

As the gate insulating film of the MOS transistor, an ONO film or an oxynitride film, which is a composite laminated film of a nitride film and an oxide film, can be used.
In the present invention, these are referred to as “gate oxide film” in a sense including them.

Next, n, such as phosphorus (P), is
A polysilicon layer 4 doped with a type impurity, and a silicide layer 5 with a high melting point metal such as tungsten (W) or titanium (Ti) are sequentially laminated thereon, and the laminated film is subjected to photolithography and dry etching. To form the gate electrode wiring 100.

Next, as shown in FIG. 1B, using the gate electrode wiring 100 and the field oxide film 2 as a mask, for example, phosphorus (P) is
A dose amount of about × 10 ^{13 to} 5 × 10 ¹³ / cm ^2, 60 k
Ions are implanted into the entire surface at an implantation energy of about eV to form an n-type low-concentration ion implantation layer 8a in the surface region of the silicon semiconductor substrate 1 on both sides of the gate electrode wiring 100.

Next, as shown in FIG.
A silicon oxide film 9 of about 0 to 150 nm is
It is formed on the entire surface by the VD method.

Next, for example, as shown in FIG.
In a dry O ₂ atmosphere, a thermal oxidation treatment is performed at a temperature of about 900 to 950 ° C. for about 60 to 150 minutes to form a thermal oxide film 100 a on the surface of the gate electrode wiring 100, and at both ends of the gate electrode wiring 100. The thickness of the gate oxide film 3 near the portion is increased to form a thick portion 3a. Also,
At this time, the n-type impurity in the n-type low-concentration ion-implanted layer 8a is activated by the heat treatment to form the n ⁻ diffusion layer 8.

The thick film portion 3a of the gate oxide film 3 is formed in the vicinity of both ends of the gate electrode wiring 100, for example, in the range of 0.03-0.
It is formed in a region having a width of about 1 μm, and has a thickness of, for example, about 200 to 300 °.

Next, as shown in FIG. 2B, the silicon oxide film 9 is anisotropically dry-etched by, for example, RIE (Reactive Ion Etching) to form, for example, Thick film portion 3 of gate oxide film 3
A sidewall oxide film 9a having a thickness of about 2 to 4 times the thickness of a is formed. In addition, the gate oxide film 3 outside the side wall oxide film 9a is removed by dry etching at this time, and the surface of the silicon semiconductor substrate 1 at that portion is exposed.

Then, next, as shown in FIG.
A silicon oxide film 10 having a thickness of about 20 to 30 nm is formed on the entire surface by, for example, a CVD method. And then
Using the gate electrode wiring 100 including the side wall oxide film 9a and the field oxide film 2 as a mask, for example, arsenic (As) as the n-type impurity 11 is 1 × 10 ¹⁵ to 1 × 10 ^16.
Ion implantation is performed on the entire surface with a dose of about / cm ² and implantation energy of about 60 keV to form an n-type high-concentration ion implantation layer 12a in the surface region of the silicon semiconductor substrate 1 outside the sidewall oxide film 9a.

Next, as shown in FIG. 3B, for example, a BPSG (boron phosphorus silicate glass) film 13 is formed on the entire surface as an interlayer insulating film, and a heat treatment is performed to flatten the surface. . Further, the heat treatment at this time activates the n-type impurities in the n-type high-concentration ion-implanted layer 12a,
An n ⁺ diffusion layer 12 mainly forming the source / drain of the channel MOS transistor is formed.

Thereafter, after forming necessary contact holes in the BPSG film 13, a metal wiring layer 14 is patterned to complete an n-channel MOS transistor having an LDD (Lightly Doped Drain) structure as shown in the figure.

The n-channel M according to the first embodiment
In the OS transistor, the gate oxide film 3 in a region having a width of, for example, about 0.03 to 0.1 μm near both ends of the gate electrode wiring 100 has a thickness of, for example, 200 to 30 μm.
Since the thick film portion 3a having a thickness of about 0 ° is formed, the electric field concentration in that portion is reduced, and the transistor characteristics are improved by improving the gate withstand voltage and suppressing GIDL.

In the thermal oxidation process for forming the thick film portion 3a, the gate electrode wiring 100 is
Therefore, it is possible to prevent vapors such as W and Ti from being generated from the metal silicide layer 5 and contaminating the inside of the furnace.

Further, since the silicon oxide film 9 is used for forming the side wall oxide film 9a of the gate electrode wiring 100, the number of steps is not increased as compared with the conventional case.

In place of the silicon oxide film 9 formed by the CVD method, a BSG (boron silicate glass) film or PS
It is also possible to use a G (phosphorus silicate glass) film. In this case, the BSG film can be used as a solid-phase diffusion source for forming a p-channel LDD layer (low-concentration diffusion layer having an LDD structure), and the PSG film can be used for forming an n-channel LDD layer.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS.

In the second embodiment, portions corresponding to those in the above-described first embodiment are denoted by the same reference numerals as those in the above-described first embodiment.

First, as shown in FIG. 4A, similarly to the first embodiment, for example, after forming a field oxide film 2 and a gate oxide film 3 on a p-type silicon semiconductor substrate 1, respectively, In the second embodiment, a polysilicon layer 4 doped with an n-type impurity such as phosphorus (P) and a refractory metal silicide layer 5 such as tungsten (W) or titanium (Ti) are sequentially stacked thereon. After that, on top of that,
A cap insulating film 6 made of a silicon oxide film is laminated, and the laminated film is patterned by photolithography and dry etching to form a gate electrode wiring pattern 1.
01 is formed. Note that the cap insulating film 6 may be a silicon nitride film.

Next, as shown in FIG. 4B, using the gate electrode wiring pattern 101 and the field oxide film 2 as a mask, for example, phosphorus (P) is used as the n-type impurity 7 at 1 × 10 ^13. Ions are implanted into the entire surface with a dose of about 5 × 10 ¹³ / cm ^{2 and} an implantation energy of about 60 keV, and an n-type low-concentration ion-implanted layer 8 a is formed in the surface region of the silicon semiconductor substrate 1 on both sides of the gate electrode wiring pattern 101.
To form

Next, as shown in FIG.
A silicon oxide film 9 of about 0 to 150 nm is
It is formed on the entire surface by the VD method.

Next, as shown in FIG.
In this embodiment, the silicon oxide film 9 is anisotropically dry-etched at this point to form a gate electrode wiring pattern 10.
1 are formed on both side surfaces. In addition, the gate oxide film 3 outside the side wall oxide film 9a is removed by dry etching at this time, and the surface of the silicon semiconductor substrate 1 at that portion is exposed.

Then, next, as shown in FIG.
For example, in a dry O ₂ atmosphere, 900 to 950
A thermal oxidation process is performed at a temperature of about 60 ° C. for about 60 to 150 minutes to form the polysilicon layer 4 of the gate electrode wiring pattern 101.
Then, a thermal oxide film 101a is formed on the side surface of the metal silicide layer 5, and the gate oxide film 3 near both ends of the gate electrode wiring pattern 101 is thickened to form a thick film portion 3a. At this time, the exposed surface of the silicon semiconductor substrate 1 outside the side wall oxide film 9a is also thermally oxidized, and a thermal oxide film 15 is formed there. Further, the n-type impurity in n-type low-concentration ion-implanted layer 8a is activated by the heat treatment at this time, and n ⁻ diffusion layer 8 is formed.

Thereafter, as shown in FIG. 6A, the gate electrode wiring pattern 101 including the side wall oxide film 9a and the field oxide film 2 are used as masks, and arsenic (As) is used as the n-type impurity 11 for example. , 1 × 10 ¹⁵ -1 × 10 ¹⁶
Ion implantation is performed on the entire surface with a dose of about / cm ² and implantation energy of about 60 keV to form an n-type high-concentration ion implantation layer 12a in the surface region of the silicon semiconductor substrate 1 outside the sidewall oxide film 9a.

Then, as shown in FIG. 6B, for example, a BPSG film 13 is formed on the entire surface as an interlayer insulating film, and heat treatment is performed to flatten the surface.
An n-type impurity in the n-type high-concentration ion-implanted layer 12a is activated to form an n ⁺ diffusion layer 12 mainly including the source / drain of the n-channel MOS transistor.

Further, after necessary contact holes are formed in the BPSG film 13, a metal wiring layer 14 is patterned to complete an n-channel MOS transistor having an LDD structure as shown in the figure.

In the second embodiment, by providing the cap insulating film 6 in advance on the gate electrode wiring, the buffer at the time of ion implantation shown in FIG. The CVD process of the silicon oxide film 10 which is a film can be omitted.

[0046]

According to the present invention, by increasing the thickness of the gate oxide film near both ends of the gate electrode using the polycide wiring, it is possible to alleviate the electric field concentration at that portion and to improve the transistor characteristics. Can be improved. In addition, since the thermal oxidation treatment for increasing the thickness of the gate oxide film can be performed in a state where the gate electrode having the polycide structure is covered with the silicon oxide film, metal vapor is generated from the metal silicide layer of the gate electrode. Contamination of the inside of the furnace is prevented.

[Brief description of the drawings]

FIG. 1 shows an n-channel M according to a first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor in the order of steps.

FIG. 2 shows an n-channel M according to the first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor in the order of steps.

FIG. 3 shows an n-channel M according to the first embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor in the order of steps.

FIG. 4 shows an n-channel M according to a second embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor in the order of steps.

FIG. 5 shows an n-channel M according to a second embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor in the order of steps.

FIG. 6 shows an n-channel M according to a second embodiment of the present invention.
FIG. 7 is a schematic cross-sectional view showing a method for manufacturing an OS transistor in the order of steps.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 p-type silicon semiconductor substrate 2 field oxide film 3 gate oxide film 3 a thick film portion 4 polysilicon layer 5 refractory metal silicide layer 6 cap insulating film 7, 11 n-type impurity 8 n ^- diffusion layer (LDD layer) 9 silicon oxide Film 9a sidewall oxide film 12 n ⁺ diffusion layer 13 BPSG film 14 metal wiring layer 15 thermal oxide film 100 gate electrode wiring 100a thermal oxide film 101 gate electrode wiring pattern 101a thermal oxide film

Claims (7)

[Claims] 1. A step of forming a gate oxide film on a surface of an element forming region of a semiconductor substrate of a first conductivity type, and a lamination comprising a polycrystalline silicon layer and a metal silicide layer thereover on the gate oxide film. Forming a film; patterning the laminated film into a shape of a gate electrode wiring; introducing a second conductivity type impurity into a surface region of the semiconductor substrate on both sides of the gate electrode wiring; Forming a silicon oxide film over the entire surface so as to cover the electrode wiring; and performing heat treatment to increase the thickness of the gate oxide film near both ends of the gate electrode wiring covered with the silicon oxide film. A method for manufacturing a semiconductor device, comprising: 2. A step of forming a side wall oxide film mainly composed of the silicon oxide film on a side surface of the gate electrode wiring by anisotropically etching the silicon oxide film after the heat treatment step. After covering the entire surface with a second silicon oxide film, introducing a second conductivity type impurity into the surface region of the semiconductor substrate outside the sidewall oxide film of the gate electrode wiring at a relatively high concentration. 2. The method for manufacturing a semiconductor device according to claim 1, comprising: 3. A step of forming a gate oxide film on a surface of an element forming region of a semiconductor substrate of a first conductivity type, and a polycrystalline silicon layer, a metal silicide layer thereover, and a metal silicide layer thereover on the gate oxide film. A step of forming a laminated film including a cap insulating layer; a step of processing the laminated film into a gate electrode wiring pattern; and a second conductivity type impurity in a surface region of the semiconductor substrate on both sides of the gate electrode wiring pattern. Introducing a silicon oxide film over the entire surface so as to cover the gate electrode wiring pattern, and anisotropically etching the silicon oxide film to form the gate electrode wiring pattern. Forming a side wall oxide film mainly composed of the silicon oxide film on a side surface; and performing a heat treatment to form a gate electrode wiring pattern covered with the silicon oxide film. Thickening the gate oxide film near both ends and forming a thermal oxide film on the surface of the semiconductor substrate outside the sidewall oxide film of the gate electrode wiring pattern; Introducing a second conductivity type impurity into the surface region of the semiconductor substrate outside the sidewall oxide film at a relatively high concentration. 4. The method according to claim 3, wherein the cap insulating layer is a silicon oxide layer. 5. A semiconductor device comprising: a gate electrode wiring formed of a laminated film including a polycrystalline silicon layer and a metal silicide layer thereon; wherein a gate oxide film near both ends of the gate electrode wiring is formed by the gate electrode wiring. A thicker portion of the gate oxide film at a central portion of the semiconductor device, wherein the thickness of the thick portion of the gate oxide film is 200 to 300 °. 6. The semiconductor device according to claim 5, wherein said thick film portion is formed in a region having a width of 0.03 to 0.1 μm near both ends of said gate electrode wiring. 7. The method according to claim 5, wherein a sidewall oxide film having a thickness of 2 to 4 times the thickness of the thick film portion is formed on a side surface of the gate electrode wiring. Semiconductor device.