JPS60247974A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the generation of hot electrons extremely by forming a low- concentration P<-> layer having the same conduction type as a substrate at a section where source-drain and a channel ion-implantation layer are in contact and making the position of an intensified power electric field to keep away from a channel current path. CONSTITUTION:A high resistance substrate 501 consisting of P type silicon is thermally oxidized to shape a gate insulating film 505. Boron ions for controlling a thershold are implanted to form an ion implantation layer 504. A polycrystalline silicon film 506 is deposited as a gate electrode, and patterned. Boron ions are implanted 507 while using these films as masks, phosphorus ions are implanted by employing said masks, and boron ions are implanted to the gate insulating film 505 and a section in the vicinity of a substrate interface again to shape a low impurity layer P<->. An insulating region 505' is formed, and phosphorus ions are implanted again to shape low-concentration N<-> regions 502, 503. As ions in the high quantity of doping are implanted to a section in the vicinity of a substrate surface to form an N<+> layer 509.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an insulated gate type fine element structure, and particularly relates to:
The present invention relates to a highly reliable semiconductor device that is excellent against hot electrons.

[Conventional technology and its problems] As semiconductor devices become faster and more highly integrated,
A particular problem is a decrease in reliability due to fluctuations in the threshold value, punch-through phenomenon, hot electron phenomenon, etc. Various countermeasures have been taken, for example, as shown in FIG. 1, the gate oxide film 15 (tOX) is thinned, and the source 13 and drain 1
The junction depth xi of No. 2 may be made shallow. On the other hand, there is a method of increasing the substrate concentration to suppress the punch-through phenomenon, but increasing the substrate concentration increases the junction capacitance between the source/drain and the substrate and the substrate bias of the threshold voltage V
The dependence on B increases, resulting in inconvenience in LSI design. Conventionally, for this purpose, a high-resistance substrate 11 is used, and a high dose of ions is implanted deep into the element active region to form a highly doped layer 17 having the same conductivity type as the substrate.

In FIG. 1, 14 is an ion implantation layer for controlling threshold voltage, and 16 is a gate electrode. However, in a semiconductor element with this structure, the electric field strength near the junction position where the drain 12 contacts the ion-implanted layers 14 and 17 increases, and holes (in the case of n-ch MO8') generated by electron collisions are absorbed into the substrate. Flowing through 11,
This is undesirable because the substrate current 1110B increases, causing fluctuations in the substrate potential and reducing the reliability of the LSI. The insulated gate transistor (hereinafter abbreviated as MOS transistor) shown in FIG. 2 includes a substrate 21, a source 21, a drain 22, a gate oxide film 5, and a gate electrode 26. Between the drains 22 and 23, a low concentration N layer 22', 23' of the same conductivity type as the source and drain is provided to suppress the high electric field and prevent the generation of hot electrons. However, the MOS transistor having this structure has a drawback in that the transconductance gm of the current-voltage characteristic is reduced. FIG. 3 shows another conventional technique made for the same purpose.

31 is a high resistance substrate, 32 and 33 are drains and sources, 37 is an ion implantation layer, 35 is a gate insulating film, 36
is a gate electrode, and 32' and O' are low concentration layers N- of the same conductivity type as the source and drain. Also in the electrical characteristics of this structure, the trans conductance gm decreases as in FIG. 2 described above. Next, another example of the prior art is shown in FIG. 41 is a high resistance board, 42.4
3 is a low concentration N-drain/source, the shrine is an ion-implanted layer for threshold voltage control, 45 is a gate insulating film, 46 is a gate electrode, and 47 is a pocket for punch-through prevention, which has the same voltage as the type substrate. type high concentration ion implantation layer, 45
' is an insulating film formed using the sidewall leaving technique, and p-4-s is formed to lower the resistance of the source/drain and gate electrodes.

It is a layer. In the MOS having this structure, the maximum value of the electric field at the portion where the lightly doped N-drain 42 contacts the single layer 47, which is more doped than the substrate, is near the interface between the gate insulating film 45 and the substrate, that is, It exists at a position where most of the channel current flows, and is not a preferable structure from the viewpoint of reducing the substrate current l81JB.

[Object of the invention] The present invention has been made in view of the above problems, and
The present invention provides a miniaturized semiconductor device composed of highly reliable MOS (MOS) transistors.

[Summary of the invention]

MO consisting of low concentration source/drain and hypocerate
In an S transistor, a low-concentration P'' layer with the same electric type as the substrate is formed in the portion where the source/drain and the channel ion/implanted layer are in contact, that is, near the interface between the Kent insulating film and the substrate, and a strong electric field is generated from the channel current path. This is a semiconductor device that further reduces the generation of hot electrons.

〔Effect of the invention〕

The present invention reduces the generation of hot electrons as much as possible,
It was possible to obtain a MOS (MOS) transistor with a lower substrate current, and the reliability of LSI was greatly improved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the structural cross-sectional view of FIG. In FIG. 5, reference numeral 501 is a high resistance (~50Ω) substrate made of, for example, P-type silicon, and this substrate is thermally oxidized to form a gate insulating film 505. Continuing,
Boron ions for threshold control are implanted to form an ion implantation layer 504. Next, for example, as a gate electrode,
A polycrystalline silicon film 506 is deposited, and the layers 506 and 504 are patterned to form a desired gate region. Using these as masks, first boron ion implantation 507
Then, using the same mask, phosphorus ions are implanted to form 502' and 503', and boron ions are implanted again near the interface between the gate insulating film 505 and the substrate.
08 is formed. Next, a CVD, Sin, film is deposited on the entire surface, and an insulating region 505' shown in FIG. 5 is formed using reactive ion etching to leave sidewalls intact. Using the 505' and 506' regions and the gate electrode 506 as a mask, phosphorus ions are implanted again to form low concentration N- regions 502 and 503. Further, next, A11 ions are implanted at a higher dose near the substrate interface to form eight layers 509, and then a normal MOS transistor process is carried out to complete the semiconductor device of the present invention.

Here, in order to explain the operation of FIG. 5, an enlarged view of the drain member is shown in FIG. 7. Drain in 709 of this device
, 702, most of the depletion layer at the drain tip is formed by the lightly doped N- region 702' and the P-
And there is I near the N-interface. On the other hand, as shown in FIG. 7, the channel current flows near the interface between the gate insulating film 705 and the substrate on the source side, and is slightly buried and protrudes from the interface on the drain side. Therefore, most of the channel current deviates from the location where the electric field is strong (x mark). In this way, the generation of hot electrons can be further reduced. FIG. 6 shows the results of a comparison between the substrate current l8tl11 of the semiconductor device according to the present invention and that according to the prior art. Comparing the maximum value of the substrate current 111tlB, in the present invention, the value is smaller by about v10 or more, and the device is superior in reliability by 1. The results of this comparison are shown in FIG. Substrate current l5u
When compared with the maximum value of a, the present invention has a smaller value of about 1.5 orders of magnitude, indicating that it is superior in reliability.

[Other embodiments of the invention]

In one embodiment of the present invention, a P-bot structure is shown as an example, but deep ion implantation layers 27 and 3 in FIGS.
A structure using 6 has the same effect, and furthermore, the source
Although eight layers 509 of high impurities were used to lower the resistance of the drain, a structure using four PT-S layers as shown in FIG. 4 may also be used.

In addition, although we have described N-ah MOS transistor example 1 in the embodiment, it can also be applied to P-ch MOS transistors, and the substrate is not only bulk silicon but also SO8.
, may be formed on an insulating substrate such as SOI.

[Brief explanation of drawings]

1, 2, 3, and 4 are cross-sectional views of a semiconductor device according to the prior art 1, FIG. 5 is a sectional view of a semiconductor device according to the present invention 1, and FIG. 6 is a sectional view of a semiconductor device according to the present invention 1. Figure 7 shows the characteristics UX comparing the conventional characteristics and the characteristics of the present invention 1. Figure 7 shows the relationship between the drain current path and the maximum electric field by enlarging the vicinity of the drain of the device of the present invention (Figure 5). It is a characteristic diagram. In the figure, 11.21.31.41.501.701... semiconductor substrate 12.22, 32, 509.13, 23.33, 7
09... High concentration drain/source N region 14.24, 34, 44, 504... Ion implantation layer for threshold control 15.25.35, 45, 505, 705
...gate insulating film 16.26.36,46,506,
706...Gate electrode 17.27, 37, 47, 5
07,707...High impurity concentration layer of the same conductivity type as the substrate

Claims (1)

[Claims] facing one main surface of the semiconductor region having the first conductivity type;
First and second conductive regions are formed with a required distance from each other, an insulating film is formed over a portion where a channel is to be formed between the first and second regions, and the insulating film is In an insulated gate transistor having a gate electrode formed thereon, an impurity concentration region higher in depth than that of a substrate having the same conductivity type as the substrate is provided in a deep region at the tip in the lateral direction along the channel of the first or second region. , a low concentration impurity region of the second conductivity type is provided so as to be surrounded by the high impurity concentration, and a region with a lower concentration of impurity than the impurity concentration of the first conductivity type directly below the channel is provided in a shallow region of the substrate surface. and,
Using the sidewall leaving technique, a region serving as a mask is formed on the sidewall of the Kent electrode, and using this mask, a region with an impurity concentration higher than that of the substrate is formed in a portion facing the first or second deep region. A semiconductor device characterized in that a deep region of a second conductivity type and a high concentration impurity concentration region of a second conductivity type are provided on the surface of the substrate, leaving a low impurity concentration region on the surface of the substrate.