JPH0656855B2 - Insulated gate type field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an insulated gate field effect transistor, and more particularly to a transistor structure having a low impurity concentration layer near a gate electrode in a drain region.

[Technical background of the invention and its problems]

In recent years, high integration of semiconductor integrated circuits and miniaturization of elements have been remarkable. In an integrated circuit using an insulated gate field effect transistor (hereinafter, simply referred to as a MOS transistor), the element is particularly miniaturized, so that the electric field strength inside the element is very large. In such a MOS transistor, carriers in the channel are accelerated by a strong electric field, and high energy carriers are generated in the vicinity of the drain region, and trapped in the gate insulating film, the threshold voltage and transconductance are increased. It will change. This effect, called the hot carrier effect, significantly impairs the device characteristics, and thus the characteristics of integrated circuits using such devices.

As a countermeasure against this hot carrier effect, a transistor structure has been proposed in which a low impurity concentration layer is provided in the drain region near the gate electrode. One of them is a so-called LDD (Lightly Doped Drain) structure.
When this LDD structure is used, the strong electric field in the vicinity of the drain region is relaxed due to the existence of the low impurity concentration layer at the end of the drain region, and as a result, the generation of hot carriers is suppressed.

However, in this MOS transistor having the LDD structure, the change in threshold voltage can be reduced to some extent by suppressing the hot carrier effect, but the effect of suppressing the amount of change in transconductance is not recognized so much. This is because when hot carriers generated near the drain are trapped in the insulating film on the side wall of the gate electrode, the electrostatic current pushes the channel current downward to the substrate, increasing the effective series resistance. Is.

[Object of the Invention]

The present invention has been made in view of the above points, and an object thereof is to provide a highly reliable MOS transistor capable of suppressing a decrease in mutual conductance due to a hot carrier effect.

[Outline of Invention]

A MOS transistor according to the present invention is an insulated gate field effect transistor having a low impurity concentration layer in the vicinity of a gate electrode in a drain region, in the vicinity of the gate electrode on a region extending from the low impurity concentration layer to the drain region outside thereof. In the insulating film, a conductive layer for diffusing charges injected into the insulating film by the hot carrier effect is provided.

〔The invention's effect〕

In the MOS transistor according to the present invention, since the low resistance conductive layer is provided on the low impurity concentration layer at least near the gate electrode in the drain region, the injected charges due to the hot carrier effect are localized near the gate electrode. As a result, the change in the threshold value is reduced and the decrease in the mutual conductance is suppressed.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows an LDD structure MOS transistor according to an embodiment. Reference numeral 11 denotes a p-type Si substrate, on which a gate electrode 1 made of a polycrystalline silicon film with a gate insulating film 12 interposed therebetween.
3 is formed. The source / drain regions are diffused by using the n ⁻ type layers 14 and 15 which are low impurity concentration layers formed by shallow diffusion using the gate electrode 13 as a mask, and the insulating film 19 left on the sidewalls of the gate electrode 13 as a mask. It is composed of n ⁺ type layers 16 and 17 having a high impurity concentration.

In such an LDD structure, in this embodiment, the conductive layer 18 is continuously provided in contact with at least the surface of the n ⁻ type layer 15 on the drain side to the surface of the n ⁺ type layer 17. The conductive layer 18 is a layer having a lower resistance than the n ⁻ type layers 14 and 15, for example, a tungsten (W) film.

FIGS. 2A to 2E are examples of manufacturing steps for obtaining such a structure. A gate electrode 13 made of a polycrystalline silicon film is formed on a p-type Si substrate 11 through a gate oxide film 12 formed by thermal oxidation according to a well-known process, and ion implantation is performed using the gate electrode 13 as a mask to self-align with the gate electrode 13. The shallow n ⁻ type layers 14 and 15 thus formed are formed ((a)). Next, the conductive layer 18 is formed by the selective CVD method ((b)). The conductive layer 18 is W in this embodiment.
It is a film. The W film formed by CVD selectively grows on the Si surface depending on the conditions and does not grow on the insulating film. Therefore, as shown in the drawing, the W film on the source / drain regions and the W film on the surface of the gate electrode 13 are automatically separated. After that, a silicon oxide film 19 is deposited on the entire surface by the CVD method ((c)). Then, the laminated film of the silicon oxide film 19 and the W film 18 is entirely etched by an anisotropic etching method such as RIE, and this is left only on the side wall of the gate electrode 13 ((d)). After that, ion implantation is performed using the gate electrode 13 and the silicon oxide film 19 on the side wall thereof as a mask to perform high-impurity concentration n ⁺ -type layers 16 and 1 in the source and drain regions.
7 is formed ((e)).

According to this manufacturing process, the conductive layer 18 is formed not only on the drain side but also on the source side. Since a high electric field is not applied to the source side, the conductive layer on the source side is essentially useless. However, if conductive layers are provided on both sides in this way, whichever is used as the source or drain in the integrated circuit Is also effective.

In the MOS transistor of this embodiment, the drain side n
Due to the conductive layer 18 provided on the ⁻ type layer 15, the charges trapped in the insulating film near the gate electrode 13 due to the hot electron effect do not stop there, but diffuse and escape to the n ⁺ type layer 17. Therefore, the decrease of the mutual conductance is suppressed, and the reliability in the case of miniaturization is improved.

FIG. 3 shows an LDD structure MOS transistor according to another embodiment of the present invention. The basic structure is the same as that of FIG. 1, and therefore the parts corresponding to those of FIG. 1 are denoted by the same reference numerals as in FIG. 1 is different from that of FIG. 1 in that the conductive layer 18 is formed in contact with the surface of the n ⁻ type layer in FIG. 1, whereas in this embodiment, the conductive layer 18 is formed via a thin insulating film 20. Is being formed.

4A to 4E show an example of the manufacturing process of this MOS transistor. This manufacturing process is also basically the same as that of FIGS. 2 (a) to 2 (e) of the previous embodiment, and therefore FIG.
Parts corresponding to (e) are assigned the same reference numerals and detailed explanations thereof are omitted. The difference from the previous manufacturing process is the fourth
In FIG. 6B, the silicon oxide film 20 is previously formed as a thin insulating film by thermal oxidation or the like before the conductive layer 18 is formed. Moreover, since a W film cannot be formed by selective CVD on the insulating film, a conductive layer such as a W film is formed by a vapor deposition method or a sputtering method.

Also in this embodiment, due to the presence of the conductive layer 18, the charges injected into the insulating film are dispersed without being localized due to the hot carrier effect, so that the same effect as the previous embodiment can be obtained.

The present invention is not limited to the above embodiments. For example, as the conductive layer, other than the W film, another metal film having a lower resistance than the n ⁻ type layer can be used.

Although the LDD structure has been described in the embodiment, another structure having a low impurity concentration layer near the drain, for example, GD
MOS with D (Graded and Diffused Drain) structure
The present invention can be similarly applied to transistors and the like. Further, the present invention is not limited to the case where the low impurity concentration layer near the gate electrode is shallower than the high impurity concentration layer outside thereof.

[Brief description of drawings]

FIG. 1 is a diagram showing a MOS transistor according to an embodiment of the present invention, and FIGS. 2 (a) to 2 (e) are diagrams showing an example of its manufacturing process.
FIG. 3 is a diagram showing a MOS transistor of another embodiment, and FIGS. 4 (a) to 4 (e) are diagrams showing an example of the manufacturing process thereof. 11 ... p-type Si substrate, 12 ... gate insulating film, 13 ...
... Gate electrode, 14, 15 ... n ^- type layer (low impurity concentration layer), 16,17 ... n ⁺ type layer (high impurity concentration layer), 1
8 ... Conductive layer (tungsten film), 19, 20 ... Silicon oxide film.

Claims (6)

[Claims] 1. In an insulated gate field effect transistor having a low impurity concentration layer near a gate electrode in a drain region, an insulating film near the gate electrode on a region extending from the low impurity concentration layer to the drain region outside thereof. An insulated gate field effect transistor characterized in that a conductive layer for diffusing charges injected into the insulating film by a hot carrier effect is provided therein. 2. The insulated gate effect transistor according to claim 1, wherein the conductive layer has a resistance lower than that of the low impurity concentration layer and is provided in contact with the surface of the low impurity concentration layer. 3. The insulated gate field effect according to claim 1, wherein the conductive layer has a resistance lower than that of the low impurity concentration layer and is provided on the surface of the low impurity concentration layer through a thin insulating film. Transistor. 4. The insulated gate field effect transistor according to claim 2, wherein the conductive layer is a metal film formed by selective CVD. 5. The insulated gate field effect transistor according to claim 3, wherein the conductive layer is a metal film formed by a vapor deposition method or a sputtering method. 6. The insulated gate field effect transistor according to any one of claims 1 to 5, wherein the conductive layer is made of tungsten.