JPH05343417A - Mos type semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent deterioration in the characteristics of specific LDD structure by forming a conductor side wall formed on a low doped region in LDD structure by way of a thin insulation film on a gate electrode side surface in such a fashion that it may come into direct contact with the low doped region. CONSTITUTION:A drain region 20 provides an N type doped region 20b on a channel side and an N type high doped region 20a on a side separated from the channel. In a similar manner, a source region 18 provides a low doped region 18b on a channel side and a high doped region 18a on a side separated from the channel side. An N type polysilicon-made conductor side wall 24 is formed on sides of a gate electrode 16 by way of a thin silicon oxide film 22 whose film thickness ranges from 100 to 500Angstrom . The conductor side wall 24, the low doped regions 18b and 20b are electrically connected to each other. This construction makes it possible to eliminate deterioration in device characteristics which are specific to LDD structure induced by hot electrons.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS semiconductor device, and more particularly to a semiconductor device having an LDD structure and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the hot carrier breakdown voltage of a MOS transistor, an LDD structure having a low impurity concentration region on the channel side of a drain region is widely adopted. FIG. 4 shows the main part near the drain of the LDD structure. A gate electrode 6 is formed on the channel region on the substrate 2 via a gate oxide film 4, and a sidewall spacer 8 used for forming an LDD structure is formed on the side surface of the gate electrode 6 from an insulator. Has been done. The drain region is composed of a high impurity concentration region 10a and a low impurity concentration region 10b on the channel side.

Even in the LDD structure, deterioration of characteristics due to hot carriers still exists. This is because hot electrons are trapped in the oxide film on the low concentration impurity region 10b, and the apparent mutual conductance gm due to the hot electrons deteriorates. The hot electrons trapped in the oxide film are the low impurity concentration region 10b.
Of the low impurity concentration region 10b, the resistance of the low impurity concentration region 10b is increased. The increase in the resistance of the low impurity concentration region 10b appears externally as a decrease in the transconductance gm or an increase in the threshold voltage.

It has been proposed that the side wall spacer 8 is made of polysilicon instead of an insulator (Japanese Patent Laid-Open No. 2-2684).
42, Japanese Patent Laid-Open No. 2-276251). However, even in those MOS transistors, since the gate oxide film exists between the side wall of the conductor and the low impurity concentration region, deterioration of the characteristics due to hot electrons exists as shown in FIG. ..

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to prevent deterioration of characteristics peculiar to an LDD structure.

[0006]

The LDD structure MO of the present invention
In the S-type semiconductor device, a conductor is formed in a side wall shape on the side surface of the gate electrode via a thin insulating film, and the side wall of the conductor is located on the low impurity concentration region of the drain region and the low impurity concentration region thereof. You are in direct contact. .. In a preferred mode, the side wall of the conductor on the side surface of the gate electrode is made of polysilicon having the same conductivity type as the drain region.

The manufacturing method of the present invention includes the following steps (A) to (F). (A) A step of forming a gate electrode on the gate oxide film in the active region and removing the gate oxide film outside the gate electrode, (B) forming a thin insulating film on the entire surface, and performing etchback to form the gate electrode A step of leaving the insulating film on the side surface of the substrate, (C) a step of implanting impurities into the substrate at a low concentration to form the source / drain,
(D) A step of depositing a polysilicon film on the entire surface and performing etching back to leave the polysilicon film on the side surface of the gate electrode through the insulating film. (E) Impurity is added to the substrate for forming source / drain. High concentration ion implantation step,
(F) A heat treatment step for activating and diffusing the impurities injected into the substrate.

[0008]

Since the side wall of the conductor formed on the side surface of the gate electrode via the thin insulating film is formed in direct contact with the low impurity concentration region of the LDD structure, the low impurity concentration region is formed. Therefore, even if hot electrons are generated, they are diffused into the side wall of the conductor and negative charges are not accumulated at the interface with the low impurity concentration region. Therefore, there is a decrease in mutual conductance gm and an increase in threshold voltage due to hot electrons. No characteristic deterioration occurs.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the main part of one embodiment. In FIG. 1, a gate oxide film 1 is formed on a P-type silicon substrate 12.
A gate electrode 16 made of polysilicon is formed via the gate electrode 4. The drain region 20 has an N-type low impurity concentration region 20b on the channel side and an N-type high impurity concentration region 20a on the side away from the channel. Similarly, the source region 18 has an N-type low impurity concentration region 18b on the channel side and an N-type high impurity concentration region 18a on the side away from the channel. A conductor side wall 24 made of N-type polysilicon is formed on the side surface of the gate electrode 16 through a thin silicon oxide film 22 having a film thickness of 100 to 500Å, and the conductor side wall 24 and the low impurity concentration regions 18b, 20 are formed.
There is no insulating film between b, and the conductor side wall 24 and the low impurity concentration regions 18b and 20b are electrically connected.
Although not shown, an interlayer insulating film is further formed as a MOS transistor, and metal wirings are connected to the source / drain regions 18 and 20 and the gate electrode 16 through the contact holes.

The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. When electrons flow from the channel to the high-concentration drain region 20a through the low-concentration drain region 20b by the operation of this NMOS transistor, even if hot electrons are generated by a high voltage at the drain end, the charge is stored in the conductor sidewall. It diffuses in 24 and does not stay at the interface with the low concentration drain region 20b.

Next, a method of manufacturing the embodiment of FIG. 1 will be described with reference to FIG. (A) A gate oxide film 14 is formed in the active region of the P-type silicon substrate 12 in which elements are isolated, a polysilicon film is deposited on the entire surface, and patterning is performed by photolithography and etching to form a gate electrode 16. (B) A silicon oxide film is thinly deposited on the entire surface or formed by thermal oxidation. The silicon oxide film is 100 ~ 500Å
It is formed to have a film thickness of. Then, etch back is performed to leave the silicon oxide film 22 only on the side surface of the gate electrode 16. Next, in order to form low impurity concentration regions of the source / drain, for example, phosphorus ions of 60 Ke are used as P-type impurities.
Implant at about 1 × 10 ¹³ / cm ^{2 with} V. 26 is the substrate 12
Is the phosphorus ions implanted in the.

(C) A polysilicon film is deposited on the entire surface and is etched back to leave the polysilicon film 24 on the side surface of the gate electrode 16 with the silicon oxide film 22 interposed therebetween. Next, in order to form high impurity concentration regions of the source / drain, for example, arsenic as an N-type impurity is added at 50 KeV to 6
About 10 ¹⁵ / cm ^{2 is} injected. At this time, the gate electrode 1
Arsenic is also implanted into the polysilicon side wall 24 on the side surface of No. 6. 28 is arsenic implanted into the substrate 12, and 30 is arsenic implanted into the polysilicon side wall 24. (D) A heat treatment for activating and diffusing the implanted ions is performed. As a result, the N-type source / drain region 20
a and 20b are formed and the polysilicon side wall 2 is formed.
4 becomes N type. After that, according to a normal process, an interlayer insulating film is deposited, contact holes are formed, metal wiring is formed,
A passivation film is formed.

[0013]

In the LDD structure MOS transistor of the present invention, there is no insulating film on the low impurity concentration region of the drain, and the side wall of the conductor formed on the side surface of the gate electrode through the insulating film has the low impurity concentration of the drain. Since it is in direct contact with the region, avalanche hot electrons at the drain are not trapped at the interface between the low impurity concentration region and the portion above it, and therefore LDD by hot electrons trapped on the low impurity concentration region is caused. Degradation of device characteristics peculiar to the structure does not occur. When manufactured by the manufacturing method of the present invention,
Since the impurity introduction to the side wall of the conductor formed on the side surface of the gate electrode via the insulating film and the impurity introduction of the source / drain formation are performed in the same step, the process is simplified.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing an embodiment.

FIG. 2 is a cross-sectional view of the main part near the drain showing the operation in the same Example.

FIG. 3 is a process cross-sectional view showing the manufacturing method of the embodiment.

FIG. 4 is a cross-sectional view of essential parts showing an operation in a conventional LDD structure.

[Explanation of symbols]

 12 P-type silicon substrate 14 Gate oxide film 16 Gate electrode 20a High-concentration drain region 20b Low-concentration drain region 22 Silicon oxide film on side face of gate electrode 24 Polysilicon sidewall

Claims (3)

[Claims] 1. A gate electrode is formed on a semiconductor substrate via a gate oxide film, and at least a drain region has an LDD structure having a low impurity concentration region on a channel side,
A conductor is formed in a sidewall shape on the side surface of the gate electrode through a thin insulating film, and the sidewall of the conductor is on the low impurity concentration region and is in direct contact with the low impurity concentration region. MOS type semiconductor device characterized by the above. 2. The MOS semiconductor device according to claim 1, wherein the side wall of the conductor is made of polysilicon having the same conductivity type as the source / drain regions. 3. An MO including the following steps (A) to (F):
Manufacturing method of S-type semiconductor device. (A) A step of forming a gate electrode on the gate oxide film in the active region and removing the gate oxide film outside the gate electrode, (B) forming a thin insulating film on the entire surface, and performing etch back to perform the gate electrode The step of leaving the insulating film on the side surface of the substrate, (C) the step of ion-implanting impurities into the substrate at a low concentration to form the source / drain, and (D) the polysilicon film deposited on the entire surface and etched back to form the gate. A step of leaving the polysilicon film on the side surface of the electrode through the insulating film; (E) a step of ion-implanting impurities into the substrate at a high concentration to form a source / drain; Heat treatment process to activate and diffuse.