JP2917301B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device, particularly an LDD (lightly doped dra
The present invention relates to a MOS transistor having an in) structure and a manufacturing method thereof.

[Summary of the Invention]

The present invention relates to a MOS transistor having an LDD structure, wherein a gate electrode is formed integrally with a first gate electrode and a side wall thereof.
And only the low concentration impurity region of the second conductivity type is formed only below the second gate electrode on the drain side, and the high concentration impurity of the second conductivity type is formed in self-alignment with the second gate electrode. By forming the region, the high-resistance region on the source side is eliminated to improve the current driving capability of the transistor, and the carrier concentration on the surface of the low-concentration impurity region on the drain side is controlled by the second gate electrode. This is to improve the initial deterioration.

According to the present invention, in a method of manufacturing a MOS transistor, a low-concentration impurity region of a second conductivity type is formed on a drain side via a mask layer covering a source side across a first gate electrode on a semiconductor substrate of a first conductivity type. Then, a second gate electrode is integrally formed on the side wall of the first gate electrode, and a high-concentration impurity is introduced using the first and second gate electrodes as a mask to form a high-concentration impurity region of the second conductivity type. This makes it possible to easily manufacture a MOS transistor having an LDD structure having high current driving capability and little initial deterioration.

In the above manufacturing method, the first conductivity type channel may be formed by using a mask layer used when forming the second conductivity type low concentration impurity region.
By masking the MOS transistor formation area,
C-M having the above LDD structure without increasing the number of masks
It enables the manufacture of OS transistors.

The present invention relates to a MOS transistor having an LDD structure, in which a gate electrode is formed on a side wall of a step portion of a semiconductor substrate, and a high-concentration impurity region is formed in a self-alignment manner with a gate electrode in an upper stage and a lower stage of the step portion, and a high-concentration impurity region in an upper stage is formed. By forming a low-concentration impurity region below the impurity region, the current driving capability of the transistor is improved and the initial deterioration is improved in the same manner as described above.

[Conventional technology]

In MOS transistors, an LDD structure is generally used to prevent deterioration of transistor characteristics due to hot carriers caused by miniaturization of the channel length (that is, deterioration of threshold voltage with time and deterioration of mutual conductance, etc.). I have.

In a conventional MOS transistor having an LDD structure, as shown in FIG. 4, a gate electrode (3) is formed on a semiconductor substrate of a first conductivity type, for example, a p-type silicon substrate (1) via a gate insulating film (2). Then, using the gate electrode (3) as a mask,
Conductivity type i.e. n-type low-concentration impurity region (4a) and to form a (5a), then n this by forming an insulating side wall, such as SiO ₂ (6) as a mask on the sidewalls of the gate electrode (3) Forming high-concentration regions (4b) and (5b) in the form of source regions (4), respectively;
And a drain region (5). (7)
Is an element isolation region by selective oxidation (LOCOS).

As shown in FIG. 5, a step portion is formed on a p-type silicon substrate (15) as a method of manufacturing a MOS transistor having a short channel length, and a gate electrode is formed on a side wall of the step portion via a gate insulating film (16). A polycrystalline silicon film (9) is selectively formed (FIGS. A and B), and a second conductivity type impurity is ion-implanted using the polycrystalline silicon film, that is, the gate electrode (9) as a mask to form an upper portion of the step portion. An n ⁺ layer (10) and (11) serving as a source and a drain are formed below the step (C in the same figure), and thereafter, the insulating film (12) and the extraction electrodes (13) and (14)
(See FIG. D) is known (see Japanese Patent Publication No. 60589/1986).

[Problems to be solved by the invention]

In the above-mentioned conventional MOS transistor having the LDD structure (see FIG. 4), low-concentration impurity regions (4a) and (5a) are provided in the source region (4) and the drain region (5), respectively. The low-concentration impurity region (5a) on the drain region (5) side is necessary to suppress the generation of hot carriers by weakening the electric field strength, but the low-concentration impurity region (4a) on the source region (4) side is unnecessary. It is. Conventionally, the low-concentration impurity region (4a) on the side of the source region (4) increases the source resistance and reduces the current driving capability of the MOS transistor having the LDD structure.

Further, the low concentration impurity region (5a) of the drain region (5)
The hot carriers injected into the upper insulating films (2) and (6) have a disadvantage that the carrier concentration on the surface of the low-concentration impurity region (5a) decreases and initial deterioration (initial Δgm / gmo value) increases. there were.

The present invention has been made in view of the above points, and has improved current driving capability.
In addition, a semiconductor device that can improve initial deterioration, that is, an LD
An object of the present invention is to provide a D-structure MOS transistor and a method for manufacturing the same.

[Means for solving the problem]

The semiconductor device (36) of the present invention comprises a first gate electrode (26A) and a side wall of the first gate electrode (26A) on a first conductivity type semiconductor substrate (21) via a gate insulating film (24). A gate electrode (2B) composed of an integrally formed second gate electrode (26B);
6), and the second conductive type low concentration impurity region (32) is formed only in the semiconductor substrate (21) under the drain-side second electrode (26B).
a) is formed, and high-concentration impurity regions (31) and (32b) of the second conductivity type serving as a source and a drain are formed in a self-aligned manner with the second gate electrode (26B).

Further, the method of manufacturing a semiconductor device according to the present invention is directed to the method of manufacturing a semiconductor device according to the first aspect, wherein the first gate electrode (26
A) and cover the source side and open the drain side (2
A mask layer (28) having 7) is formed, and the mask layer (2
After forming a second-conductivity-type low-concentration impurity region (32a) on the drain side via 8), a second gate electrode (26B) is integrally formed on the side wall of the first gate electrode (26A). Using the first gate electrode (26A) and the second gate electrode (26B) as a mask, high-concentration impurities are introduced to form second-conductivity-type high-concentration impurity regions (31) and (32b) serving as a source and a drain. I do.

Further, in the above manufacturing method, the MOS transistor formation region (43) of the first conductivity type channel is formed by the mask layer (28) used for forming the low concentration impurity region (32a) of the second conductivity type.
May be masked.

Another semiconductor device (51) of the present invention is a semiconductor substrate (21).
A gate electrode (49G) is formed on the side wall (48C) of the step portion (48) formed in the above via a gate insulating film (24), and the gate electrode (49G) is formed on the upper portion (48A) and the lower portion (48B) of the step portion. High-concentration impurity regions (32
b) and (31b) are formed, and a low-concentration impurity region (32a) is formed at least below the high-concentration impurity region (32b) in the upper stage (48A).

[Action]

In the semiconductor device (36) of the first invention, the low concentration impurity region (32a) is formed only on the drain (32) side,
Since there is no low concentration impurity region on the source (31) side,
The resistance on the source (31) side is reduced, and the transistor current driving capability is increased. Further, since the second gate electrode (26B) integral with the first gate electrode (26A) is formed on the low concentration impurity region (32a) on the drain (32) side, the gate electrode (26) reduces The carrier concentration on the surface of the impurity region (32a) can be controlled, and the initial deterioration is reduced.

Further, in the manufacturing method of the second invention, the mask layer (2) covering the source side over a part of the first gate electrode (26A) is provided.
8), a low concentration impurity is introduced to form a low concentration impurity region (32a), and then a second gate electrode (26B) is formed on the side wall of the first gate electrode (26A). 1st and 2nd
The gate electrodes (26A) and (26B) are used as masks to introduce high-concentration impurities to form high-concentration impurity regions (31) and (32b) serving as a source and a drain. No impurity region is formed, and a low-concentration impurity region (32a) is formed only on the drain (32) side.
The gate electrode (26) is formed on the low-concentration impurity region (32a) on the drain side, so that the semiconductor device (36) can be easily manufactured.

Further, according to the manufacturing method of the third invention, the mask layer (2) used for forming the low-concentration impurity region (32a) of the second conductivity type is formed.
Since the MOS transistor formation region (43) of the first conductivity type channel is masked in 8), a C-MOS transistor (complementary MOS transistor) having the configuration according to the first invention can be easily formed without increasing the number of masks. can do.

In the semiconductor device (51) of the fourth invention, the gate electrode (4) formed on the step side wall (48C) of the semiconductor substrate (21).
9G) and the drain (3
2) is formed, and the source (31) is formed in the lower stage (48B). Then, the low-concentration impurity region substantially in contact with the channel region (50) is not formed in the source (31) below the step portion, and the low-concentration impurity region (32a) in contact with the channel region only in the drain (32) above the step portion. ) Is formed, the current driving capability of the transistor is increased. In addition, since the gate electrode (49G) is formed via the gate insulating film (24) on the step side wall of the drain (32) facing the low-concentration impurity region (32a), the surface of the low-concentration impurity region (32a) The carrier concentration can be controlled by the gate electrode (49G), and the initial deterioration is reduced. Further, since the drain (32) is formed in the upper part of the step portion and the source (31) is formed in the lower part, the depletion layer does not easily extend from the drain (32) to the source (31) side, and therefore, punch-through hardly occurs.

〔Example〕

 Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows an example of a MOS transistor having an LDD structure according to the present invention. In this example, first, as shown in FIG. 1A, an element isolation region (SiO ₂ ) (SiO ₂ ) (LOCOS) is formed on the main surface of a semiconductor substrate of the first conductivity type, for example, a p-type silicon substrate (21). 22) is formed, and a gate insulating film (24) made of, for example, SiO ₂ or the like is formed on the main surface of the element formation region (23). Then, on top of the gate insulating film (24), an SiO ₂ film (2
A first gate electrode (26A) made of, for example, polycrystalline silicon and laminated with 5) is formed.

Next, as shown in FIG. 1B, a first gate electrode (26
An opening (2) covers a region where a source region is to be formed and a region where a drain region is to be formed so as to straddle part of A).
A photoresist mask (28) having (7) is formed.
Through this photoresist mask (28), the low-concentration second
Conductive type impurities, that is, n-type impurities (29) are ion-implanted.
Next, after a polycrystalline silicon film is formed on the entire surface, a side wall portion of the polycrystalline silicon film is formed on the side wall of the first gate electrode (26A) by RIE (reactive ion etching) as shown in FIG. 1C. 26B). The side wall (26B) is to be integrated with the first gate electrode (26A) to be a second gate electrode to which the same potential is applied. The first and second gate electrodes (26A) and (26B) form a gate electrode (26). Then, high-concentration n-type impurities (30) for forming a source region and a drain region are ion-implanted using the first gate electrode (26A) and the second gate electrode (26B) as a mask.

Next, an annealing process for activation is performed to perform an n-type source region (31) composed of a high-concentration impurity region, and an n-type drain region composed of a low-concentration impurity region (32a) and a high-concentration impurity region (32b). An area (32) is formed (see FIG. 1D).

Next, an interlayer insulating film (33) is deposited, source and drain contact holes are formed, and after performing a reflow process, a source made of Al that makes ohmic contact with the source region (31) and the drain region (32). An electrode (34) and a drain electrode (35) are formed. In this way, the intended MOS transistor (36) having the LDD structure shown in FIG. 1D is obtained.

According to the MOS transistor (36) having the LDD structure having such a configuration, the low-concentration impurity region (32a) is formed only on the drain region (32) side, and the low-concentration impurity region is not formed on the source region (31) side. The resistance on the source side is reduced, and the current driving capability can be improved. The first region is formed on the low-concentration impurity region (32a) of the drain region (32).
Gate electrode (26B) integrated with the first gate electrode (26A)
Is formed, the second gate electrode (26B)
Thereby, the carrier concentration on the surface of the low-concentration impurity region (32a) can be controlled, and the initial deterioration of the MOS transistor can be reduced.

Regarding the manufacturing process, the number of resist masks (28) for ion-implanting the low-concentration n-type impurity (29) shown in FIG. 1B is increased by one in comparison with a normal LDD structure MOS transistor. However, when applied to a C-MOS transistor, the number of masks does not increase. That is, in the manufacturing process of the C-MOS transistor, a p-type well region (42) is usually formed in a predetermined region of one main surface of an n-type silicon substrate (41) as shown in FIG. Gate electrodes (45) and (46) made of a polycrystalline silicon film are formed in a region (42) and a p-channel MOS transistor formation region (43) on an n-type substrate (41) via a gate insulating film (44), respectively. After that, for example, a p-channel MOS transistor formation region (43)
Is covered with a photoresist mask (28), and an n-channel MOS
A low-concentration n-type impurity (2) for forming a low-concentration impurity region on the side of the p-type well region (42) for forming the transistor.
9) is ion-implanted. (22) is an element isolation region,
(25) is an SiO ₂ film laminated on the gate electrode.

In the present invention, the photoresist mask (28) at this time is extended to a position over the gate electrode (46) of the n-channel MOS transistor formation region, that is, the p-type well region (42) as shown in FIG. Only a low concentration n-type impurity (29) is ion-implanted. In this way, the process of FIG. 1B described above can be obtained, and without increasing the number of masks, a C
-MOS transistors can be manufactured.

FIG. 3 shows another example of the present invention. In this example, a semiconductor substrate of the first conductivity type as shown in FIG.
A step portion (48) having a predetermined step d is formed on the main surface of the silicon substrate (21). Then, an element isolation region (22) is formed by selective oxidation by an ordinary method, and the upper step (48) is formed.
A), after forming a gate insulating film (24) of SiO ₂ etc. on the surface over the step side wall (48C) and the step lower part (48B), apply a polycrystalline silicon film (49) to be the gate electrode on the entire surface Form.

Next, RIE (Reactive Ion Etching) is performed on the polycrystalline silicon film (49) to leave the polycrystalline silicon film (49) only on the side wall of the step portion. Is introduced to reduce the resistance to form the gate electrode (49G) shown in FIG. 3B.

Next, as shown in FIG. 3C, using the gate electrode (49G) as a mask, a low-concentration n is formed on the upper (48A) and lower (48B) steps.
3D is deeply implanted, followed by FIG.
A shallow ion implantation of a high concentration n-type impurity (30) is performed as shown in FIG.

Thereafter, an annealing process for activation is performed, and the gate electrodes (49A) and 49 (B) are formed on the upper part (48A) and the lower part (48B) of the step part, respectively.
An n-type drain region (32) and an n-type source region (31) are formed in self-alignment with G).

The drain region (32) is a shallow high-concentration impurity region (32b)
And a low concentration impurity region (32a) thereunder, and the source region (31) is similarly composed of a shallow high concentration impurity region (31b) and a low concentration impurity region (31a) thereunder (third region).
(See FIG. E). However, in this case, the portion immediately below the gate electrode (49G) below the step portion is a substantial channel region (50), and therefore there is a low concentration impurity region (32a) in contact with the channel region (50) only in the drain region (32). , Source area (31)
In this case, the low concentration impurity region substantially in contact with the channel region (50) does not exist.

Next, an interlayer insulating film (32) is formed, source and drain contact holes are formed, and a reflow process is performed. Then, a source electrode (34) and a drain electrode (3) made of Al are formed.
5) Form. Thus, the desired L shown in FIG.
A DD structure MOS transistor (51) is obtained.

According to the MOS transistor (51) having the LDD structure having such a configuration, the low-concentration impurity region (32a) is formed deeper than the high-concentration impurity region (32b) on the side of the drain region (32) above the step portion. However, on the side of the source region (31) below the step portion, the low concentration impurity region (31a) is located immediately below the high concentration impurity region (31b) and the channel region (50)
And there is substantially no low-concentration impurity region. Therefore, the resistance on the source side is reduced, and the current driving capability of the transistor can be improved.

Further, since the drain region (32) is formed in the upper part of the step portion and the gate electrode (49G) is formed on the side wall of the step portion facing the low concentration impurity region (32a), the low concentration impurity region is formed by the gate electrode (49G). The surface carrier concentration of (32a) can be adjusted. Initial deterioration due to hot carriers can be reduced.

In addition, since the side wall (side wall) of the polycrystalline silicon film formed by RIE is used as the gate electrode (49G) by utilizing the stepped portion, the gate length can be reduced, and the fineness can be reduced.
A MOS transistor can be formed.

Further, since the drain region (32) is formed in the upper part of the step portion, and the channel region (50) and the source region (31) are formed in the lower portion of the step portion, the drain region (32) is changed to the source region (3).
1) The depletion layer hardly extends to the side, and punch-through hardly occurs.

〔The invention's effect〕

According to the semiconductor device of the present invention, a gate electrode including the first and second gate electrodes is formed, and a high-concentration impurity region serving as a source and a drain is formed in a self-aligned manner with the second gate electrode. Since only the low-concentration impurity region is formed only under the second gate electrode on the side, the resistance on the source side can be reduced, and the current driving capability of the transistor having the LDD structure can be improved. The carrier concentration on the surface of the low-concentration impurity region can be controlled, and initial deterioration can be reduced.

According to the manufacturing method of the present invention, the source side is covered with the mask layer over the first gate electrode to form a low-concentration impurity region on the drain side, and then the second gate electrode is formed on both side walls of the first gate electrode. Since the gate electrode is integrally formed and the high concentration impurity region is formed using the gate electrode as a mask, the semiconductor device can be easily manufactured. Further, in this manufacturing method, if the MOS transistor formation region of the first conductivity type channel is masked by the mask layer used for forming the low concentration impurity region on the side of the MOS transistor of the second conductivity type channel, the number of steps, ie, the number of mask steps A C-MOS transistor having the above configuration can be easily formed without increasing the number of transistors.

Further, according to the semiconductor device of the present invention, the gate electrode is formed on the side wall of the step formed on the semiconductor substrate, and the high-concentration impurity region is formed in the upper and lower steps of the step in a self-aligned manner with the gate electrode. In both cases, since the low-concentration impurity regions are formed below the high-concentration impurity regions in the upper stage, the current driving capability of the transistor having the LDD structure can be improved and the initial deterioration can be reduced. In addition, generation of punch-through between the source and the drain can be controlled, and a fine transistor with a small channel length can be formed.

[Brief description of the drawings]

1A to 1D are cross-sectional views in the order of steps showing an example of a MOS transistor according to the present invention. FIG. 2 is a cross-sectional view showing an example of steps when the present invention is applied to a method of manufacturing a C-MOS transistor. 4A to 4E are cross-sectional views of another example of a MOS transistor according to the present invention in the order of steps, FIG. 4 is a cross-sectional view of a conventional MOS transistor, and FIGS. FIG. 6 is a sectional view showing an example of a process sequence, and FIG. 6 is a conventional LDD.
It is sectional drawing which shows the example of a manufacturing method of the C-MOS transistor of a structure. (21) is a semiconductor substrate, (24) is a gate insulating film, (26)
[(26A) and (26B)] are gate electrodes, (31) is a source region, (32) is a drain region, (32a) is a low concentration impurity region, and (32b) is a high concentration impurity region.

Claims (4)

(57) [Claims] 1. A gate electrode formed on a semiconductor substrate of a first conductivity type, comprising a first gate electrode and a second gate electrode integrally formed on a side wall of the first gate electrode. Only a low-concentration impurity region of the second conductivity type is formed only in the semiconductor substrate below the second gate electrode, and a high-concentration impurity region of the second conductivity type is formed in self-alignment with the second gate electrode. Semiconductor device. 2. A first conductive type semiconductor substrate formed on a first conductive type semiconductor substrate.
Forming a mask layer covering the source side and having an opening on the drain side across the gate electrode, forming a low-concentration impurity region of the second conductivity type on the drain side via the mask layer; A second gate electrode is integrally formed on the side wall of the gate electrode, and a high-concentration impurity region is introduced using the first gate electrode and the second gate electrode as a mask to form a high-concentration impurity region of the second conductivity type. A method for manufacturing a semiconductor device, comprising: 3. The semiconductor device according to claim 2, wherein the MOS transistor formation region of the first conductivity type channel is masked by a mask layer used when forming the second conductivity type low concentration impurity region. Method. 4. A gate electrode is formed on the side wall of the step formed on the semiconductor substrate, and a high-concentration impurity region is formed in a self-aligned manner with the gate electrode on the upper and lower steps of the step. A semiconductor device in which a low concentration impurity region is formed below an impurity region.