JP2001044437A - Mos transistor and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shallowly form a source region and a drain region of a MOS transistor, while suppressing leakage current. SOLUTION: After a first gate electrode 10A is formed on an SOI substrate 50, an amorphous silicon film, grown over the entire surface, is patterned on the SOI substrate 50. An nMOS source electrode 18 and an nMOS drain electrode 19 are formed on side regions, respectively, of the first gate electrode 10A on the SOI substrate 50, and the electrode is implanted with arsenic ions. With the SOI substrate 50 thermally processed, the arsenic ions implanted in the nMOS source electrode 18 and nMOS drain electrode 19 are diffused in the SOI substrate 50, to form an n-type high-concentration source region 23A and n-type high-concentration drain region 23B.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, in the field of semiconductor devices, rapid miniaturization or low power consumption has been progressing. Therefore, in a MOS transistor, along with horizontal miniaturization, that is, reduction in design rules, vertical miniaturization, or It has become important to make the diffusion layer shallow (shallow junction).

FIG. 9 shows a conventional method of manufacturing a MOS transistor, specifically, a method of manufacturing a CMOS transistor.
This will be described with reference to FIG.

[0004] First, as shown in FIG.
01, a shallow trench isolation 102 is formed in an n-channel MOS transistor formation region (hereinafter, referred to as an n-channel MOS transistor formation region).
R _nmos and p-channel MO
S transistor forming region (hereinafter, referred to as pMOS forming region) after defining R _pmos respectively, pMOS forming region to form the nMOS threshold value control layer 103 and the p-type well layer 104 in the nMOS forming region R _nmos R _pmos , PMOS threshold control layer 105 and n-type well layer 10
6, a first gate electrode 108A made of a polysilicon film is formed on the nMOS formation region R _nmos via a first gate oxide film 107A, and pM
A second gate oxide film 107B on the OS formation region R _pmos
Gate electrode 10 made of a polysilicon film through
8B is formed. Next, using the first gate electrode 108A as a mask, an n-type impurity is ion-implanted obliquely into the nMOS formation region R _nmos so that the n-type low-concentration source region 10 is formed.
9A and the n-type low concentration drain region 109B are formed, and the pMO is formed using the second gate electrode 108B as a mask.
After forming a p-type low concentration source region 110A and a p-type low concentration drain region 110B by ion-implanting a p-type impurity obliquely into the S formation region R _pmos , a TEOS film is formed on the side surface of the first gate electrode 108A. Is formed, and the second gate electrode 1 is formed.
A second side wall 111B made of a TEOS film is formed on the side surface of the substrate 08B.

Next, as shown in FIG. 10, an n-type impurity is ion-implanted into the nMOS formation region R _{nmos by} using the first gate electrode 108A and the first side wall 111A as a mask to form an n-type high-concentration source. The region 112A and the n-type high concentration drain region 112B are formed, and the second gate electrode 108B and the second side wall 111B are formed.
The p-type high-concentration source region 113A and the p-type high-concentration drain region 113B are formed by ion-implanting p-type impurities into the pMOS formation region R _pmos using
Of the second gate electrode 108B
Above, above the n-type high-concentration source region 112A, above the n-type high-concentration drain region 112B, and above the p-type high-concentration source region 11.
A silicon layer 114 is selectively epitaxially grown on 3A and on the p-type high concentration drain region 113B. Thereafter, although not shown, the silicon layer 114
After depositing a metal film thereon, heat treatment is performed on the metal film to silicide the silicon layer 114. Thereby, the first gate electrode 108A and the second gate electrode 1
08B, the n-type high-concentration source region 112A, the n-type high-concentration drain region 112B, the p-type high-concentration source region 113A, and the region in contact with the silicon layer 114 in each of the p-type high-concentration drain regions 113B are silicided.

[0006]

By the way, in order to form a shallow diffusion layer, in other words, to form a source region and a drain region shallowly, the above-described method for forming a source region and a drain region by ion implantation has been proposed. Alternatively, after selectively growing an epitaxial layer in a region on the side of the gate electrode on the semiconductor substrate, impurities are implanted into the epitaxial layer, and then the impurities contained in the epitaxial layer are diffused into the semiconductor substrate by heat treatment. A method of forming a source region and a drain region in such a manner is used. The structure of the MOS transistor formed by this method is called an elevated source / drain structure or a lift-up source / drain structure.

However, an epitaxial layer (eg, FIG. 10) is formed in a region on the semiconductor substrate beside the gate electrode.
When the silicon layer 114 is selectively grown, a region (hereinafter, referred to as a facet) having a plane orientation of (111) is formed. As a result, the epitaxial layer and the gate electrode (on the side surface of the gate electrode) are formed. A groove (see region A in FIG. 10) is generated between the groove (including the formed sidewall) and a cause of a leak current occurs. On the other hand, if the growth of the epitaxial layer is promoted in order to eliminate the above-mentioned groove, element isolation (for example, the shallow trench isolation 1 shown in FIG. 10) is performed.
02), a footing of the epitaxial layer occurs (see region B in FIG. 10), resulting in a so-called bridge, which causes a leak current.

Further, in order to obtain a practically sufficient growth rate of the epitaxial layer, it is necessary to perform epitaxial growth at a high temperature of about 1000 ° C. or higher. Since impurities contained in the concentration source region or the low concentration drain region are diffused, there is a problem (short channel effect) that the gate length is reduced and the threshold voltage is rapidly lowered.

In some cases, the selectivity cannot be ensured depending on the growth conditions for growing the epitaxial layer.
Abnormal growth of the epitaxial layer may occur.

Further, when a polysilicon film is epitaxially grown in a region beside a gate electrode on a semiconductor substrate to form a lift-up source / drain structure, a polysilicon film is formed between the polysilicon film and the semiconductor substrate. When the interfacial oxide film is reduced, abnormal growth of the polysilicon film is likely to occur. On the other hand, if the interface oxide film formed between the polysilicon film and the semiconductor substrate is left as it is, when the polysilicon film is silicided, the region in contact with the polysilicon film in the source region or the drain region is uniformly formed. It cannot be silicided. That is, a region that is not silicided occurs on the surface of the source region or the surface of the drain region.

In view of the above problems, an object of the present invention is to make it possible to form a source region and a drain region of a MOS transistor shallowly while suppressing a leakage current.

[0012]

In order to achieve the above object, a MOS transistor according to the present invention has a gate electrode formed on a semiconductor substrate and a gate electrode formed on a region of the semiconductor substrate beside the gate electrode. A source electrode and a drain electrode, and a source region and a drain region respectively formed in a region below the source electrode and a region below the drain electrode in the semiconductor substrate. Amorphous silicon film formed at least on the side region of the gate electrode is formed by patterning,
The source region and the drain region are formed by diffusing impurities implanted in the source electrode and the drain electrode into the semiconductor substrate.

According to the MOS transistor of the present invention, the source electrode and the drain electrode are formed by patterning the amorphous silicon film formed at least on the side of the gate electrode on the semiconductor substrate. It is possible to prevent a situation in which a facet is formed when the amorphous silicon film is formed and a groove is formed between the amorphous silicon film and the gate electrode, or a situation in which a bridge is generated due to a footing of the amorphous silicon film on element isolation. Therefore, by diffusing the impurities implanted into the source electrode and the drain electrode into the semiconductor substrate, the source region and the drain region can be formed shallow while suppressing a leak current.

In the MOS transistor according to the present invention, the source electrode and the drain electrode are preferably silicided.

In this case, the resistance of the source electrode and the drain electrode can be reduced.

In the MOS transistor according to the present invention, the semiconductor substrate is preferably an SOI substrate.

In this way, the parasitic capacitance of the MOS transistor can be reduced.

According to the method of manufacturing a MOS transistor of the present invention, a step of forming a gate electrode on a semiconductor substrate, a step of growing an amorphous silicon film at least in a region on a side of the gate electrode on the semiconductor substrate, Patterning the film to form a source electrode and a drain electrode in regions on the semiconductor substrate beside the gate electrode, implanting impurities into the source electrode and the drain electrode, and subjecting the semiconductor substrate to a heat treatment. Forming a source region and a drain region by diffusing the impurities implanted into the source electrode and the drain electrode into a region below the source electrode and a region below the drain electrode in the semiconductor substrate, respectively. And

According to the method for manufacturing a MOS transistor of the present invention, after an amorphous silicon film is grown on at least a region on a side of a gate electrode on a semiconductor substrate,
Since the amorphous silicon film is patterned to form a source electrode and a drain electrode, a facet is formed during the growth of the amorphous silicon film and a groove is formed between the amorphous silicon film and the gate electrode. A situation in which a bridge is generated due to the footing of the silicon film can be prevented. Therefore,
By diffusing impurities implanted into the source electrode and the drain electrode into the semiconductor substrate, the source region and the drain region can be formed shallow while suppressing leakage current.

In the method of manufacturing a MOS transistor according to the present invention, after the step of forming the source region and the drain region, a metal film is deposited on the source electrode and the drain electrode, and the metal film is subjected to a heat treatment. Preferably, the method further includes the step of silicidizing the source electrode and the drain electrode.

With this configuration, the resistance of the source electrode and the drain electrode can be reduced.

In the method of manufacturing a MOS transistor according to the present invention, a step of removing an oxide film formed on the surface of the semiconductor substrate is further provided between the step of forming the gate electrode and the step of growing the amorphous silicon film. Preferably, the step of growing the amorphous silicon film preferably includes a step of putting the semiconductor substrate into a heat treatment furnace maintained at a temperature of about 400 ° C. or lower and then growing the amorphous silicon film.

By doing so, the interfacial oxide film formed between the semiconductor substrate and the amorphous silicon film can be reduced while preventing abnormal growth of the amorphous silicon film, so that the contact between the source electrode and the source region can be reduced. Resistance and the contact resistance between the drain electrode and the drain region can be reduced, and when the source electrode and the drain electrode are silicided, the region in contact with the source electrode in the source region and the region in contact with the drain electrode in the drain region are reduced. It can be uniformly silicidized.

In the method for manufacturing a MOS transistor according to the present invention, a low-concentration source region and a low-concentration source region are formed in a region on the side of the gate electrode in the semiconductor substrate between the step of forming the gate electrode and the step of growing the amorphous silicon film. Forming a drain region, and forming a sidewall on a side surface of the gate electrode;
The step of growing the amorphous silicon film preferably includes a step of growing the amorphous silicon film at a temperature of about 500 to 550 ° C.

With this configuration, the diffusion of impurities contained in the low-concentration source region and the low-concentration drain region can be prevented, so that the short channel effect can be suppressed.

In the method of manufacturing a MOS transistor according to the present invention, a step of forming a sidewall on a side surface of the gate electrode is further provided between the step of forming the gate electrode and the step of growing the amorphous silicon film. Growing the amorphous silicon film on the semiconductor substrate including on the gate electrode, and forming the source electrode and the drain electrode comprises forming the amorphous silicon film on the side wall of the amorphous silicon film. It is preferable to include a step of patterning so as to overlap with.

This makes it possible to reliably prevent a situation in which a groove is formed between the amorphous silicon film and the gate electrode.

In the method of manufacturing a MOS transistor according to the present invention, a first insulating film is grown on a semiconductor substrate including on a gate electrode between a step of forming a gate electrode and a step of growing an amorphous silicon film. The step of causing
Forming a sidewall made of a second insulating film on the side surface of the gate electrode with the first insulating film interposed therebetween, and removing a portion of the first insulating film exposed above the semiconductor substrate to form a gate electrode; Forming an opening in a region surrounded by the sidewalls above, wherein the step of growing the amorphous silicon film includes the step of growing the amorphous silicon film on a semiconductor substrate including a portion above the gate electrode. Forming a source electrode and a drain electrode may include forming a gate upper electrode on the gate electrode by patterning the amorphous silicon film so that the amorphous silicon film remains in the opening. preferable.

In this manner, the gate upper electrode can be formed when forming the source electrode and the drain electrode.

When the gate upper electrode is formed, it is preferable that the first insulating film is a silicon oxide film and the second insulating film is a silicon nitride film.

With this configuration, since the silicon nitride film has etching selectivity with respect to the silicon oxide film, the sidewall made of the second insulating film is removed when the first insulating film is removed. Can be prevented.

In the method for manufacturing a MOS transistor according to the present invention, the semiconductor substrate is preferably an SOI substrate.

With this arrangement, the parasitic capacitance of the MOS transistor can be reduced.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a MOS transistor according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS.
This will be described with reference to FIG.

First, as shown in FIG.
A BOX oxide film 2 formed on a silicon substrate 1;
A shallow trench isolation 4 is formed in a predetermined region of the SOI substrate 50 including the silicon layer 3 formed on the BOX oxide film 2.
_Are formed to define an nMOS formation region R _nmos and a pMOS formation region R _pmos , respectively.

Next, after a resist pattern (not shown) having an opening in the nMOS formation region R _nmos is formed on the SOI substrate 50, ions are implanted into the nMOS formation region R _nmos using the resist pattern as a mask. Then, the nMOS threshold value control layer 5 and the p-type well layer 6 are sequentially formed. After a resist pattern (not shown) having an opening in the pMOS formation region R _pmos is formed on the SOI substrate 50, ions are implanted into the pMOS formation region R _pmos using the resist pattern as a mask, and the pMOS A threshold control layer 7 and an n-type well layer 8 are sequentially formed.

Next, after a silicon oxide film and a polysilicon film having a thickness of, for example, 3 nm are sequentially grown over the entire surface of the SOI substrate 50, a resist covering the gate electrode formation region is formed on the polysilicon film. A pattern (not shown) is formed, and thereafter, the polysilicon film and the silicon oxide film are sequentially subjected to dry etching using the resist pattern as a mask to form a third silicon oxide film on the nMOS formation region R _nmos . A first gate electrode 10A made of a polysilicon film via one gate oxide film 9A
_Is formed, and a second gate electrode 10B made of a polysilicon film is formed on the pMOS formation region R _pmos via a second gate oxide film 9B made of a silicon oxide film.

Next, as shown in FIG. 2, the S including the upper part of the first gate electrode 10A and the upper part of the second gate electrode 10B is formed.
Over the entire surface of the OI substrate 50, for example, a film thickness of 30 nm
After the TEOS film 11 is grown, the first gate electrode 1
0A is used as a mask and nMOS formation region R _{nmos is} n
The n-type low-concentration source region 12A and the n-type low-concentration drain region 12B are formed by obliquely ion-implanting a p-type impurity, and the pM
A p-type impurity is ion-implanted obliquely into the OS formation region R _pmos to form a p-type low-concentration source region 13A and a p-type low-concentration drain region 13B.

Next, after a silicon nitride film having a thickness of, for example, 200 nm is grown on the entire surface of the TEOS film 11, the silicon nitride film is etched back by dry etching. As shown, a first sidewall 14A made of a silicon nitride film is formed on a side surface of a first gate electrode 10A via a TEOS film 11, and silicon is formed on a side surface of a second gate electrode 10B via a TEOS film 11. A second sidewall 14B made of a nitride film is formed. The silicon nitride film is TEOS
It has etching selectivity with respect to the film 11.

Next, as shown in FIG. 4, wet etching is performed on the TEOS film 11 using the first side wall 14A and the second side wall 14B as a mask, so that the TEOS film 11 Remove the part exposed to the. As a result, a first opening 15A is formed in a region on the first gate electrode 10A surrounded by the first sidewall 14A, and a second sidewall 14B on the second gate electrode 10B is formed. The second opening 15B is formed in a region surrounded by
Is formed.

Next, after the oxide film (natural oxide film or the like, not shown) formed on the surface of the SOI substrate 50 is completely removed by wet etching, the SOI substrate 50 is
It is put into a heat treatment furnace maintained at a temperature of about 00 ° C. or less, and then, as shown in FIG.
An amorphous silicon film 16 having a thickness of, for example, 40 nm is grown at a temperature of about 500 to 550 ° C., for example, 530 ° C. over the entire surface of the SOI substrate 50 including the upper part A and the second gate electrode 10B. Thereby, the interfacial oxide film formed between the amorphous silicon film 16 and the SOI substrate 50 can be reduced.

Next, after forming a resist film over the entire surface of the amorphous silicon film 16, the resist film is patterned by lithography to form a resist pattern 17 as shown in FIG. That is,
On the nMOS formation region R _nmos , the resist pattern 17 is
Is formed in a region on the side of the gate electrode 10A so as to overlap with the first sidewall 14A.
On the pMOS formation region R _pmos , the resist pattern 17 is
Is formed so as to overlap the second side wall 14B in a region on the side of the gate electrode 10B.

Next, the amorphous silicon film 16 is dry-etched using the resist pattern 17 as a mask, thereby forming an nMOS source electrode 18 and an nMOS drain electrode 19 made of the amorphous silicon film 16 as shown in FIG. To the nMOS formation region R
_The pMOS source electrode 20 and the pMOS drain electrode 21 formed on the _nmos and the amorphous silicon film 16 are formed on the pMOS formation region R _pmos . At this time, the nMOS source electrode 18 and the nMOS drain electrode 19 are formed on the SOI substrate 50 in a region beside the first gate electrode 10A.
4A, and the pMOS source electrode 20 and the pMOS drain electrode 21 are formed on the SOI substrate 50 in a region on the side of the second gate electrode 10B. It is formed so as to overlap with the wall 14B. Further, the amorphous silicon film 16 is formed by the first opening 15A and the second opening 1
By patterning so as to remain in 5B,
The first gate upper electrode 2 is formed on the first gate electrode 10A.
2A are formed, and a second gate upper electrode 22B is formed on the second gate electrode 10B.

Next, after forming a resist pattern (not shown) having openings in the nMOS source electrode 18 and the nMOS drain electrode 19 on the SOI substrate 50, the nMOS source electrode 18 and the nMOS source electrode 18 are formed using the resist pattern as a mask. An n-type impurity, for example, arsenic ion is accelerated to the nMOS drain electrode 19 at an acceleration energy of 30 Ke.
Ions are implanted under the conditions of V and a dose of 3.0 × 10 ¹⁵ / cm ² .

Next, after a resist pattern (not shown) having openings in the pMOS source electrode 20 and the pMOS drain electrode 21 is formed on the SOI substrate 50, the pMOS source electrode 20 and the pMOS source electrode 20 are formed using the resist pattern as a mask. A p-type impurity, for example, BF ₂ ion is accelerated to the pMOS drain electrode 21 at an acceleration energy of 20 Ke.
V ions are implanted under the conditions of a dose of 2.0 × 10 ¹⁵ / cm ² .

Next, for example, 1
RTA (rapid heat treatment) is performed at 000 ° C. for 10 seconds. As a result, the arsenic ions contained in the nMOS source electrode 18 are converted into _nMO in the nMOS formation region R _nmos .
The n-type high-concentration source region 23A is formed by diffusing into the region below the S source electrode 18, and the arsenic ions contained in the nMOS drain electrode 19 are _{converted to} the nMOS drain electrode 19 in the nMOS formation region R _nmos . Is diffused into the lower region to form n-type high-concentration drain region 23B. The BF included in the pMOS source electrode 20
₂ ions form the pMOS in the pMOS formation region R _pmos
Is diffused into the region below the source electrode 20 for p-type, the p-type high-concentration source region 24A is formed, and the BF ₂ ions contained in the drain electrode 21 for pMOS are converted into the drain electrode 21 for pMOS in the pMOS formation region R _pmos . Is diffused into the region below the p-type high concentration drain region 24B.

Next, the source electrode for nMOS 18, nMO
After depositing a cobalt film on the drain electrode 19 for S, the source electrode 20 for pMOS, and the drain electrode 21 for pMOS, a heat treatment is performed on the cobalt film, as shown in FIG. NM
A source silicide electrode for OS 25, a drain silicide electrode for nMOS, a source silicide electrode for pMOS 27, and a drain silicide electrode for pMOS are formed. Further, by depositing the above-mentioned cobalt film on the first gate upper electrode 22A and the second gate upper electrode 22B and performing a heat treatment, each gate upper electrode is silicided to form the first gate upper silicide electrode. 29A and a second upper gate silicide electrode 29B are formed.
At this time, the region of the first gate electrode 10A in contact with the first gate upper electrode 22A, the second gate electrode 10A
B, a region in contact with the second gate upper electrode 22B;
a region in contact with the nMOS source electrode 18 in the n-type high-concentration source region 23A, an n-type high-concentration drain region 23B
In the region in contact with the drain electrode 19 for nMOS, p
Of the p-type high-concentration source region 24A in contact with the pMOS source electrode 20, and the p-type high-concentration drain region 24
The region of B in contact with the pMOS drain electrode 21 is also silicided and becomes a part of each silicide electrode.

According to the present embodiment, after the amorphous silicon film 16 is grown over the entire surface of the SOI substrate 50, the amorphous silicon film 16 is patterned to form an nMOS source electrode 18 and an nMOS drain electrode 19. In order to form the source electrode 20 for pMOS and the drain electrode 21 for pMOS, a facet is formed at the time of growth of the amorphous silicon film 16 and the gap between the amorphous silicon film 16 and the first gate electrode 10A or the second gate electrode 10B is formed. Or the amorphous silicon film 16 on the shallow trench isolation 4
A bridge can be prevented from occurring due to the hemming.
Therefore, the n-type impurity implanted into the nMOS source electrode 18 and the nMOS drain electrode 19 is diffused into the nMOS formation region R _nmos , and the pMOS source electrode 20.
By diffusing the p-type impurity implanted into the pMOS drain electrode 21 into the pMOS formation region R _pmos ,
While suppressing the leak current, the n-type high concentration source region 23A,
The n-type high-concentration drain region 23B, the p-type high-concentration source region 24A, and the p-type high-concentration drain region 24B can be formed shallowly.

According to the present embodiment, the nMOS source electrode 18, the nMOS drain electrode 19, the pMOS
After depositing a cobalt film on the source electrode 20 for pMOS and the drain electrode 21 for pMOS, heat treatment is performed on the cobalt film to silicide each source electrode and drain electrode. The resistance can be reduced.

According to the present embodiment, the SOI substrate 5
After removing the oxide film formed on the surface of
The substrate 50 is put into a heat treatment furnace maintained at a temperature of about 400 ° C. or lower, and then the amorphous silicon film 16 is grown on the SOI substrate 50. SOI substrate 5
0 and the amorphous silicon film 16 can be reduced in the interfacial oxide film.
Resistance between the nMOS drain electrode 19 and the n-type high-concentration drain region 23B, the contact resistance between the nMOS drain electrode 19 and the n-type high-concentration drain region 23B, and the contact resistance between the pMOS source electrode 20 and the p-type high-concentration source region 24A. The contact resistance between the pMOS drain electrode 21 and the p-type high-concentration drain region 24B can be reduced. Further, the nMOS source electrode 18, the nMOS drain electrode 19, the pMOS source electrode 20, and the pMO
When the S drain electrode 21 is silicided, a region in contact with the nMOS source electrode 18 in the n-type high-concentration source region 23A, a region in contact with the nMOS drain electrode 19 in the n-type high-concentration drain region 23B, and a p-type high concentration PMOS source electrode 2 in source region 24A
The region in contact with 0 and the region in contact with the pMOS drain electrode 21 in the p-type high-concentration drain region 24B can be uniformly silicidized.

Further, according to the present embodiment, the nMOS formation
Region R_nmosThe n-type low concentration source region 12A and the n-type low concentration
The drain region 12B and the pMOS formation region.
Area R _pmosThe p-type low concentration source region 13A and the p-type low concentration
After forming the drain region 13B, the first gate electrode 1
When the first sidewall 14A is formed on the side of 0A
In both cases, the second sidewall is provided on the side surface of the second gate electrode 10B.
14B, and then an amorphous silicon film
16 at a temperature of about 500 to 550 ° C.
n-type low concentration source region 12A, n-type low concentration drain region
12B, p-type low concentration source region 13A, and p-type low concentration
The impurities contained in the drain region 13B are diffused.
To prevent short-circuit effects
can do.

Further, according to the present embodiment, after forming the first sidewall 14A on the side surface of the first gate electrode 10A and forming the second sidewall 14B on the side surface of the second gate electrode 10B, First gate electrode 10
Growing an amorphous silicon film 16 on the SOI substrate 50 including on the first gate electrode A and the second gate electrode 10B;
Then, in order to pattern the amorphous silicon film 16 so that the amorphous silicon film 16 overlaps the first sidewall 14A and the second sidewall 14B, the amorphous silicon film 16 and the first gate electrode 10A or the first A situation in which a groove is formed between the second gate electrode 10B and the second gate electrode 10B can be reliably prevented.

According to the present embodiment, after the TEOS film 11 is grown on the SOI substrate 50 including on the first gate electrode 10A and on the second gate electrode 10B,
First sidewall 14A made of a silicon nitride film on the side surface of first gate electrode 10A via TEOS film 11
And TE on the side surface of the second gate electrode 10B.
A second sidewall 14B made of a silicon nitride film is formed with the OS film 11 interposed therebetween, and thereafter, a portion of the TEOS film 11 exposed on the SOI substrate 50 is removed, thereby forming a portion on the first gate electrode 10A. A first opening 15A is formed in a region surrounded by the first sidewall 14A, and a second opening 15B is formed in a region surrounded by the second sidewall 14B on the second gate electrode 10B. To form At this time, since the silicon nitride film has an etching selectivity with respect to the TEOS film 11, when removing the TEOS film 11, the first sidewall 14A and the second sidewall 14B are removed.
The first opening 15 can be prevented from being removed.
A and the second opening 15B can be reliably formed. Therefore, after the amorphous silicon film 16 is grown on the SOI substrate 50 including the first gate electrode 10A and the second gate electrode 10B, the amorphous silicon film 16 is By patterning so as to remain in the first opening 15A and the second opening 15B, the source electrode 18 for nMOS,
Drain electrode 19 for nMOS, source electrode 2 for pMOS
0 and when forming the pMOS drain electrode 21,
The first gate upper electrode 2 is formed on the first gate electrode 10A.
2A can be formed, and the second gate upper electrode 22B can be formed on the second gate electrode 10B.

Further, according to the present embodiment, since the SOI substrate 50 is used as the semiconductor substrate, the parasitic capacitance of the MOS transistor can be reduced.

In this embodiment, a CMOS transistor having a lift-up source / drain structure is formed. Instead, an n-channel MOS transistor having a lift-up source / drain structure or a p-channel MOS transistor is formed.
Even when only an OS transistor is formed, or a BiCMO comprising a CMOS transistor having a raised source / drain structure and a bipolar transistor
The same effect can be obtained when an S transistor is formed.

In this embodiment, the SOI substrate is used as the semiconductor substrate. However, the same effect can be obtained when a silicon substrate or the like is used instead.

In this embodiment, sidewalls made of a silicon nitride film are formed on the side surfaces of the first gate electrode 10A and the side surfaces of the second gate electrode 10B with the TEOS film 11 interposed therebetween. Instead, another silicon oxide film having etching selectivity with respect to the silicon nitride film may be used.

[0058]

According to the present invention, a facet is formed during the growth of an amorphous silicon film to form a groove between the amorphous silicon film and the gate electrode, or a footing of the amorphous silicon film occurs on element isolation. Since the occurrence of a bridge can be prevented, the impurities injected into the source electrode and the drain electrode made of the amorphous silicon film are diffused into the semiconductor substrate, so that the source region and the drain region are formed shallow while suppressing the leak current. be able to.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one step of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 5 is a sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 6 is a sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 8 is a sectional view showing one step of a method for manufacturing a semiconductor device according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

FIG. 10 is a cross-sectional view showing one step of a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 BOX oxide film 3 silicon layer 4 shallow trench isolation 5 threshold control layer for nMOS 6 p-type well layer 7 threshold control layer for pMOS 8 n-type well layer 9A first gate oxide film 9B second Gate oxide film 10A first gate electrode 10B second gate electrode 11 TEOS film 12A n-type low-concentration source region 12B n-type low-concentration drain region 13A p-type low-concentration source region 13B p-type low-concentration drain region 14A first 14B Second sidewall 15A First opening 15B Second opening 16 Amorphous silicon film 17 Resist pattern 18 nMOS source electrode 19 nMOS drain electrode 20 pMOS source electrode 21 pMOS drain electrode 22A 1 gate upper electrode 22B 2nd gate Upper electrode 23A n-type high-concentration source region 23B n-type high-concentration drain region 24A p-type high-concentration source region 24B p-type high-concentration drain region 25 nMOS source silicide electrode 26 nMOS drain silicide electrode 27 pMOS source silicide electrode 28 pMOS Drain silicide electrode 29A First gate upper silicide electrode 29B Second gate upper silicide electrode 50 SOI substrate R _nmos nMOS formation region R _pmos pMOS formation region

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Claims (11)

[Claims] A gate electrode formed on a semiconductor substrate; a source electrode and a drain electrode formed in regions on the semiconductor substrate beside the gate electrode; and a lower portion of the source electrode on the semiconductor substrate. A source region and a drain region formed in a region below the drain electrode and a region below the drain electrode, respectively, wherein the source electrode and the drain electrode are formed at least in a region on the semiconductor substrate beside the gate electrode. The formed amorphous silicon film is formed by patterning, and the source region and the drain region are formed by diffusing impurities implanted in the source electrode and the drain electrode into the semiconductor substrate. Characteristic MOS transistor. 2. The MOS transistor according to claim 1, wherein the source electrode and the drain electrode are silicided. 3. The MOS transistor according to claim 1, wherein said semiconductor substrate is an SOI substrate. A step of forming a gate electrode on the semiconductor substrate; a step of growing an amorphous silicon film on at least a region of the semiconductor substrate on a side of the gate electrode; and patterning the amorphous silicon film; Forming a source electrode and a drain electrode in a region on the side of the gate electrode on the semiconductor substrate; implanting impurities into the source electrode and the drain electrode; and performing a heat treatment on the semiconductor substrate Thereby, the impurities injected into the source electrode and the drain electrode
Forming a source region and a drain region by diffusing into a region below the source electrode and a region below the drain electrode in the semiconductor substrate, respectively. Method. 5. After the step of forming the source region and the drain region, after depositing a metal film on the source electrode and the drain electrode, a heat treatment is performed on the metal film to form the source electrode and the drain electrode. 5. The method according to claim 4, further comprising the step of silicidizing the electrode.
3. The method for manufacturing a MOS transistor according to 1. 6. The method according to claim 1, further comprising a step of removing an oxide film formed on a surface of the semiconductor substrate between the step of forming the gate electrode and the step of growing the amorphous silicon film. 5. The method according to claim 4, wherein the step of growing comprises a step of, after putting the semiconductor substrate into a heat treatment furnace maintained at a temperature of about 400 ° C. or less, growing the amorphous silicon film. A method for manufacturing a MOS transistor. 7. A low-concentration source region and a low-concentration drain region are respectively formed in a region of the semiconductor substrate beside the gate electrode between the step of forming the gate electrode and the step of growing the amorphous silicon film. Forming an amorphous silicon film at a temperature of about 500 to 550 ° C., further comprising: forming a sidewall on a side surface of the gate electrode; and forming the amorphous silicon film at a temperature of about 500 to 550 ° C. 5. The method for manufacturing a MOS transistor according to claim 4, wherein: 8. A step of forming a sidewall on a side surface of the gate electrode between the step of forming the gate electrode and the step of growing the amorphous silicon film, wherein the step of growing the amorphous silicon film Includes a step of growing the amorphous silicon film on the semiconductor substrate including the upper part of the gate electrode. The step of forming the source electrode and the drain electrode includes the step of forming the amorphous silicon film and the step of forming the amorphous silicon film. 5. The method according to claim 4, further comprising the step of patterning so as to overlap with the sidewall. 9. A step of growing a first insulating film on the semiconductor substrate including on the gate electrode, between the step of forming the gate electrode and the step of growing the amorphous silicon film; Forming a sidewall made of a second insulating film on a side surface of the gate electrode with the first insulating film interposed therebetween, and removing a portion of the first insulating film exposed on the semiconductor substrate; Forming an opening in a region on the gate electrode surrounded by the sidewall, wherein the step of growing the amorphous silicon film comprises: Forming the source electrode and the drain electrode in the amorphous silicon film. Scan the silicon film is patterned so as to leave the opening, a manufacturing method of a MOS transistor according to claim 4, characterized in that it comprises a step of forming a gate upper electrode on the gate electrode. 10. The method according to claim 9, wherein the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. 11. The method according to claim 4, wherein the semiconductor substrate is an SOI substrate.