JPH0652738B2 - Insulated gate type field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an insulated gate field effect transistor, and more particularly to a transistor structure having a low impurity concentration layer near a gate electrode in a drain region.

[Technical background of the invention and its problems]

In recent years, high integration of semiconductor integrated circuits and miniaturization of elements have been remarkable. In an integrated circuit using an insulated gate field effect transistor (hereinafter, simply referred to as a MOS transistor), the element is particularly miniaturized, so that the electric field strength inside the element is very large. In such a MOS transistor, carriers in the channel are accelerated by a strong electric field, and high energy carriers are generated in the vicinity of the drain region, and trapped in the gate insulating film, the threshold voltage and transconductance are increased. It will change. This is called the hot carrier effect. This effect significantly impairs the device characteristics, and thus the characteristics of the integrated circuit using such an element.

As a countermeasure against this hot carrier effect, a transistor structure has been proposed in which a low impurity concentration layer is provided in the drain region near the gate electrode. One of them is a so-called LDD (Lightly Doped Drain) structure. When this LDD structure is used, the strong electric field in the vicinity of the drain region is relaxed due to the existence of the low impurity concentration layer at the end of the drain region, and as a result, the generation of hot carriers is suppressed.

However, in this MOS transistor having the LDD structure, the change in threshold voltage can be reduced to some extent by suppressing the hot carrier effect, but the effect of suppressing the amount of change in transconductance is not recognized so much. This is because if hot carriers generated near the drain are trapped in the insulating film on the side wall of the gate electrode, the electrostatic force pushes the channel current down the substrate, increasing the effective series resistance. is there.

[Object of the Invention]

The present invention has been made in view of the above points, and an object thereof is to provide a highly reliable MOS transistor capable of suppressing a decrease in mutual conductance due to a hot carrier effect.

[Outline of Invention]

The MOS transistor according to the present invention is an insulated gate field effect transistor having a low impurity concentration layer in the vicinity of a gate electrode in a drain region, wherein the low impurity concentration layer holds a charge having a polarity opposite to that of majority carriers in the drain region. A layer is provided, and a first insulating film is provided to separate the charging layer from the gate electrode and the low impurity concentration layer,
A second side wall of the gate electrode is formed to cover the charging layer.
Is provided.

〔The invention's effect〕

In the MOS transistor according to the present invention, the electrostatic force of the charging layer maintains the channel current path in the vicinity of the drain on the surface of the substrate and suppresses the decrease in mutual conductance. Even if hot carriers are trapped in the gate electrode sidewall insulating film near the drain due to the hot carrier effect, they recombine with charges of opposite polarity in the charging layer, so that the channel current flows downward from the substrate surface. It takes time to be pushed to. Therefore, the deterioration rate of the mutual conductance is slower than that of the conventional structure, and the reliability can be improved accordingly.

Example of Invention

 First, a reference example will be described.

FIG. 1 shows an LDD structure MOS transistor of one reference example. Reference numeral 11 denotes a p-type Si substrate, on which a gate electrode 1 made of a polycrystalline silicon film with a gate insulating film 12 interposed therebetween.
3 is formed. The source / drain regions are formed by diffusing the n ⁻ -type layers 14 and 15 which are low impurity concentration layers diffused using the gate electrode 13 as a mask and the insulating film 19 left on the sidewalls of the gate electrode 13 as a mask. It is composed of n ⁺ type layers 16 and 17 having an impurity concentration.
In this embodiment, in such an LDD structure, the charging layer 18 holding a positive charge is provided in contact with at least the surface of the n ⁻ type layer 15 on the drain side.

FIGS. 2A to 2E are examples of manufacturing steps for obtaining such a structure. A gate electrode 13 made of a polycrystalline silicon film is formed on a p-type Si substrate 11 through a gate insulating film 12 by thermal oxidation according to a well-known process, and ion implantation is performed using the gate electrode 13 as a mask to self-align with the gate electrode 13. N ⁻ type layers 14 and 15 are formed ((a
)). Next, the positively charged layer 18 is formed on the entire surface ((b)). This charging layer is a silicon nitride film formed by the CVD method in this reference example. It is known that a silicon nitride film formed by CVD is naturally charged with positive charges during its deposition. After that, a silicon oxide film 19 is deposited on the entire surface by the CVD method ((c)). Then, the laminated film of the silicon oxide film 19 and the silicon nitride film 18 is entirely etched by an anisotropic etching method such as RIE, and this is left only on the side wall of the gate electrode 13 ((d)). Then, ion implantation is performed using the gate electrode 13 and the silicon oxide film 19 on the side wall thereof as a mask to form high impurity concentration n ⁺ type layers 16 and 17 in the source and drain regions ((e)).

According to this manufacturing process, the charging layer 18 is symmetrically formed not only on the drain side but also on the source side. The source side charging layer is omitted in FIG. 1 because it is essentially useless on the source side where a high electric field is not applied. However, providing a charging layer on both sides in this way has the advantage that it is effective regardless of which is used as the source or drain in the integrated circuit.

In the MOS transistor of this reference example, n on the drain side
^The positively charged layer 18 provided on the ⁻ type layer 15 suppresses a decrease in mutual conductance due to the hot electron effect, and improves reliability in the case of miniaturization.

FIG. 3 shows an LDD structure MOS transistor according to an embodiment of the present invention. The basic structure is the same as that of FIG. 1, and therefore the parts corresponding to those of FIG. 1 are denoted by the same reference numerals as in FIG. 1 differs from that of FIG. 1 in that the charging layer 18 is formed in contact with the surface of the n ⁺ -type layer in FIG. 1, whereas in this embodiment the charging layer 18 is formed via a thin insulating film 20. Is being formed.

4A to 4E show an example of the manufacturing process of this MOS transistor. This manufacturing process is also basically the same as FIG. 2 (a) to (e) of the above-mentioned reference example, and therefore FIG.
Parts corresponding to (e) are assigned the same reference numerals and detailed explanations thereof are omitted. The difference from the previous manufacturing process is the fourth
In FIG. 6B, the silicon oxide film 20 is previously formed as a thin insulating film by thermal oxidation or the like before forming the charging layer 18.

Also in this embodiment, the electrostatic force due to the charging layer 18 works to attract the current flowing through the n ⁻ -type layer 15 on the drain side to the surface through the insulating film 20, and therefore the same effect as the above-mentioned reference example can be obtained. .

The present invention is not limited to the above embodiments. For example, other than the silicon nitride film formed by CVD as the charging layer, another material that is similarly positively charged at the time of deposition can be used. In the case of a p-channel MOS transistor, a charging layer may be used as a charging layer. After forming the film as the charging layer,
It is also possible to use one that is forcibly charged by an ion beam or an electron beam. In the case of the structure of the embodiment shown in FIG. 3, a conductive layer such as a polycrystalline silicon film may be used as the charging layer.

In addition, although the case of the LDD structure has been described in the embodiment, another structure having a low impurity concentration layer near the drain, for example, GDD.
The present invention can be similarly applied to a MOS transistor having a (Graded and Diffused Drain) structure. Further, in the embodiment, the low impurity concentration layer near the drain and the source is formed shallow, but the present invention is also effective when it is deeper than the high impurity concentration layer.

[Brief description of drawings]

FIG. 1 is a diagram showing a MOS transistor according to a reference example of the present invention, and FIGS. 2 (a) to 2 (e) are diagrams showing an example of the manufacturing process thereof.
FIG. 3 is a diagram showing a MOS transistor of one embodiment, FIG.
Drawing (a)-(e) is a figure showing the example of the manufacturing process. 11 ... p-type Si substrate, 12 ... gate insulating film, 13 ...
... Gate electrode, 14, 15 ... n ^- type layer (low impurity concentration layer), 16,17 ... n ⁺ -type layer (high non-native object concentration layer), 1
8 ... Positively charged layer (CVD silicon nitride film), 19,
20 ... Silicon oxide film.

Claims (2)

[Claims] 1. An insulated gate field effect transistor having a low impurity concentration layer near a gate electrode in a drain region, wherein a charging layer holding a charge having a polarity opposite to that of majority carriers in the drain region is provided on the low impurity concentration layer. A first insulating film is provided to separate the charging layer from the gate electrode and the low impurity concentration layer, and a second insulating film is formed on a side wall of the gate electrode to cover the charging layer.
2. An insulated gate field effect transistor, characterized in that a gate side wall insulating film is constituted by the first insulating film, the charging layer and the second insulating film. 2. The insulated gate field effect transistor according to claim 1, wherein the charging layer is a silicon nitride film deposited by a CVD method.