JPH06268215A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the irregularity in threshold value due to the fluctuation in thickness of a semiconductor layer, and to improve the mobility of the semiconductor layer by a method wherein the region of channel edge of a thin film SOI is formed at high density, and the region is prevented from depletion even when an inverted layer is formed. CONSTITUTION:An element isolation region 18 is formed on a semiconductor layer 3 which is formed on an oxide film 2, and then the semiconductor layer is doped at low density by conducting ion-implanting and annealing operations. A gate oxide film 7 is formed by oxidation, and after polysilicon has been deposited and doped, it is processed into a required size, and a gate electrode 6 is formed. Then, a high density region 4 is formed using the gate electrode as a mask. The region 4 is formed in such a manner that the semiconductor layer is not depleted even when an inverted layer is formed and also it is formed in the size of 1.4X10<17>/cm<3> so that the threshold value can be determined by conductive impurity density. Then, a source/drain diffusion layer region 5 is formed by ion-implanting arsenic, and an interlayer insulating film 9 and a metal electrode 10 are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device formed on a semiconductor layer on an insulating film, and more particularly to a MIS type device which aims to improve the mobility by suppressing the threshold variation due to the film thickness variation of the semiconductor layer. The present invention relates to a semiconductor device.

[0002]

2. Description of the Related Art SOI (Silic
on On Insulatar), the operation principle is the same for other semiconductor materials. The thin-film SOI MOS transistor (FIG. 2) in which the semiconductor layer on the insulating film is extremely thin and the semiconductor layer in the channel region is completely depleted when the MOS inversion layer is formed is used for suppressing the punch-through, improving the mobility, and improving the junction capacitance. There are effects such as reduction. However, the thin film SOI semiconductor layer 3
The thickness is extremely thin, about 0.1 μm, so it is difficult to control the thickness, and there is a variation of about ± 0.02 μm. Since the threshold value of the thin film SOI is determined by the amount of charge in the fully depleted channel region, it varies depending on the thickness of the semiconductor layer 3 as long as it is in the fully depleted state. That is, the amount of charges contained increases in proportion to the thickness of the semiconductor layer 3, and the threshold value increases in accordance with the amount of charges. Therefore, there is a problem in that the amount of charge in the channel region changes due to the variation in the film thickness of the semiconductor layer 3 due to the fluctuation of the manufacturing process, and the threshold value varies. FIG. 3 shows the semiconductor layer thickness dependence of the threshold value of the thin film SOI. The concentration of the semiconductor layer 3 is 2.2 × 10
^When it is set to ¹⁷ / cm ³ , the semiconductor layer has a thickness of 5 in order to set the threshold value to 0.2 V in the fully depleted state.
It is necessary to set the thickness to 5 nm, and if the film thickness fluctuates by about ± 0.02 μm, the threshold value fluctuates by ± 0.1 V. This variation in threshold value causes problems such as large fluctuations in circuit speed and defective circuit operation when a circuit formed of MOS transistors is operated at a low voltage.

An example of measures against variations in threshold in thin film SOI is disclosed in Japanese Patent Laid-Open No. 3-297171. Conductive impurities are introduced into the thin film semiconductor layer 3 by low energy ion implantation,
By introducing conductive impurities only into the inside of the semiconductor layer, the entire charge is controlled. According to this method, the amount of conductive impurities in the channel is constant regardless of the variation in the thickness of the semiconductor layer 3, so that the threshold value does not depend on the thickness of the semiconductor layer as long as it is completely depleted. This method can accurately control the threshold value of the thin film SOI without changing the device structure, but it is technically difficult to implant ions only inside the semiconductor having a thickness of 0.1 μm.

[0004]

The conventional thin film SOI has a problem that the threshold value varies due to the variation in the thickness of the semiconductor layer on the insulating film.

An object of the present invention is to reduce the threshold variation due to the variation of the semiconductor layer thickness by devising the device structure of the thin film SOI, and to further improve the mobility.
Type semiconductor device.

[0006]

The above object is to increase the concentration of the region 4 at the channel end of the thin film SOI to form an inversion layer in this region as shown in the basic embodiment of the present invention (FIG. 1). Do not completely deplete the time. That is, since the threshold value of this region is determined by the conductive impurity concentration,
The threshold can be determined regardless of the thickness of the thin film semiconductor. Since the threshold value is determined at the channel edge, the other channel regions 3 are completely depleted to reduce punch-through and have an extremely low concentration to reduce impurity scattering to improve mobility.

[0007]

The threshold of the thin film SOI depends on the SOI film thickness because the channel region is completely depleted. Therefore, a region not completely depleted is provided and the threshold position is determined in that region. By doing so, a threshold value independent of the SOI film thickness can be obtained. In the basic embodiment of the present invention (FIG. 1), the concentration of the region 4 at the channel end is set to a concentration at which the threshold value becomes a predetermined value without being completely depleted. In this embodiment, as shown in FIG. 3, the SOI film thickness is set to 120 nm and the channel edge concentration is 1.4 × 10 4.
^{It is set to 17} / cm ^{3 so} as not to be in a fully depleted state including fluctuations in the SOI film thickness (FIG. 3). Therefore, the threshold value of this region does not depend on the SOI film thickness, and a constant threshold value can be obtained. On the other hand, since the region 3 at the center of the channel is completely depleted, a low concentration (1 × 10 ¹⁶ / cm 2
³ ) is set. The threshold value is extremely lower than that of the region 4 at the channel end and does not become a factor that determines the threshold value of the entire transistor. Further, since the semiconductor layer 3 is completely depleted from the surface to the interface with the insulating film 2, punch-through can be suppressed, and since the amount of conductive impurities is small, impurity scattering is small and high mobility can be achieved.

[0008]

FIG. 1 shows a first embodiment of the present invention. First, an element isolation region 8 is formed on the semiconductor layer 3 (thickness: 120 nm) formed on the oxide film 2 by a wafer bonding method or the like.
It is formed by OCOS oxidation, and then the semiconductor layer is made to have a low concentration (1 × 10 ¹⁶ / cm 2) by ion implantation and annealing.
³ ) Dope. Forming the gate oxide film 7 by oxidation,
A gate electrode 6 is formed by depositing polysilicon and doping it by ion implantation and then processing it to a required size. After that, the high-concentration region 4 is formed in a self-aligned manner by oblique ion implantation of boron using the gate electrode 6 as a mask. The concentration of the region 4 is set to 1.4 × 10 ¹⁷ / cm ³ so that the semiconductor layer is not completely depleted even when the inversion layer is formed and the threshold value can be determined only by the concentration of the conductive impurities (FIG. 3).
However, at the channel end, part of the charge in the depletion layer is dominated by the source / drain electric field due to the effect of the electric field due to the source / drain.
It has a higher concentration than the structure. After that, the source / drain diffusion layer region 5 is formed by ion implantation of arsenic, and the interlayer insulating film 9 and the metal electrode 10 are formed according to the usual method for forming a MIS type semiconductor device. According to this embodiment, the threshold value is determined in the region 4, so that the threshold value does not change even if the thickness of the semiconductor layer changes from 100 nm to 140 nm. In addition, the channel central region 4 is 1 × 10 ¹⁶ / c
Since the concentration is as low as m ³ , it is possible to completely deplete and suppress punch through, and to improve mobility by relaxing the electric field and reducing impurity scattering at the interface of the gate oxide film 7.

Next, a second embodiment is shown in FIG. In order to determine the threshold without completely depleting the channel edge,
The buried layer 11 having a high concentration is provided, and the semiconductor layer surface at the channel end is set to have a low concentration. The high-concentration buried layer 11 is formed by oblique ion implantation using the gate electrode 6 as a mask. The energy of ion implantation is increased to set the concentration distribution peak at the interface between the semiconductor layer and the oxide film 2. There is. According to this embodiment, a threshold value independent of the thickness of the semiconductor layer can be obtained, and since the surface of the channel end also has a low concentration, a decrease in mobility is suppressed and the mobility of the transistor as a whole is further improved. be able to.

A third embodiment of the present invention is shown in FIG. In this embodiment, the high concentration layer 4 is provided only on the source side to control the threshold value. According to this structure, the threshold value is determined by the high-concentration region 4 on the source side, so that a constant threshold value can be obtained regardless of variations in the thickness of the semiconductor layer, and the junction capacitance between the drain and the channel region 3 Can be reduced. Even if the high-concentration buried layer 11 is provided only on the source side as in the second embodiment, the same effect can be obtained.

Next, FIG. 6 shows a fourth embodiment in which a CMOS structure is formed by using the present invention, and FIG. 7 shows a forming method thereof.
Normally, CMOS of the substrate requires a well region for element isolation, but in the thin film SOI, the underlying oxide film 2 and the element isolation region 8 are used.
Since the element is completely insulated and isolated, the well is unnecessary. After forming the element isolation region 8, ion implantation is distributed by a mask when the semiconductor layer is doped N
The MOS region 3 is p-type and the PMOS region 12 is n-type (FIG. 7a). After forming the gate oxide film, polysilicon is deposited and arsenic is implanted into the NMOS region 6 to become n-type polysilicon, and boron is implanted into the PMOS region 15 to p.
Shaped polysilicon. Then, the polysilicon is processed into a gate having a required size, and high-concentration regions 4 and 14 are formed by oblique ion implantation using the gate electrode as a mask (FIG. 7B). Here, the same buried layer as in the second embodiment can be formed by increasing the energy of oblique ion implantation. Next, arsenic is ion-implanted in the NMOS region and boron is ion-implanted in the PMOS region to form source / drain regions (5, 13) (FIG. 7c).
After that, the wiring process is completed by a normal process (FIG. 7d). According to the present embodiment, it is possible to provide an SOI-CMOS integrated circuit in which the circuit performance changes little even if the semiconductor layer thickness changes.

Next, FIG. 8 shows a fifth embodiment in which the present invention is applied to a double gate SOI. In the thin film SOI, a double gate SOI structure in which the back gate electrode 16 is provided below the channel region may be used. In this case, since the channel region is controlled by the two gates, the depletion layer at the time of forming the inversion layer extends from both upper and lower sides of the channel region.
Therefore, the semiconductor layer is completely depleted even if it is twice as thick as the one-sided gate. Even in this case, the principle that the threshold varies depending on the thickness of the semiconductor layer does not change. In this embodiment, since the total concentration of the depletion layer at the time of forming the inversion layer is smaller than the thickness of the semiconductor layer due to the high concentration region 4 at the channel end, the region is not completely depleted and the threshold value is the conductive impurity concentration. Is determined by. In addition, since the central portion 3 of the channel is completely depleted at a low concentration, punch-through can be suppressed and mobility can be improved. The formation method is as follows. First, after forming the element isolation region 8 gate oxide film 17 and the gate electrode 16 on a normal substrate, the oxide film 2 is formed by deposition. Next, the insulating film 2 is faced down and bonded to another semiconductor substrate 1. The semiconductor layer is polished and thinned using the element isolation region 8 as a stopper. Next, the gate oxide film 7 and the gate electrode 6 are formed, and the high concentration region 4 is formed by oblique ion implantation. After that, the interlayer film 9 and the electrode 10 are formed by a normal wiring process. According to the present embodiment, it is possible to provide a MOS transistor having a large driving current without variation in the threshold value due to the variation in the film thickness of the semiconductor layer even in the double gate SOI.

Next, FIG. 9 shows a sixth embodiment in which the present invention is applied to a vertical type thin film SOI. A normal semiconductor substrate 1 is processed by dry etching to form a thin wall (active region), and a double gate SOI type MOS transistor is formed in the region. The gate electrodes are formed on both sides of the wall so that current flows in the vertical direction. Also in the present embodiment, the wall thickness varies depending on the precision of dry etching, and the threshold value varies. By forming the high-concentration region 4 at the channel end, this region is not completely depleted, and the threshold value can be determined by the impurity concentration. Further, the other channel regions 3 are made to have a low concentration to be completely depleted, so that punch-through can be suppressed and the mobility can be improved. First, the high-concentration regions 4 are formed on the semiconductor substrate 1 by changing the ion implantation energy. Next, a thin active region is formed by dry etching while leaving the active region to be a transistor. After forming the gate oxide film 7 by oxidation, polysilicon is deposited on the entire surface and dry etching is performed to form a gate electrode on the sidewall of the active region. Next, when high-concentration ion implantation of arsenic is performed, source / drain regions 5 are formed in a self-aligned manner on the top of the active layer and the substrate. After that, by the normal wiring process,
The interlayer film 9 and the electrode 10 are formed. According to the present embodiment, it is possible to provide a MOS transistor having a large driving current without variations in threshold value due to variations in the film thickness of the semiconductor layer even in the vertical double-gate SOI.

An example of a circuit using the present invention is shown in FIG. Since the transistor of the present invention has a small threshold variation, it can be stably operated even in a circuit such as a differential amplifier in which the threshold variation directly affects the output offset voltage.

The field effect transistor of each embodiment of the present invention can obtain high mobility by operating at a low temperature of 200 K or less.

[0016]

As described above, according to the present invention, the variation in the threshold value due to the variation in the thickness of the semiconductor layer of the thin film SOI is reduced, and the mobility is improved to enable the high speed operation. The dependency of the threshold voltage on the semiconductor layer film pressure is shown in FIG. 3. In the conventional case, the threshold value is ± 20 nm due to the film thickness variation of ± 20 nm.
In contrast to the fluctuation of 0.1 V, there is no fluctuation of the threshold value in this embodiment. In the conventional example, the threshold value fluctuates ± 0.1 V over the entire channel length due to the variation in the semiconductor layer thickness, whereas in the present invention, the threshold value does not change even if the semiconductor layer thickness fluctuates. (FIG. 11). Also, in the present invention, the lowering of the threshold value (short channel effect) in the short channel has the same performance as that of the conventional fully depleted SOI.

[Brief description of drawings]

1 shows a basic embodiment of the invention.

FIG. 2 shows an example of a conventional thin film SOI structure.

FIG. 3 shows a semiconductor layer film thickness dependence of a threshold value in a thin film SOI type MOS transistor.

FIG. 4 shows a second embodiment using a high-concentration buried layer.

FIG. 5 shows a third embodiment in which a high concentration region is provided only on the source side.

FIG. 6 shows a fourth embodiment in which the present invention is applied to a CMOS structure.

FIG. 7 shows a forming method according to a fourth embodiment of the present invention.

FIG. 8 shows a fifth embodiment in which the present invention is applied to a double gate SOI.

FIG. 9 shows a sixth embodiment in which the present invention is applied to the vertical SOI.

FIG. 10 shows an example of a differential amplifier circuit using the present invention.

FIG. 11 shows the effect of the present invention on the channel length dependence of the threshold value.

[Explanation of symbols]

1 ... Semiconductor substrate, 2 ... Base oxide film, 3 ... Channel region p
Type semiconductor layer, 4 ... Channel end p type semiconductor layer, 5 ... N type source / drain diffusion layer, 6 ... N type polysilicon gate electrode, 7 ... Gate oxide film, 8 ... Field oxide film, 9 ... Interlayer insulating film, Reference numeral 10 ... Aluminum electrode layer, 11 ... Channel end p-type high-concentration buried layer, 12 ... Channel region n-type semiconductor layer, 13
... p-type source / drain diffusion layer, 14 ... channel end n-type semiconductor layer, 15 ... p-type polysilicon gate electrode, 16 ...
n-type polysilicon back gate electrode, 17 ... Back gate oxide film.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Koichi Seki, Koichi Seki 1-280, Higashi Koikekubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (5)

[Claims] 1. In a MIS type semiconductor device formed in a semiconductor layer on an insulating film, the concentration of conductive impurities at the channel edge of the semiconductor device is increased so that the thickness of the depletion layer when the inversion layer is formed is the thickness of the semiconductor layer. And the other channel regions are completely depleted from the surface of the semiconductor layer to the interface with the insulating film due to the spread of the depletion layer during formation of the inversion layer. . 2. A depletion layer at the time of forming an inversion layer by providing a buried layer having a high conductive impurity concentration in a region deeper than a surface of a channel end of the semiconductor device in a MIS type semiconductor device formed on a semiconductor layer on an insulating film. Is set to be smaller than the thickness of the semiconductor layer on the insulating film, and the other channel regions are separated from the surface of the semiconductor layer by the expansion of the depletion layer during the formation of the inversion layer, and the film interface with the insulation is formed. A semiconductor device characterized by being completely depleted. 3. A semiconductor device according to claim 1, wherein the high concentration region or the high concentration buried layer is provided only on one side of a channel end. 4. A semiconductor integrated circuit using the MIS type semiconductor device according to any one of claims 1 to 3. 5. The MIS type semiconductor device and the semiconductor integrated circuit according to claim 1, which are operated at a low temperature of 200 K or less.