JPH05102179A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain the title semiconductor device wherein its resistance value of an LDD region is reduced, its current driving power is high and its operating speed is high by a method wherein fixed electric charges having opposite conductivity type to that of a channel are introduced into an insulating film on the sidewall of a gate corresponding to the upper part of the LDD region or into the interface between the insulating film and a semiconductor substrate. CONSTITUTION:A gate region provided with a gate insulating film 3 and a gate electrode 4 which are laminated on a semiconductor substrate 1 is formed; a source region and drain region 7, 8 are formed on both sides of the gate region. In such a MOS field-effect transistor, fixed positive charges 9 in the case of an n-channel MOS field-effect transistor or fixed negative charges in the case of a p-channel MOS field-effect transistor are contained in an insulating film 6 at the sidewall part of the gate or in the interface between the insulating film 6 at the sidewall part of the gate and the semiconductor substrate 1. For example, fixed electric charges is introduced when the insulating film on the sidewall of a gate is deposited, or ions of Cs or the like are implanted after a gate electrode has been formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro semiconductor device, and more particularly to a MOS field effect transistor.

[0002]

2. Description of the Related Art Conventionally, high integration and high performance of Si MOS integrated circuits have been achieved by miniaturization of elements.
In particular, shortening the gate length is extremely important not only for reducing the element area but also for improving the current driving force of the element and thus for improving the operation speed. On this occasion,
In a region with a gate length of 1 μm or less, in order to prevent the so-called short channel effect and to secure the drain breakdown voltage and hot carrier reliability, the source and drain regions are parallel to each other and have the same conductivity type as the source and drain regions. A region having a low impurity concentration is provided. So-called Lightl
A y-doped Drain (LDD) structure is adopted. However, even if the channel length is miniaturized, the length of the LDD region is from the viewpoint of suppressing electric field concentration and the short channel effect at the drain end, and from the viewpoint of manufacturing difficulty and securing a margin. , Can't scale well. In addition, in order to suppress the short channel effect, it is necessary to keep the pn junction depth of this LDD region low, so that the impurity concentration in this region cannot be made sufficiently high. As a result of this,
If the thickness is about 0.3 μm or less, the ratio of the resistance component of the LDD region to the total resistance of the MOSFET increases, so that there is a problem that the increase in drain current and the improvement in operating speed due to the reduction in channel length cannot be expected.

[0003]

As described above, in the MOSFET using the LDD of the conventional type, the length of the LDD region cannot be shortened sufficiently as the gate length is shortened. The ratio of the total resistance increases, and as a result, the drain current does not increase, and there is a problem in that an improvement in operating speed cannot be expected in the ultrafine region.

[0004]

According to the semiconductor device of the present invention, a channel is formed in the gate sidewall insulating film corresponding to the upper part of the LDD region or at the interface between this insulating film and the semiconductor substrate forming the LDD region. Basically, it includes a MOSFET characterized in that a fixed charge having a sign opposite to the conductivity type is introduced.

[0005]

According to the present invention, positive fixed charges are formed on the n-type LDD region in the case of the n-channel MOSFET, and negative fixed charges are formed on the p-type LDD region in the case of the p-channel MOSFET. Has been done. Therefore, since the carrier accumulation layer is electrostatically formed on the surface of the LDD region,
Compared with the case where there is no fixed charge, the carrier concentration in the LDD region becomes higher, and the resistance in the LDD region is reduced. If an attempt is made to increase the carriers in the LDD region by increasing the amount of ions implanted during the formation of the LDD layer, the pn junction depth also becomes deep and causes a short channel effect. It is due to the generated electrostatic potential, and its influence only affects the very surface of the semiconductor, so that the short channel effect is not brought about.

The formation of the fixed charges described above can be realized by a method of introducing into the film at the time of depositing the gate side wall insulating film, a method of implanting ions such as cesium after forming the gate electrode, and in any case LDD consistently
Since a fixed charge can be formed on the region, the channel portion is not affected, which is advantageous.

[0007]

EXAMPLES Examples of the present invention will be described below. Figure 1
FIG. 2 is a sectional view showing an embodiment of an n-channel MOSFET according to the present invention. FIG. 2 is a p-channel MOSF according to the present invention.
It is sectional drawing which shows one Example of ET. Here, each of (a) shows a case where electric charges exist in the interface, and (b) shows a case where electric charges exist in the sidewall insulating film.

First, FIG. 1 will be described. An element isolation oxide film 2 is formed on a p-type silicon substrate 1, and a gate electrode 4 of an n-channel MOSFET is formed via a gate insulating film 3. A post oxide film 5 is formed on both sides of the gate electrode and the surface of the gate electrode, and side wall insulating films 6 are arranged on both sides of the gate electrode. Self-aligned to these,
n-type LDD (Lightly doped drain)
n) Region 7 and high-concentration n-type source / drain region 8 are formed. Here, in FIG.
And the LDD region 7 are provided with a positive charge 9, and in the side wall insulating film 6 in FIG. MOSFE
The substrate on which T is formed is covered with an insulating film 10, which is opened on the source / drain region 8 and a metal electrode 11 is formed.

Next, FIG. 2 will be described. The element isolation oxide film 2 is formed on the n-type silicon substrate 12, and the gate insulating film 3 is formed.
The gate electrode 4 of the p-channel MOSFET is formed via the. A post oxide film 5 is formed on both sides of the gate electrode and the surface of the gate electrode, and side wall insulating films 6 are arranged on both sides of the gate electrode. Self-aligned with these, p-type LDD (Lightly doped dr)
an ain) region 13 and a high-concentration p-type source / drain region 14 are formed. Here, in the figure (a), the negative charge 15 is generated at the interface between the post oxide film 5 and the LDD region 13.
In the diagram (b), the negative charges 15 are arranged in the sidewall insulating film 6. The substrate on which the MOSFET is formed is covered with an insulating film 10, which is the source / drain region 14
The metal electrode 11 is formed by opening above.

The above-mentioned positive charge 9 or negative charge 15 can be typically formed by the following method. (1) An element such as cesium which forms a fixed charge in an oxide film or at an interface between the oxide film and a semiconductor is ion-implanted. (Ion-implanted cesium becomes a positive charge in a silicon oxide film. Devices, ED-34 (1987) 2
8). (2) Fixed charges are trapped in the insulating film when the sidewall insulating film is deposited. (3) After forming the sidewall insulating film, rapid thermal nitriding or plasma nitriding is performed to form fixed charges in the insulating film. (4) After forming the MOSFET, a high voltage is applied between the source / drain and the gate for a short time to inject carriers to trap the carriers in the electron / hole traps in the insulating film.

3 to 9 are sectional views specifically showing the manufacturing steps of the method of forming fixed charges by ion implantation in the above-mentioned fixed charge forming method. A specific manufacturing process will be described with reference to these process sectional views.

First, the element isolation insulating film 2 is formed on the silicon substrate 1 in the same manner as in the normal MOS integrated circuit process, and polycrystalline silicon to be the gate electrode 4 is deposited by the thermal CVD method and patterned. Then, in order to form an LDD region, phosphorus is implanted with an energy of 20 KeV and a dose of 4 ×.
Ions are implanted under the condition of 10 ¹³ cm ^-2 (FIG. 3). afterwards,
A post oxide film is formed at 850 ° C. in dry oxygen (FIG. 4).
Next, cesium ion implantation for forming positive fixed charges is performed under the conditions of 20 KeV and 4 × 10 ¹² cm ⁻² (FIG. 5). After that, a silicon nitride film 17 to be a sidewall insulating film is deposited to 100 nm by a thermal CVD method (FIG. 6). next,
The silicon nitride film 17 is etched back by the RIE (reactive ion etching) method to leave the silicon nitride film 6 on the side wall of the gate (FIG. 7). After that, the ion implantation for forming the source / drain regions 8 is performed by using arsenic as the ion species, the implantation energy is 30 KeV, and the dose amount is 5 × 10 ¹⁵ cm.
Perform under the condition of ^-2 (Fig. 8). Finally, the silicon oxide film 10 is deposited by the CVD method, patterned, and then a metal thin film such as aluminum is deposited by the sputtering method. Further, by patterning this metal thin film, the electrode 1
1 is formed and completed (FIG. 9).

In this embodiment, the silicon nitride film is used as the side wall insulating film, but the present invention is not limited to this.
A silicon oxide film, a tantalum oxide film, or the like can be used as well.

[0014]

As described above, according to the present invention, in the LDD type MOSFET having an extremely fine channel length, the resistance value of the LDD region can be reduced without causing any adverse effect such as the short channel effect. Current driving force
A high operating speed can be realized.

[Brief description of drawings]

FIG. 1 is an n-channel MOSFET according to an embodiment of the present invention.
Sectional view of.

FIG. 2 is a p-channel MOSFET according to an embodiment of the present invention.
Sectional view of.

FIG. 3 is a sectional view of the same.

FIG. 4 is a sectional view of the same.

FIG. 5 is a sectional view of the same.

FIG. 6 is a sectional view of the same.

FIG. 7 is a sectional view of the same.

FIG. 8 is a sectional view of the same.

FIG. 9 is a sectional view of the same.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... P-type silicon substrate 2 ... Element isolation oxide film 3 ... Gate insulating film 4 ... Gate electrode 5 ... Post oxide film 6 ... Side wall insulating film 7 ... N-type LDD (Lightly doped dr)
ain) region 8 ... High-concentration n-type source / drain region 9 ... Positive fixed charge 10 ... Interlayer insulating film 11 ... Metal electrode 12 ... N-type silicon substrate 13 ... P-type LDD (Lightly doped d)
Rain region 14 ... High-concentration p-type source / drain region 15 ... Negative fixed charge 16 ... N-type ion implantation region 17 ... Silicon nitride film

Claims (2)

[Claims] 1. A MOS type field effect transistor having a gate region having a gate insulating film and a gate electrode laminated on a semiconductor substrate, and a source and drain regions formed on both sides of the gate region. A semiconductor device characterized in that a fixed positive charge is included in an n-channel MOS type field effect transistor and a fixed negative charge is included in a p-channel MOS type field effect transistor at an interface between the insulating film in the insulating film or the side wall of the gate and the semiconductor substrate. .. 2. A step of forming a gate insulating film on a semiconductor substrate, a step of forming a gate electrode on the gate insulating film, a step of forming an insulating film on a side wall portion of the gate electrode, and a side wall portion thereof. 2. A method for manufacturing a semiconductor device, comprising the step of: ion-implanting an element that becomes a fixed charge in the insulating film in the insulating film or on the side wall of the insulating film after forming a gate electrode.