JP2757491B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2757491B2 JP2757491B2 JP1251124A JP25112489A JP2757491B2 JP 2757491 B2 JP2757491 B2 JP 2757491B2 JP 1251124 A JP1251124 A JP 1251124A JP 25112489 A JP25112489 A JP 25112489A JP 2757491 B2 JP2757491 B2 JP 2757491B2
- Authority
- JP
- Japan
- Prior art keywords
- impurity
- region
- concentration
- semiconductor substrate
- channel portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 40
- 238000004519 manufacturing process Methods 0.000 title description 6
- 238000000034 method Methods 0.000 title description 4
- 239000012535 impurity Substances 0.000 claims description 75
- 239000000758 substrate Substances 0.000 claims description 23
- 238000005468 ion implantation Methods 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】 《産業上の利用分野》 この発明は、半導体装置の製造方法に関し、特に側壁
ゲート型MOSFETを有する半導体装置に適用して有効な技
術に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique which is effective when applied to a semiconductor device having a sidewall gate type MOSFET.
《従来の技術》 従来、第２図に示す側壁ゲート型MOSFETなどの半導体
装置は、一般に次のような工程を経て製造されている。
すなわち、まず半導体基板１の表面に凸部を設けてチャ
ネル部Ｃ、ソース電極相当部Ｓ′を形成した後、SiO2に
よりゲート絶縁膜２を形成する。次に高不純物濃度Ｎ型
半導体領域４をイオン打込みにより形成した後、ゲート
電極３を多結晶シリコンにより形成し、これにより側壁
ゲート型MOSFETが得られる。<< Prior Art >> Conventionally, a semiconductor device such as a sidewall gate type MOSFET shown in FIG. 2 is generally manufactured through the following steps.
That is, first, a convex portion is provided on the surface of the semiconductor substrate 1 to form a channel portion C and a source electrode equivalent portion S ′, and then the gate insulating film 2 is formed of SiO 2 . Next, after the high impurity concentration N-type semiconductor region 4 is formed by ion implantation, the gate electrode 3 is formed of polycrystalline silicon, whereby a sidewall gate type MOSFET is obtained.
このようにして得られた側壁ゲート型MOSFETは、半導
体基板１上の平坦面にチャネル部Ｃが設けられた平面ゲ
ート型MOSFETと異なり、半導体基板１に垂直な凸部側壁
面にチャネル部Ｃを有するため、単位MOSFETあたりの表
面投影面積が少なくなり、その分だけMOSFETの微細化、
高集積化を図ることができる。The sidewall gate type MOSFET thus obtained is different from the planar gate type MOSFET in which the channel portion C is provided on the flat surface on the semiconductor substrate 1 and the channel portion C is formed on the convex side wall surface perpendicular to the semiconductor substrate 1. As a result, the surface projected area per unit MOSFET is reduced, and the
High integration can be achieved.
なお、上記側壁ゲート型MOSFETに関しては「1988Inte
rnational Electron Devices Meeting （IEDM88）」予
稿集pp. 222−225等に報告されている。Regarding the above-mentioned sidewall gate type MOSFET, refer to 1988
rnational Electron Devices Meeting (IEDM88) "Proceedings pp. 222-225.
《発明が解決しようとする問題点》 しかしながら、このような従来の方法で製造された側
壁ゲート型MOSFETにあっては、チャネル部Ｃの上・下部
に隣接するソース電極Ｓ部およびドレイン電極Ｄ部の双
方が高不純物濃度領域４となっている。このため、MOSF
ET動作時におけるチャネル部Ｃの最大電界が大きくな
り、この電界によって発生するホットキャリアがゲート
電極３とチャネル部Ｃ間のゲート絶縁膜２によって捕獲
され、このことによってチャネル部Ｃに局所的な固定電
荷が発生する。その結果、この固定電荷によって生じる
チャネルＣの電界分布の異常に起因して、MOSFETの特性
劣化が生じ、ドレイン電流が減少するという問題点があ
った。<< Problems to be Solved by the Invention >> However, in the sidewall gate type MOSFET manufactured by such a conventional method, the source electrode S portion and the drain electrode D portion adjacent to the upper and lower portions of the channel portion C are provided. Are the high impurity concentration regions 4. Therefore, MOSF
The maximum electric field in the channel portion C during the ET operation increases, and hot carriers generated by this electric field are captured by the gate insulating film 2 between the gate electrode 3 and the channel portion C, thereby locally fixing the channel portion C. Charge is generated. As a result, there is a problem that the characteristics of the MOSFET deteriorate due to the abnormal electric field distribution of the channel C caused by the fixed charge, and the drain current decreases.
この発明は、このような従来の問題点に着目してされ
たもので、その目的は、ゲート電極下に低不純物濃度領
域を形成し、LDD （Lightly Doped Drain）構造を自己
整合的に形成することにより、ホットキャリアによる特
性劣化を防止し、ドレイン電流の減少を小さくできる半
導体装置の製造方法を提供することにある。The present invention has been made in view of such a conventional problem, and has as its object to form a low impurity concentration region under a gate electrode and form an LDD (Lightly Doped Drain) structure in a self-aligned manner. Accordingly, it is an object of the present invention to provide a method of manufacturing a semiconductor device capable of preventing deterioration of characteristics due to hot carriers and reducing a decrease in drain current.
《問題を解決するための手段》 この発明は、上記のような目的を達成するため、第１
導電形の半導体基板の突部側壁に沿って該半導体基板表
面に垂直にチャネル部を形成する工程と、 前記半導体基板上への第２導電形の第１不純物のイオ
ン打込みにより、前記半導体基板上の突部以外の平坦部
および前記突部の上面部に低不純物濃度の不純物層を形
成する工程と、 前記チャネル部の側壁面にゲート電極を形成した後、
このゲート電極をマスクとして、前記第１不純物のイオ
ン打込み深さより浅い第２導電形の第２不純物のイオン
打込みにより、前記低不純物濃度の不純物層より深さの
浅い高不純物濃度の不純物層を前記平坦部および前記上
面部に形成する工程と、 所定条件下で熱処理を行うことにより、前記平坦部の
高不純物濃度の不純物層をドレイン領域（またはソース
領域）とすると共に、前記上面部の高不純物濃度の不純
物層をソース領域（またはドレイン領域）とし、かつ、
前記ドレイン領域（またはソース領域）と前記チャネル
部との間および前記ソース領域（またはドレイン領域）
と前記チャネル部との間に、各々、低不純物濃度領域を
形成する工程と、 を含むことを特徴とする。<< Means for Solving the Problem >> In order to achieve the above object, the present invention
Forming a channel portion perpendicular to the surface of the semiconductor substrate along the projecting side wall of the semiconductor substrate of the conductivity type; and ion-implanting a first impurity of the second conductivity type onto the semiconductor substrate to form a channel on the semiconductor substrate. Forming an impurity layer having a low impurity concentration on a flat portion other than the protrusion and an upper surface of the protrusion, and after forming a gate electrode on a side wall surface of the channel portion,
By using this gate electrode as a mask, the high-impurity-concentration impurity layer, which is shallower than the low-impurity-concentration impurity layer, is ion-implanted with a second impurity of the second conductivity type, which is shallower than the ion-implantation depth of the first impurity. Forming a flat region and the upper surface portion, and performing a heat treatment under a predetermined condition so that the high impurity concentration impurity layer of the flat portion becomes a drain region (or a source region) and the high impurity concentration of the upper surface portion The impurity layer having a high concentration as a source region (or a drain region); and
Between the drain region (or source region) and the channel portion and the source region (or drain region)
Forming a low-impurity-concentration region between the semiconductor device and the channel portion, respectively.
《作用》 この発明によれば、上記第１の工程により第１導電形
の半導体基板の突部側壁に沿って該半導体基板表面に垂
直にチャネル部が形成され、上記第２工程により第２導
電形の第１不純物のイオン打込みによる低不純物納度領
域が前記半導体基板上の突部以外の平坦部および突部上
面部に形成され、上記第３工程によりゲート電極が形成
されると共に、このゲート電極をマスクとして前記第１
不純物のイオン打込み深さより浅くした第２導電形の第
２不純物のイオン打込みにより、前記平坦部および前記
突部上面部に前記低不純物濃度の不純物層より深さの浅
い高不純物濃度の不純物層が形成される。そして、上記
第４工程により所定条件下で熱処理を行うと、前記平坦
部の高不純物濃度不純物層がドレイン領域（またはソー
ス領域）とされると共に、前記突部上面部の高不純物濃
度不純物層がソース領域（またはドレイン領域）とさ
れ、かつ、ドレイン領域（またはソース領域）とチャネ
ル部との間、およびソース領域（またはドレイン領域）
とチャネル部との間に、各々、低不純物濃度領域が形成
される。<< Operation >> According to the present invention, a channel portion is formed perpendicularly to the surface of the semiconductor substrate along the projecting side wall of the semiconductor substrate of the first conductivity type in the first step, and the second conductive layer is formed in the second step. A low impurity acceptability region formed by ion implantation of a first impurity is formed on a flat portion other than the protrusion on the semiconductor substrate and on the upper surface of the protrusion. A gate electrode is formed in the third step and the gate electrode is formed. Using the electrodes as a mask, the first
By the ion implantation of the second impurity of the second conductivity type which is shallower than the ion implantation depth of the impurity, an impurity layer having a high impurity concentration which is shallower than the impurity layer having a low impurity concentration is formed on the flat portion and the upper surface of the protrusion. It is formed. When the heat treatment is performed under predetermined conditions in the fourth step, the high impurity concentration impurity layer on the flat portion becomes a drain region (or a source region), and the high impurity concentration impurity layer on the protrusion upper surface portion becomes A source region (or a drain region), between a drain region (or a source region) and a channel portion, and a source region (or a drain region)
A low impurity concentration region is formed between the gate electrode and the channel portion.
このため、ドレイン領域（またはソース領域）とチャ
ネル部との間、およびソース領域（またはドレイン領
域）とチャネル部との間に、各々、LDD構造が自己整合
的に形成されるので、動作時におけるチャネル部の電界
が従来のように大きくなることはなく、チャネル部に局
所的な固定電荷が生ずるのを防止する。その結果、固定
電荷に起因する特性劣化を防ぐことができる。また、ゲ
ート電極に印加する電界で低不純物濃度領域の伝導度を
変えるとによって低不純物濃度領域の抵抗を低下させ、
このことによって低不純物濃度領域の抵抗成分によるド
レイン電流の減少を少なくすることができる。Therefore, the LDD structures are formed in a self-aligned manner between the drain region (or the source region) and the channel portion and between the source region (or the drain region) and the channel portion. The electric field in the channel portion does not increase as in the prior art, and the generation of local fixed charges in the channel portion is prevented. As a result, it is possible to prevent characteristic deterioration due to the fixed charge. Also, by changing the conductivity of the low impurity concentration region by an electric field applied to the gate electrode, the resistance of the low impurity concentration region is reduced,
As a result, a decrease in drain current due to the resistance component in the low impurity concentration region can be reduced.
《実施例》 以下、この発明を図面に基づいて説明する。<< Example >> Hereinafter, the present invention will be described with reference to the drawings.
第1A〜1D図はこの実施例に係るLDD構造Ｎチャネル側
壁ゲート型MOSFETの製造工程を示す断面図である。この
MOSFETの製造方法を図示工程順に段階的に説明する。1A to 1D are cross-sectional views showing the steps of manufacturing an N-channel sidewall gate type MOSFET having an LDD structure according to this embodiment. this
The method of manufacturing a MOSFET will be described step by step in the order shown.
（ａ）まず第1A図に示すように、半導体基板１の表面に
突部を設けてチャネル部Ｃとソース電極相当部Ｓ′を形
成し、この後、ゲート絶縁膜２を半導体基板１上に形成
する。この半導体基板１およびゲート絶縁膜２の好まし
い具体的な材料としては、ここでは（100）結晶面を有
するＰ型単結晶シリコン基板、および基板の熱酸化によ
り形成された二酸化シリコンがそれぞれ使用されてい
る。(A) First, as shown in FIG. 1A, a projection is provided on the surface of a semiconductor substrate 1 to form a channel portion C and a source electrode equivalent portion S ′, and thereafter, a gate insulating film 2 is formed on the semiconductor substrate 1. Form. Preferable specific materials for the semiconductor substrate 1 and the gate insulating film 2 include a P-type single crystal silicon substrate having a (100) crystal plane and silicon dioxide formed by thermal oxidation of the substrate. I have.
（ｂ）その後、第1B図に示すように、リンなどのＮ型不
純物（第１不純物）による低不純物濃度のＮ型不純物層
5Aを、イオン打込みにより半導体基板１に所定の深さで
形成する。(B) Thereafter, as shown in FIG. 1B, an N-type impurity layer having a low impurity concentration by an N-type impurity (first impurity) such as phosphorus.
5A is formed at a predetermined depth in the semiconductor substrate 1 by ion implantation.
（ｃ）次に第1C図に示すように、ゲート絶縁膜２を介し
て多結晶シリコンなどによりゲート電極３を半導体基板
１の凸部側壁に形成する。なお、ゲート電極３はCVD法
などによって多結晶シリコンをその側壁全体に設け、異
方性エッチング例えばリアクティブイオンエッチング
（RIE法）などにより形成する。その後、このゲート電
極３をマスクとして、ヒ素等のＮ型不純物（第２不純
物）による高不純物濃度のＮ型不純物層6Aをイオン打込
みにより形成する。(C) Next, as shown in FIG. 1C, a gate electrode 3 is formed on the side wall of the convex portion of the semiconductor substrate 1 by using polycrystalline silicon or the like via the gate insulating film 2. The gate electrode 3 is formed by providing polycrystalline silicon on the entire side wall by a CVD method or the like and performing anisotropic etching such as reactive ion etching (RIE method). Thereafter, using this gate electrode 3 as a mask, an N-type impurity layer 6A having a high impurity concentration of an N-type impurity (second impurity) such as arsenic is formed by ion implantation.
（ｄ）最後に第1D図に示すように、所定の温度および時
間の条件下で熱処理を行うことによって、前記低不純物
濃度のＮ型不純物層5Aと前記高不純物濃度のＮ型不純物
層6Aを活性化し、このＮ型不純物層5Aおよび6Aをそれぞ
れ、N-型半導体領域５およびN+型半導体領域６とする。(D) Finally, as shown in FIG. 1D, by performing a heat treatment under the conditions of a predetermined temperature and time, the low impurity concentration N-type impurity layer 5A and the high impurity concentration N-type impurity layer 6A are formed. The N-type impurity layers 5A and 6A are activated to be an N − -type semiconductor region 5 and an N + -type semiconductor region 6, respectively.
上記工程（ａ）〜（ｄ）を有する本実施例によれば、
次に述べるような効果を得ることができる。すなわち、
低不純物濃度のＮ型不純物層5Aを形成した後にゲート電
極３を形成し、このゲート電極３をマスクとして高不純
物濃度のＮ型不純物層6Aを形成することによって、LDD
構造を自己整合的に形成することができる。したっがっ
て、ホットキャリア効果による特性劣化が小さい側壁ゲ
ートMOSFETの微細化・高集積化を図ることができる。特
にゲート電極３下に低不純物濃度のN-型半導体領域５が
存在するようになるため、MOSFET動作時のゲート電圧に
よってN-型半導体領域５の電気伝導度を高くすることが
できる。その結果、この低不純物濃度のN-型半導体領域
５の抵抗成分によるドレイン電流の減少を少なくするこ
とができる。According to this embodiment having the above steps (a) to (d),
The following effects can be obtained. That is,
The LDD is formed by forming the gate electrode 3 after forming the N-type impurity layer 5A having a low impurity concentration, and forming the N-type impurity layer 6A having a high impurity concentration using the gate electrode 3 as a mask.
The structure can be formed in a self-aligned manner. Accordingly, miniaturization and high integration of the side wall gate MOSFET in which the characteristic deterioration due to the hot carrier effect is small can be achieved. In particular, since the N − -type semiconductor region 5 having a low impurity concentration is present below the gate electrode 3, the electric conductivity of the N − -type semiconductor region 5 can be increased by the gate voltage during the operation of the MOSFET. As a result, it is possible to reduce a decrease in drain current due to the resistance component of the low impurity concentration N − -type semiconductor region 5.
以上、この発明の一実施例に基づいて具体的に説明し
たが、この発明は前記実施例に限定されるものではな
く、その要旨を逸脱しない範囲で例えば下記〜の如
く種々変更可能であることは言うまでもない。As described above, the present invention has been specifically described based on one embodiment. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof, for example, as described below. Needless to say.
ドレイン電極ＤであるN-型半導体領域５と、N+型半
導体領域６およびゲート電極３とによって、ソース電極
ＳであるN+型半導体領域６の外周を必ずしも包囲しなく
てもよい。The outer periphery of the N + type semiconductor region 6 serving as the source electrode S does not necessarily have to be surrounded by the N − type semiconductor region 5 serving as the drain electrode D and the N + type semiconductor region 6 and the gate electrode 3.
チャネル部Ｃにしきい値電圧制御のための不純物が
導入されていてもよい。An impurity for controlling the threshold voltage may be introduced into the channel portion C.
各半導体領域１、３、５、６の導電型は実施例とは
逆であってもよい。The conductivity type of each semiconductor region 1, 3, 5, 6 may be opposite to that of the embodiment.
この発明は、ゲート電極３およびゲート絶縁膜２の
材料と厚さを使用条件等に応じて適宜変更することが可
能である。In the present invention, the materials and thicknesses of the gate electrode 3 and the gate insulating film 2 can be appropriately changed according to the use conditions and the like.
低不純物濃度のＮ型不純物層5Aのイオン打込み深さ
を高不純物濃度のＮ型不純物層6Aのイオン打込み深さよ
りも深くすることによって、ソース電極Ｓ側にもLDD構
造を形成することがでる。By making the ion implantation depth of the low impurity concentration N-type impurity layer 5A deeper than the ion implantation depth of the high impurity concentration N-type impurity layer 6A, the LDD structure can be formed also on the source electrode S side.
《発明の効果》 以上説明してきたように、本発明は、側壁ゲート型、
つまり半導体基板表面に垂直方向にチャネルを有する半
導体装置において、低不純物濃度の第１不純物のイオン
打込み深さを高不純物濃度の第２不純物のイオン打込み
深さより深くしたイオン注入により、ドレイン領域のみ
ならずソース領域にも低不純物濃度領域を形成したLDD
構造を形成したものである。<< Effect of the Invention >> As described above, the present invention provides a sidewall gate type,
That is, in a semiconductor device having a channel in the vertical direction on the surface of the semiconductor substrate, the ion implantation depth of the first impurity with a low impurity concentration is made larger than the ion implantation depth of the second impurity with a high impurity concentration, so that only the drain region is formed. LDD with low impurity concentration region also formed in source region
It is a structure formed.
このため、ドレイン領域とチャネル部との間、および
ソース領域とチャネル部との間に、各々、LDD構造を自
己整合的に形成でき、ゲート電圧による動作時に低不純
物濃度領域の電気伝導度を高くすることができ、低不純
物濃度領域の抵抗成分によるドレイン電流減少の減少を
少なくすることができる。Therefore, the LDD structure can be formed in a self-aligned manner between the drain region and the channel portion and between the source region and the channel portion, and the electric conductivity of the low impurity concentration region can be increased during operation by the gate voltage. It is possible to reduce a decrease in drain current decrease due to a resistance component in the low impurity concentration region.
第1A図〜第1D図はこの発明の実施例であるLDD構造チャ
ネル側壁ゲート型MOSFETの製造工程を示す断面図、第２
図は従来方法による側壁ゲート型MOSFETを示す断面図で
ある。 １……半導体基板 ２……ゲート絶縁膜 3,G……ゲート電極 ５……N-型半導体領域 5A……低濃度Ｎ型不純物層 ６……N+型半導体領域 6A……高濃度Ｎ型不純物層 Ｄ……ドレイン電極 Ｓ……ソース電極1A to 1D are cross-sectional views showing a manufacturing process of an LDD structure channel side wall gate type MOSFET according to an embodiment of the present invention.
FIG. 1 is a sectional view showing a side wall gate type MOSFET according to a conventional method. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Gate insulating film 3, G ... Gate electrode 5 ... N - type semiconductor region 5A ... Low concentration N type impurity layer 6 ... N + type semiconductor region 6A ... High concentration N type Impurity layer D: drain electrode S: source electrode
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭60−136369（ＪＰ，Ａ) 特開 昭63−244683（ＪＰ，Ａ) 特開 昭61−105872（ＪＰ，Ａ) 特開 昭64−76737（ＪＰ，Ａ) 特開 平１−179363（ＪＰ，Ａ) 特開 昭63−131576（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-60-136369 (JP, A) JP-A-63-244683 (JP, A) JP-A-61-105872 (JP, A) JP-A 64-64 76737 (JP, A) JP-A-1-179363 (JP, A) JP-A-63-131576 (JP, A)
Claims (1)
て該半導体基板表面に垂直にチャネル部を形成する工程
と、 前記半導体基板上への第２導電形の第１不純物のイオン
打込みにより、前記半導体基板上の突部以外の平坦部お
よび前記突部の上面部に低不純物濃度の不純物層を形成
する工程と、 前記チャネル部の側壁面にゲート電極を形成した後、こ
のゲート電極をマスクとして、前記第１不純物のイオン
打込み深さより浅い第２導電形の第２不純物のイオン打
込みにより、前記低不純物濃度の不純物層より深さの浅
い高不純物濃度の不純物層を前記平坦部および前記上面
部に形成する工程と、 所定条件下で熱処理を行うことにより、前記平坦部の高
不純物濃度の不純物層をドレイン領域（またはソース領
域）とすると共に、前記上面部の高不純物濃度の不純物
層をソース領域（またはドレイン領域）とし、かつ、前
記ドレイン領域（またはソース領域）と前記チャネル部
との間および前記ソース領域（またはドレイン領域）と
前記チャネル部との間に、各々、低不純物濃度領域を形
成する工程と、 を含むことを特徴とする半導体装置の製造方法。1. A step of forming a channel portion perpendicular to a surface of a semiconductor substrate along a projecting side wall of a semiconductor substrate of a first conductivity type, and ions of a first impurity of a second conductivity type on the semiconductor substrate. Forming a low-impurity-concentration impurity layer on the flat portion other than the protrusion on the semiconductor substrate and on the upper surface of the protrusion by implanting; forming a gate electrode on a side wall surface of the channel portion; Using the electrode as a mask, ion implantation of a second impurity of a second conductivity type, which is shallower than the ion implantation depth of the first impurity, causes the impurity layer having a high impurity concentration, which is shallower than the impurity layer having a low impurity concentration, to be formed in the flat portion. Forming a high-impurity-concentration impurity layer in the flat portion as a drain region (or a source region) by performing a heat treatment under a predetermined condition; An impurity layer having a high impurity concentration is used as a source region (or a drain region), and between the drain region (or the source region) and the channel portion and between the source region (or the drain region) and the channel portion. Forming a low impurity concentration region, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251124A JP2757491B2 (en) | 1989-09-27 | 1989-09-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251124A JP2757491B2 (en) | 1989-09-27 | 1989-09-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03112165A JPH03112165A (en) | 1991-05-13 |
| JP2757491B2 true JP2757491B2 (en) | 1998-05-25 |
Family
ID=17218026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1251124A Expired - Fee Related JP2757491B2 (en) | 1989-09-27 | 1989-09-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2757491B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4527814B2 (en) | 1997-06-11 | 2010-08-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| JP3788022B2 (en) * | 1998-03-30 | 2006-06-21 | セイコーエプソン株式会社 | Thin film transistor and manufacturing method thereof |
| JP5614915B2 (en) | 2007-09-27 | 2014-10-29 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | Semiconductor device, semiconductor device manufacturing method, and data processing system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136369A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63244683A (en) * | 1987-03-30 | 1988-10-12 | Mitsubishi Electric Corp | Field effect type semiconductor device and its manufacture |
-
1989
- 1989-09-27 JP JP1251124A patent/JP2757491B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
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| JPH03112165A (en) | 1991-05-13 |
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