JPH03112165A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH03112165A JPH03112165A JP1251124A JP25112489A JPH03112165A JP H03112165 A JPH03112165 A JP H03112165A JP 1251124 A JP1251124 A JP 1251124A JP 25112489 A JP25112489 A JP 25112489A JP H03112165 A JPH03112165 A JP H03112165A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- electrode
- type
- gate
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000005468 ion implantation Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 5
- 239000000969 carrier Substances 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052785 arsenic Inorganic materials 0.000 abstract description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 2
- 239000011574 phosphorus Substances 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 5
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
- H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
（産業−にの利用分野）
この発明は、半導体装置の製造方法に関し、特に側壁ゲ
ート型ＭＯ３ＦＥＴを有する半導体装置に適用して有効
な技術に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and particularly to a technique that is effective when applied to a semiconductor device having a sidewall gate type MO3FET.
（従来の技術）
従来、第２図に示す側壁ゲート型ＭＯ８ＦＥＴなどの半
導体装置は、一般に次のような工程を経て製造されてい
る。すなわち、まず半導体基板１の表面に凸部を設けて
チャネル部Ｃ１ソース電極相当部Ｓ′を形成した後、５
ｉ０２によりゲート絶縁膜２を形成する。次に高不純物
濃度Ｎ型半導体領域４をイオン打込みにより形成した後
、ゲート電極３を多結晶シリコンにより形成し、これに
より側壁ゲート型ＭＯ８ＦＥＴが得られる。(Prior Art) Conventionally, semiconductor devices such as the sidewall gate type MO8FET shown in FIG. 2 are generally manufactured through the following steps. That is, first, a convex portion is provided on the surface of the semiconductor substrate 1 to form a channel portion C1 and a portion S′ corresponding to the source electrode.
A gate insulating film 2 is formed using i02. Next, after forming a highly impurity-concentrated N-type semiconductor region 4 by ion implantation, a gate electrode 3 is formed of polycrystalline silicon, thereby obtaining a sidewall gate type MO8FET.
このようにして得られた側壁ゲート型ＭＯ８ＦＥＴは、
半導体基板１１−の平担面にチャネル部Ｃが設けられた
平面ゲート型ＭＯ８ＦＥＴと異なり、半導体基板１に垂
直な凸部側壁面にチャネル部Ｃをａするため、単位ＭＯ
８ＦＥＴあたりの表面投影面積が少なくなり、その分だ
けＭＯＳＦＥＴの微細化、高集積化を図ることができる
。The sidewall gate type MO8FET obtained in this way is
Unlike the planar gate type MO8FET in which the channel portion C is provided on the flat surface of the semiconductor substrate 11-, the channel portion C is provided on the side wall surface of the convex portion perpendicular to the semiconductor substrate 1.
The surface projected area per 8FET is reduced, and MOSFETs can be miniaturized and highly integrated accordingly.
なお、ｌ〕記側壁ゲート型Ｍ ＯＳ Ｆ Ｆ、 Ｔに関
してはｒ１９８８１ｎｔｅｒｎａｔｉｏｎａｌ Ｅｌ
ｅｃｔｒｏｎ Ｄｅｖｆｃｅｓ Ｍｅｅｔｉｎｇ（
ＩＥＤＭ８８）Ｊ子拾集ｐｐ、２２２−２２５等に報告
されている。Note that r19881international El for sidewall gate type MOS F, T
ectron Devfces Meeting (
It is reported in IEDM88) Jko Collection pp, 222-225, etc.
（発明が解決しようとする問題点）
しかしながら、このような従来の方法で製造された側壁
ゲート型ＭＯ８ＦＥＴにあっては、チャネル部Ｃの」二
・下部に隣接するソース電極Ｓ部およびドレイン電Ｆｆ
ｉ、Ｄ部の双方が高不純物濃度領域４となっている。こ
のため、ＭＯ８ＦＥＴ動作時におけるチャネル部Ｃの最
大電界が大きくなり、この電界によって発生するホット
キャリアがゲート電極３とチャネル部Ｃ間のゲート絶縁
膜２によって捕獲され、このことによってチャネル部Ｃ
に局所的な固定電荷が発生する。その結果、この固定電
荷によって生じるチャネルＣの電界分布の異常に起因し
て、ＭＯＳＦＥＴの特性劣化が生じ、ドレイン電流が減
少するという問題点があった。(Problems to be Solved by the Invention) However, in the sidewall gate type MO8FET manufactured by such a conventional method, the source electrode S part adjacent to the lower part of the channel part C and the drain current Ff
Both the i and D portions are high impurity concentration regions 4. Therefore, the maximum electric field in the channel portion C during MO8FET operation increases, and hot carriers generated by this electric field are captured by the gate insulating film 2 between the gate electrode 3 and the channel portion C.
A local fixed charge is generated. As a result, there is a problem in that the characteristics of the MOSFET are deteriorated due to an abnormality in the electric field distribution in the channel C caused by the fixed charges, and the drain current is reduced.
この発明は、このような従来の問題点に着目してされた
もので、その目的は、ゲート電極下に低不純物濃度領域
を形成し、ＬＤＤ （Ｌｉｇｈｔ １ｙ Ｄｏｐｅｄ
Ｄｒａｉｎ）構造を自己整合的に形成することによ
り、ホットキャリアによる特性劣化を防止し、ドレイン
電流の減少を小さくできる半導体装置の製造方法を提供
することにある。The present invention was made by focusing on such conventional problems, and its purpose is to form a low impurity concentration region under the gate electrode and to create a LDD (Light 1y Doped
An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent characteristic deterioration due to hot carriers and reduce decrease in drain current by forming a drain structure in a self-aligned manner.
（問題点を解決するための手段）
この発明は、１−記のような目的を達成するため、半導
体基板の凸部側壁に沿ってチャネル部を形成する工程と
、
前記半導体基板に第１不純物をイオン打込みにより導入
する工程と、
前記チャネル部の側壁面にゲート電極を形成した後、こ
のゲート電極をマスクとして第２不純物をイオン打込み
により導入し、チャネル部の下部側、１一部側にそれぞ
れドレ・ｆン領域、ソース領域を形成する工程と、
をａむことを特徴とする。(Means for Solving the Problems) In order to achieve the object as described in 1-, the present invention includes a step of forming a channel portion along a side wall of a convex portion of a semiconductor substrate, and a step of forming a first impurity on the semiconductor substrate. After forming a gate electrode on the side wall surface of the channel portion, a second impurity is introduced by ion implantation using the gate electrode as a mask, and a second impurity is introduced into the lower side and one part side of the channel portion. The method is characterized by comprising a step of forming a drain region and a source region, respectively.
（作用）
この発明によれば、１−記工程（ａ）でチャネル部を形
成し、次工程（）））で第１不純物を導入して低不純物
濃度領域を形成し、その後の工程（Ｃ）でゲート電極を
設ける。そして、このゲート電極をマスクとして第２不
純物を導入して高不純物濃度領域を形成することで、Ｌ
ＤＤ構造を自己整合的に形成する。(Operation) According to the present invention, a channel portion is formed in the step (a) of step 1, a first impurity is introduced in the next step ()) to form a low impurity concentration region, and a low impurity concentration region is formed in the subsequent step (C ) to provide a gate electrode. Then, by introducing a second impurity using this gate electrode as a mask and forming a high impurity concentration region, L
A DD structure is formed in a self-aligned manner.
したがって、ゲート電極下には工程（ｂ）で導入した低
濃度の第１不純物のみが存在するようになるため、動作
時におけるチャネル部の電界が従来のように大きくなる
ことはなく、チャネル部に局所的な固定電荷が生ずるの
を防止する。その結果、固定電荷に起因する特性劣化を
防ぐことができる。また、ゲート電極に印加する電界で
低不純物濃度領域の伝導度を変えることによって低不純
物濃度領域の抵抗を低下させ、このことよって低不純物
濃度領域の抵抗成分によるドレイン電流の減少を少なく
することができる。Therefore, only the low-concentration first impurity introduced in step (b) exists under the gate electrode, so the electric field in the channel region during operation does not become as large as in the past, and the channel region Prevents local fixed charges from forming. As a result, characteristic deterioration caused by fixed charges can be prevented. Furthermore, by changing the conductivity of the low impurity concentration region with the electric field applied to the gate electrode, the resistance of the low impurity concentration region can be lowered, thereby reducing the decrease in drain current due to the resistance component of the low impurity concentration region. can.
（実施例） 以下、この発明を図面に基づいて説明する。(Example) The present invention will be explained below based on the drawings.
第１Ａ〜ＩＤ図はこの実施例に係るＬＤＤ措造Ｎチャネ
ル側壁ゲート型ＭＯ８ＦＥＴの製造工程を示す断面図で
ある。このＭＯＳＦＥＴの製造方法を図示工程順に段階
的に説明する。FIGS. 1A to 1D are cross-sectional views showing the manufacturing process of the LDD-structured N-channel sidewall gate type MO8FET according to this embodiment. The method for manufacturing this MOSFET will be explained step by step in the order of the illustrated steps.
（ａ） まず第１Ａ図に示すように、半導体基板１の
表面に突部を設けてチャネル部Ｃとソース電極相当部Ｓ
′を形成し、この後、ゲート絶縁膜２を半導体基板１１
ユに形成する。この半導体基板１およびゲート絶縁ｒ￥
２の好ましい具体的な祠料としては、ここでは（１００
）結晶面を有するＰ型車結晶シリコン基板、および基板
の熱酸化により形成された二酸化シリコンがそれぞれ使
用されている。(a) First, as shown in FIG. 1A, protrusions are provided on the surface of the semiconductor substrate 1 to form a channel portion C and a source electrode equivalent portion S.
', and then the gate insulating film 2 is formed on the semiconductor substrate 11.
form into yu. This semiconductor substrate 1 and gate insulation r
Here, as a preferable specific amulet of No. 2, (100
) P-type wheel crystalline silicon substrates with crystal planes and silicon dioxide formed by thermal oxidation of the substrates are used, respectively.
（ｂ） その後、第１Ｂ図に示すように、リンなどの
Ｎ型不純物（第１不純物）による低不純物濃度のＮ型不
純物層５Ａを、イオン打込みにより半導体基板１に所定
の深さで形成する。(b) Thereafter, as shown in FIG. 1B, an N-type impurity layer 5A with a low impurity concentration using an N-type impurity (first impurity) such as phosphorus is formed at a predetermined depth in the semiconductor substrate 1 by ion implantation. .
（ｃ） 次に第１Ｃ図に示すように、ゲート絶縁膜２
を介して多結晶シリコンなどによりゲート電極３を半導
体基板１の凸部側壁に形成する。なお、ゲート電極３は
ＣＶＤ法などによって多結晶シリコンをその側壁全面に
設け、異方性エツチング例えばリアクチ、ｆブ、イオン
エツチング（ＲＩＥ法）などにより形成する。その後、
このゲート電極３をマスクとして、ヒ素等のＮ型不純物
（第２不純物）による高不純物濃度のＮ型不純物層６Ａ
をイオン打込みにより形成する。(c) Next, as shown in FIG. 1C, the gate insulating film 2
A gate electrode 3 is formed of polycrystalline silicon or the like on the side wall of the convex portion of the semiconductor substrate 1 via a wafer. The gate electrode 3 is formed by applying polycrystalline silicon over the entire side wall by CVD or the like, and by anisotropic etching such as react, f-bubble, ion etching (RIE), or the like. after that,
Using this gate electrode 3 as a mask, an N-type impurity layer 6A with a high impurity concentration made of N-type impurities (second impurities) such as arsenic.
is formed by ion implantation.
（ｄ） 最後に第１Ｄ図に示すように、所定の温度お
よび時間の条件下で熱処理を行うことによって、前記低
不純物濃度のＮ型不純物層５Ａと前記高不純物濃度のＮ
型不純物層６Ａを活性化し、このＮ型不純物層５Ａおよ
び６Ａをそれぞれ、Ｎ型半導体領域５およびＮ゛型半導
体領域６とする。(d) Finally, as shown in FIG. 1D, heat treatment is performed under conditions of predetermined temperature and time to form the N-type impurity layer 5A with the low impurity concentration and the N-type impurity layer with the high impurity concentration.
Type impurity layer 6A is activated, and N type impurity layers 5A and 6A are used as N type semiconductor region 5 and N' type semiconductor region 6, respectively.
上記工程（ａ）〜（ｄ）を有する本実施例によれば、次
に述べるような効果を得ることができる。According to this embodiment having the above steps (a) to (d), the following effects can be obtained.
すなわち、低不純物濃度のＮ型不純物層５Ａを形成した
後にゲート電極３を形成し、このゲート電極３をマスク
として高不純物濃度のＮ型不純物層６Ａを形成すること
によって、ＬＤＤＩ造を自己整合的に形成することがで
きる。したがって、ポットキャリア効果による特性劣化
が小さい側壁ゲ−）−ＭＯＳ、Ｆ Ｅ Ｔの微細化・高
集積化を図ることができる。特にゲート電極３下に低不
純物濃度のＮ−型半導体領域５が存在するようになるた
め、ＭＯ８ＦＥＴ動作時のゲート電圧によってＮ−型半
導体領域５の電気伝導度を高くすることができる。その
結果、この低不純物濃度のＮ−型半導体領域５の抵抗成
分によるドレイン電流の減少を少なくすることができる
。That is, by forming the gate electrode 3 after forming the N-type impurity layer 5A with a low impurity concentration, and forming the N-type impurity layer 6A with a high impurity concentration using the gate electrode 3 as a mask, the LDDI structure can be made in a self-aligned manner. can be formed into Therefore, it is possible to achieve miniaturization and high integration of sidewall GMOS and FETs whose characteristics are less degraded by the pot carrier effect. In particular, since the N-type semiconductor region 5 with a low impurity concentration exists under the gate electrode 3, the electrical conductivity of the N-type semiconductor region 5 can be increased by the gate voltage during MO8FET operation. As a result, the decrease in drain current due to the resistance component of the N- type semiconductor region 5 having a low impurity concentration can be reduced.
以１−１この発明の一実施例に基づいて具体的に説明し
たが、この発明は前記実施例に限定されるものではなく
、その要旨を逸脱しない範囲で例えば下記■〜■の如く
秤々変更可能であることは言うまでもない。1-1 This invention has been specifically explained based on one embodiment of the present invention, but the present invention is not limited to the above-mentioned embodiment. Needless to say, it can be changed.
■ ドレイン電極りであるＮ−型半導体領域５と、Ｎ′
型半導体領域６およびゲート電極３とによって、ソース
電極ＳであるＮ′型半導体領域６の外周を必ずしも包囲
しなくてもよい。■ N-type semiconductor region 5, which is the drain electrode, and N'
The N' type semiconductor region 6 and the gate electrode 3 do not necessarily have to surround the outer periphery of the N' type semiconductor region 6, which is the source electrode S.
■ チャネル部Ｃにしきい値電圧制御のための不純物が
導入されていてもよい。(2) Impurities may be introduced into the channel portion C for threshold voltage control.
■ 各半導体領域１．３．５．６の導電型は実施例とは
逆であってもよい。(2) The conductivity type of each semiconductor region 1.3.5.6 may be opposite to that in the embodiment.
■ この発明は、ゲート電極３およびゲート絶縁膜２の
ｌ１と厚さを使用条件等に応じて適宜変更することが可
能である。(2) In the present invention, the l1 and thickness of the gate electrode 3 and gate insulating film 2 can be changed as appropriate depending on usage conditions and the like.
■−低不純物濃度のＮ型不純物層５Ａのイオン打込み深
さを高不純物濃度のＮ型不純物層６Ａのイオン打込み深
さよりも深くすることによって、ソース電極Ｓ側にもＬ
ＤＤ措造を形成することがでる。■-By making the ion implantation depth of the N-type impurity layer 5A with a low impurity concentration deeper than the ion implantation depth of the N-type impurity layer 6A with a high impurity concentration, L is also applied to the source electrode S side.
It is possible to form a DD structure.
（発明の効果）
以上説明してきたように、この発明によれば、側壁ゲー
ト型ＭＯ８ＦＥＴ等の半導体装置において、低不純物濃
度領域を形成した後その」−にゲート電極を形成し、こ
のゲート電極をマスクとして高不純物濃度領域を形成す
ることによって、ＬＤＤ措造を自己整合的に形成するの
で、ポットキャリアによる特性劣化を防止し、半導体装
置の微細化、高集積化を図ることができるばかりでなく
、ゲート電極下に低不純物濃度領域が存在するため、ゲ
ート電圧による動作時に低不純物濃度領域の電気伝導度
を高くすることができ低不純物濃度領域の抵抗成分によ
るドレイン電流減少の現象を小さくすることができる。(Effects of the Invention) As described above, according to the present invention, in a semiconductor device such as a sidewall gate type MO8FET, after forming a low impurity concentration region, a gate electrode is formed in the region. By forming a high impurity concentration region as a mask, the LDD structure is formed in a self-aligned manner, which not only prevents characteristic deterioration due to pot carriers, but also enables miniaturization and high integration of semiconductor devices. Since there is a low impurity concentration region under the gate electrode, the electrical conductivity of the low impurity concentration region can be increased during operation with gate voltage, and the phenomenon of decrease in drain current due to the resistance component of the low impurity concentration region can be reduced. I can do it.
第］、Ａ図〜第１Ｄ図はこの発明の実施例であるＬＤＤ
構造チャネル側壁ゲート型ＭＯ３ＦＥＴの製造工程を示
す断面図、第２図は従来方法による側壁ゲート型ＭＯ８
ＦＥＴを示す断面図である。
１・・・半導体基板
２・・・ゲート絶縁膜
３、 Ｇ・・・ゲート電極
５・・・Ｎ 型半導体領域
５Ａ・・・低濃度Ｎ型不純物層
６・・・Ｎ′型半導体領域
６Ａ・・・高濃度Ｎ型不純物層
Ｄ・・・ドレイン電極
Ｓ・・・ソース電極], Figures A to 1D are LDDs that are embodiments of this invention.
A cross-sectional view showing the manufacturing process of a structured channel sidewall gate type MO3FET, FIG. 2 is a sidewall gate type MO8 manufactured by a conventional method.
It is a sectional view showing FET. 1... Semiconductor substrate 2... Gate insulating film 3, G... Gate electrode 5... N type semiconductor region 5A... Low concentration N type impurity layer 6... N' type semiconductor region 6A. ...High concentration N-type impurity layer D...Drain electrode S...Source electrode
Claims (1)
る工程と、 前記半導体基板に第１不純物をイオン打込みにより導入
する工程と、 前記チャネル部の側壁面にゲート電極を形成した後、こ
のゲート電極をマスクとして第２不純物をイオン打込み
により導入し、チャネル部の下部側、上部側にそれぞれ
ドレイン領域、ソース領域を形成する工程と、 を含むことを特徴とする半導体装置の製造方法。[Claims] 1. A step of forming a channel portion along a side wall of a convex portion of a semiconductor substrate, a step of introducing a first impurity into the semiconductor substrate by ion implantation, and a step of forming a gate electrode on a side wall surface of the channel portion. After forming the gate electrode, a second impurity is introduced by ion implantation using the gate electrode as a mask to form a drain region and a source region on the lower side and the upper side of the channel portion, respectively. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251124A JP2757491B2 (en) | 1989-09-27 | 1989-09-27 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1251124A JP2757491B2 (en) | 1989-09-27 | 1989-09-27 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03112165A true JPH03112165A (en) | 1991-05-13 |
| JP2757491B2 JP2757491B2 (en) | 1998-05-25 |
Family
ID=17218026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1251124A Expired - Fee Related JP2757491B2 (en) | 1989-09-27 | 1989-09-27 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2757491B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11284192A (en) * | 1998-03-30 | 1999-10-15 | Seiko Epson Corp | Vertical type transistor and its manufacture |
| US6392279B1 (en) | 1997-06-11 | 2002-05-21 | Fujitsu Limited | Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance |
| JP2009081389A (en) * | 2007-09-27 | 2009-04-16 | Elpida Memory Inc | Semiconductor device, method for manufacturing semiconductor device, and data process system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136369A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63244683A (en) * | 1987-03-30 | 1988-10-12 | Mitsubishi Electric Corp | Field effect type semiconductor device and its manufacture |
-
1989
- 1989-09-27 JP JP1251124A patent/JP2757491B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136369A (en) * | 1983-12-26 | 1985-07-19 | Toshiba Corp | Manufacture of semiconductor device |
| JPS63244683A (en) * | 1987-03-30 | 1988-10-12 | Mitsubishi Electric Corp | Field effect type semiconductor device and its manufacture |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6392279B1 (en) | 1997-06-11 | 2002-05-21 | Fujitsu Limited | Semiconductor device having LDD structure adapted to lower parasitic capacitance and parasitic resistance |
| JPH11284192A (en) * | 1998-03-30 | 1999-10-15 | Seiko Epson Corp | Vertical type transistor and its manufacture |
| JP2009081389A (en) * | 2007-09-27 | 2009-04-16 | Elpida Memory Inc | Semiconductor device, method for manufacturing semiconductor device, and data process system |
| US8735970B2 (en) | 2007-09-27 | 2014-05-27 | Yoshihiro Takaishi | Semiconductor device having vertical surrounding gate transistor structure, method for manufacturing the same, and data processing system |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2757491B2 (en) | 1998-05-25 |
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