JP3052348B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method suitable for use in manufacturing a MOS integrated circuit device.

2. Description of the Related Art In recent years, there has been remarkable progress in the development of MOS LSIs. In particular, in the sense that the advantages of low power consumption can be fully utilized, high integration does not allow other semiconductor devices to follow.
As the degree of integration increases, one of the major problems for recent LSI development is the short channel effect of transistors and the punch-through phenomenon. With the short channel effect, the charge in the channel region under the gate is strongly affected not only by the gate voltage but also by the depletion layer charge in the source and drain regions, the electric field, and the potential distribution as the device is miniaturized, particularly as the gate length is reduced. This is a phenomenon that deteriorates the characteristics. This short channel effect largely depends on the gate length, the gate oxide film thickness, and the junction depth of the source / drain diffusion layers. On the other hand, the punch-through phenomenon is a phenomenon in which the distance between the source and drain diffusion layers is reduced as the gate length is reduced, the depletion layer of the source is connected to the depletion layer of the drain, and the drain current cannot be controlled by the gate voltage.

Accordingly, at present, there is a demand for miniaturization of elements, and there is a demand for a method of manufacturing a semiconductor device which prevents a short channel effect and a punch-through phenomenon.

In addition, various contact diameters have been reduced along with miniaturization of elements. Gate polysilicon contacts are no exception. Unwanted impurities or oxides are formed on the polycrystalline silicon surface during the semiconductor manufacturing process,
It is expected that the contact characteristics will remarkably deteriorate with the miniaturization of the element. Therefore, there is also a demand for a process having stable and reliable contact characteristics of gate polycrystalline silicon and having favorable characteristics.

An example of a conventional method for manufacturing an NMOS transistor will be described below. FIG. 4 is a schematic sectional view of an example of a conventional NMOS transistor. Conventional manufacturing technology uses a P-type silicon substrate 400
Is provided with a P-well layer 401 (about 1E15 cm ^-3 ) on which an NMOS is to be formed, then a thin gate oxide film (10 nm to 25 nm) 402 is formed, and then about 300 nm of polycrystalline silicon is deposited by a CVD method. Then, phosphorus is diffused into the polycrystalline silicon by POCl ₃ diffusion (about 1E20 cm ^{−3 to} 1E21 cm ⁻³ ). Then, gate electrode processing is performed by photolithography and etching. Next, using the gate electrode 403 as a mask, phosphorus is ion-implanted (acceleration voltage: 40 KeV, implantation amount: 1 to 3E13 cm ⁻² ), and the n ⁻ layer 404, that is, LDD (Li) is formed so that the surface concentration becomes about 1E18 cm ^−3.
ghtly doped drain) layer is formed (FIG. 3A).
Next, after depositing a CVD SiO ₂ film on the entire surface of the substrate by 150 nm to 250 nm,
Anisotropic etching, that is, etching of the deposited film thickness of the CVD SiO ₂ only in the vertical direction,
A sidewall 405 having a width of 50 nm to 250 nm is formed. next,
Arsenic (80 KeV, 6E15 cm ^-2 ) is implanted and the source drain of NMOS
406 regions are formed. Thereafter, in order to electrically activate the impurities implanted in the source / drain regions, heat treatment is performed at a high temperature of about 900 ° C. for about 30 to 40 minutes (FIG. 9B). Next, a phosphor glass film 408 is deposited to a thickness of about 700 nm to form an interlayer insulating film. Next, in order to flatten the interlayer insulating film 408, reflow is performed at about 900 ° C. for about 30 to 40 minutes.
Then, the source / drain electrode window 409 and the gate electrode window 4 are formed at desired locations by photolithography and etching.
Form 10. Then, about 800 nm of AL-Si-Cu411 is deposited,
Processed to form electrodes.

According to the conventional method for manufacturing a MOS transistor, the source / drain regions are formed by ion implantation.
The source / drain diffusion layer tends to be deep due to heat treatment for electrical activation thereof, heat treatment at the time of reflow after depositing a phosphorus glass film for flattening, and the like. (For devices around 1 μm, the diffusion layer is about 0.2-0.3 μm.
m. ) If the diffusion layer is deeper, the short channel effect and punch-through effect of the transistor are promoted,
In addition, the effect becomes remarkable with miniaturization and high integration in the future. In order to solve the problem, it is conceivable to reduce the acceleration energy of ion implantation to form a diffusion layer, but both the NMOS and PMOS diffusion layers are 1E15 cm ^-2
A high dose is required, and it is very difficult to realize it with low acceleration energy. Conversely, a method of reducing the dose to make the diffusion layer shallower is also conceivable, but this increases the layer resistance of the diffusion layer and causes deterioration of device characteristics.

Also, the electrode window of gate polycrystalline silicon in which impurities are diffused at a high concentration has been required to be miniaturized, and the size thereof has been reduced. Along with this, if the polycrystalline silicon surface is oxidized or undesired impurity contamination occurs during the manufacturing process, the impurity concentration on the gate polycrystalline silicon surface may be lowered and the characteristics of the gate electrode contact may be deteriorated. Is getting bigger.

The present invention has been made in view of the above-described problems, and can have an effect of reducing the depth of a diffusion layer in a source / drain portion, and can increase an impurity concentration on a surface of a gate polycrystalline silicon, An object of the present invention is to provide a method for manufacturing a semiconductor device capable of stably providing a contact resistance of a gate electrode window.

Means for Solving the Problems The present invention solves the above-mentioned problems, a step of forming an impurity layer on a semiconductor substrate, and a step of forming an amorphous layer by ion implantation in part of the impurity layer, Applying a heat treatment to the semiconductor substrate to collect impurities in the amorphous layer.

Further, the semiconductor substrate is made amorphous by ion-implanting a Group 4 element, fluorine, fluoride, or an inert gas.

More specifically, the present invention comprises a step of forming a gate oxide film on a silicon substrate, a step of forming polycrystalline silicon on the gate oxide film, a step of diffusing impurities into the polycrystalline silicon, Forming a gate electrode by patterning crystalline silicon, forming a source / drain layer by ion implantation using the gate electrode as a mask, and ion-implanting a part of the impurity layer and the gate electrode on the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: a step of forming an amorphous layer; and a step of performing a heat treatment on the semiconductor substrate and the gate electrode to collect impurities in the amorphous layer.

According to the present invention, the impurity diffusion layer can be concentrated at a desired position by the above-described configuration, and therefore, the depth of the source / drain diffusion layer can be easily reduced, and the short channel effect and the punch-through phenomenon can be suppressed. In addition, the electrode window contact characteristics of the gate polycrystalline silicon can be stably provided, and a fine semiconductor device having good characteristics and high reliability can be obtained.

Embodiment Hereinafter, a method for manufacturing a semiconductor device of the present invention will be described in detail with reference to the drawings. For simplicity, an example in which the present invention is applied to an NMOS will be described.

In FIG. 1A, a P-well layer 101 (about 1E15 cm ⁻³ ) on which an NMOS is formed is provided on a P-type silicon substrate 100. After forming a thin gate oxide film 102 (10 nm to 25 nm), polycrystalline silicon is deposited to a thickness of 300 nm by CVD. Then POCl ₃
The resistance is reduced by doping phosphorus into the polycrystalline silicon by about 1E21 cm ^-3 by diffusion. Next, gate electrode processing is performed on the polycrystalline silicon film by photolithography and etching. Next, using this gate electrode 103 as a mask,
Phosphorus ion implantation (acceleration voltage 40 KeV, implantation amount 1-3E13c
m- ² ), and the n ^- layer 1 has a surface concentration of about 1E18cm- ^3.
04 is formed as an LDD layer.

Next, in FIG. 1 (b), an insulating film such as CVDS is formed on the entire surface of the substrate.
After depositing an iO ₂ film of 150 to 250 nm, anisotropic etching, that is, etching of the deposited film thickness of the CVD SiO ₂ only in the vertical direction, to form a sidewall 105 of 150 to 250 nm width on the side wall of the gate electrode 103. . Next, arsenic (80 KeV, 6E15 cm ^-2 ) is implanted using the gate electrode with the sidewall as a mask to form an NMOS source drain 106 region.

Next, in FIG. 1 (c), this step is one of the features of the present invention.
First, silicon is ion-implanted into the source / drain layer and the gate electrode at, for example, 40 keV and 2E15 cm ⁻² . In the source / drain layer and the gate polycrystalline silicon, the amorphous layer 107 is formed at a position of about 50 nm from the semiconductor substrate surface and the gate polycrystalline silicon surface due to the range.

Next, heat treatment is performed at 900 ° C. for about 30 minutes. Then,
As shown in FIG. 1D, in the source / drain layer, phosphorus and arsenic pile up in the amorphous layer 107, and the concentration at about 50 nm from the surface of the source / drain layer becomes high. The cause is that impurities (phosphorus and arsenic in this case) in the semiconductor substrate are gathered, and the source / drain diffusion layer can be made shallower. A similar phenomenon occurs in the gate polycrystalline silicon 103. For example, even if impurities are formed in the gate polycrystalline silicon or an oxide film is formed on the polycrystalline silicon surface before the heat treatment, and the impurity concentration on the surface (in this case, the phosphorus concentration) is reduced, the contact resistance may be abnormally increased. It is expected that the present invention can increase the impurity concentration (in this case, the phosphorus concentration) at a position of about 50 nm from the surface of the gate polycrystalline silicon, and stabilize the contact characteristics of the gate polycrystalline silicon electrode. Can be provided well. Although silicon was used as the ion species, other Group 4 elements or Group 4 fluorides may be used. Even a substance having a small atomic weight, such as fluorine, may be used as an ion implantation material for forming an amorphous substance, since the influence of the conductivity type does not adversely affect the device. Further, an inert gas may be used for the ion implantation material for forming an amorphous phase. If the source drain layer and the gate polycrystalline silicon have the same conductivity type, it is needless to say that the same ion type or the same conductivity type fluoride as the conductivity type may be used.

Thereafter, in FIG. 1E, the phosphor glass film 108 is
A degree of deposition is performed to form an interlayer insulating film. Next, in order to flatten the interlayer insulating film, reflow is performed at approximately 900 ° C. for approximately 30 to 40 minutes. Then, a source / drain electrode window 109 and a gate electrode window 110 are formed at desired locations by photolithography and etching. Then, the AL-Si-Cu film is changed to
The electrode is deposited and processed to a certain degree.

Supplementary data on the phenomenon that impurities collect in the amorphous layer will be added. The results of an experiment in which BF ₂ , which is a fluoride of the opposite conductivity type, is implanted into phosphorus-doped gate polycrystalline silicon and subjected to a heat treatment are shown. This experiment is based on the assumption that impurities of the opposite conductivity type (P type) such as B come into the N-type gate polycrystalline silicon (abnormal contact resistance is expected to increase only with B contamination alone). This is equivalent to an experiment on what happens to the contact resistance of the gate polycrystalline silicon when an amorphous layer is formed by ion implantation and heat treatment is performed, which is a feature of the present invention. To explain the details of the experiment, 3E20
B in 300 nm of polycrystalline silicon diffused with phosphorus at a high concentration of about cm ^-3
A sample into which F ₂ was not injected and a sample into which 40 keV and 3E15 cm ⁻³ were injected were prepared, and then heat treatment was performed at 900 ° C. in an N ₂ atmosphere for 40 minutes. Then, an interlayer film, a contact, and an aluminum electrode were formed. FIG. 2 shows the Kelvin method of 2.0 μm for two samples.
The result of the contact resistance between the polycrystalline silicon of m □ and the aluminum electrode is shown. The difference in contact resistance between the sample injected with BF ₂ at 40 keV and 3E15 cm ^-3 and the sample not injected at all was about 3
The increase was only about twice. When BF ₂ is implanted under the above conditions, the concentration of B on the polycrystalline silicon surface is expected to be about 3E20 cm ^−3, which is almost the same as the concentration of P (phosphorus), and an abnormal increase in resistance is expected due to the canceling effect. . However, the actual increase was only about three times.

FIG. 3 shows that BF ₂ is added to phosphorus-doped polycrystalline silicon at 40 keV and 3E15c.
The SIMS analysis result of P (phosphorus), B, and F of the sample injected at m ^-3 is shown. P of the surface by injection of As is apparent BF ₂ from FIG.
It can be seen that (phosphorus) pile-ups 300. This is because BF ₂ is about 100 nm from the polycrystalline silicon surface.
Amorphized by implantation, P
(Phosphorus) piled up. Therefore, the concentration of P (phosphorus) on the polycrystalline silicon surface was higher than that of B, and the contact resistance did not increase as expected.

As described above, the present invention makes use of the phenomenon that impurities are gathered in the amorphized portion by the heat treatment, and can obtain stable gate polycrystalline silicon contact characteristics. Further, it has an effect of making the source / drain layer shallow, and can provide a stable and good semiconductor device which does not cause a punch-through phenomenon or a short channel effect. Thus, it is possible to provide an ideal method of manufacturing a semiconductor device. it can. Further, the heat treatment performed after the ion implantation for forming the amorphous layer according to the present invention is a heat treatment conventionally required for activating the source / drain layer, and only the number of steps of the ion implantation for forming the amorphous layer is increased. In particular, there is no great difference in throughput.

As described above, the source / drain diffusion layer is conventionally deepened by applying the heat treatment. However, when the present invention is used, the diffusion layer does not become deeper even when the heat treatment is applied, and the ion implantation for amorphization is performed. By simply changing the conditions, the concentration of the impurity layer at a desired position can be increased. That is, the diffusion layer can be formed at a desired position, particularly at a shallow position, with a simple process, and the contact characteristics of the gate polycrystalline silicon can be stably and favorably provided.

In this embodiment, the explanation has been given by taking the NMOS as an example.
It goes without saying that the present invention may be applied to the source / drain and gate polycrystalline silicon of the transistor. In this embodiment, a method of manufacturing a MOS transistor having a well structure is described.
If a mold substrate is used and an N-type substrate is used for PMOS, the well structure is not particularly required. The substrate conduction type may be either N or P depending on whether or not a well structure is used.

Further, in this embodiment, the source / drain layer and the gate polycrystalline silicon have the same conductivity type, but may be different. However, in this case, the ion implantation for forming the amorphous layer is desirably performed with a Group 4 element such as silicon, a fluoride of the Group 4 element, or an inert gas. Alternatively, the ion implantation for forming the source / drain layer amorphous layer and the ion implantation for forming the gate polycrystalline amorphous layer may be performed separately.

Also, the present invention may be implemented with a CMOS structure. At this time, the ion implantation material for forming the amorphous layer is preferably a Group 4 element such as silicon, fluorine, a fluoride of the Group 4 element, or an inert gas. Or NMOS source / drain, N
When the type gate polycrystalline silicon is to be made amorphous, N type ion species or its fluoride is implanted. When the PMOS source / drain and the P type gate polycrystalline silicon are made amorphous, the P type ion species or What is necessary is just to inject the fluoride.

Although the embodiment of the present invention is a semiconductor device having an LDD structure, it goes without saying that a semiconductor device having a DDD (Double Diffused Drain) structure or a single drain type semiconductor device may be used.

As is clear from the above description, according to the present invention, the depth of the source / drain diffusion layer can be reduced, the short channel effect and the punch-through effect can be suppressed, and the contact characteristics of the gate polycrystalline silicon surface can be further reduced. And a highly reliable and fine semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a process flow sectional view of an NMOS transistor according to an embodiment of the present invention, and FIG. 2 is a contact resistance characteristic diagram by Kelvin method when BF ₂ is implanted into phosphorus-doped polycrystalline silicon and when it is not implanted. FIG. 3 is a graph showing SIMS analysis characteristics of P (phosphorus), B, and F when BF ₂ is injected into phosphorus-doped polycrystalline silicon, and FIG. 4 is an NMOS formed by using a conventional manufacturing method.
FIG. 3 is a structural cross-sectional view of a transistor. 100,400: Silicon substrate, 101, 401: P well layer, 10
2,402: Gate oxide film, 103,403: Gate electrode, 104,
404 …… n ^- layer, 105,405 …… side wall (CVD SiO
₂ ), 106,406 ... source / drain layer, 107 ... amorphous layer, 108,408 ... phosphorus glass film, 109,409 source / drain electrode window, 110,410 ... gate electrode window, 111,411 ... AL-Si
-Cu film, 300 ... Pile up of phosphorus.

──────────────────────────────────────────────────続 き Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 29/78 H01L 29 / 62G (56) References JP-A-47-37176 (JP, A) JP-A-61-278165 ( JP, A) JP-A-2-2117 (JP, A) JP-A-4-79216 (JP, A) JP-A-59-17244 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/265 H01L 29/78 INSPEC (DIALOG) WPI (DIALOG)

Claims (11)

(57) [Claims] A step of forming an impurity layer on a semiconductor substrate;
Forming an amorphous layer in a part of the impurity layer by ion implantation shallower than the impurity layer, and performing a heat treatment on the semiconductor substrate to collect impurities in the impurity layer in the amorphous layer And a method for manufacturing a semiconductor device. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made amorphous by ion implantation of a Group 4 element. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate is made amorphous by ion implantation of fluorine. 4. The method according to claim 1, wherein the semiconductor substrate is made amorphous by ion implantation of a fluoride. 5. The method according to claim 1, wherein the semiconductor substrate is made amorphous by ion implantation of an inert gas. 6. A step of forming a gate oxide film on a semiconductor substrate, a step of forming polycrystalline silicon on the gate oxide film, and a step of forming a gate electrode by patterning the polycrystalline silicon. Forming a source / drain layer by ion implantation using the gate electrode as a mask, forming an amorphous layer by ion implantation shallower than the source / drain layer on a part of the source / drain layer and the gate electrode, Performing a heat treatment on the semiconductor substrate and the gate electrode to collect impurities in the source / drain layer in the amorphous layer. 7. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is made amorphous by ion implantation of a Group 4 element. 8. The method according to claim 6, wherein the semiconductor substrate is made amorphous by ion implantation of fluorine. 9. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate is made amorphous by ion implantation of an inert gas. 10. The semiconductor device according to claim 6, wherein the conductivity type of each impurity of the source / drain layer and the gate electrode is the same, and the ion type of the amorphous layer type ion implantation is the same as the conductivity type. Of manufacturing a semiconductor device. 11. The method according to claim 6, wherein the conductivity type of the source / drain layer and the gate electrode impurity is the same, and the ion type of the amorphous type ion implantation is the same fluoride as the conductivity type. A method for manufacturing a semiconductor device.