JP3438395B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a MOSFET channel structure and a method of forming the same. 2. Description of the Related Art A conventional method for forming a buried channel transistor will be described with reference to FIG. First, as shown in FIG. 5A, a well containing an impurity of a first conductivity type (hereinafter, referred to as N-type) is formed on the surface of a silicon semiconductor substrate 501, and then a silicon oxide film 502 of about 20 nm is formed.
For example, BF ₂ is implanted as an impurity of the second conductivity type (hereinafter, referred to as P-type) by ion implantation at an energy of 40 keV and a dose of about 1E12 to form a P-type impurity diffusion layer 503. Next, as shown in FIG. 5B, the silicon oxide film 502 is removed by a wet etch method, and then thermally oxidized again to form a gate insulating film 50 of about 10 nm.
4 is formed. Next, polycrystalline silicon or the like containing a high concentration of phosphorus is deposited by a CVD method to a thickness of about 300 nm, patterned, thermally oxidized at about 850 degrees to form a gate electrode 505, and then a P-type such as BF ₂ is formed. Impurities are ion-implanted at an energy of 40 keV and a dose of 1E13.
The P-type impurity diffusion layer 506 is formed by the implantation to a certain degree. Then, a silicon oxide film is formed by CVD method.
After depositing about 0 nm, the silicon oxide film is anisotropically etched by about 200 nm by dry etching or the like to form a sidewall spacer 507 of the silicon oxide film along the sidewall of the gate electrode 505. After that, a P-type impurity such as BF _{2 is} implanted by an ion implantation method at an energy of 50 keV and a dose of about 2E15.
By applying a high-temperature heat treatment such as a TA method, impurities in the source / drain 508 are activated. At this time, the gate electrode 505 has an N-type conductivity because it contains a high concentration of phosphorus in advance. In this manner, a buried channel P-channel MOSFET having an LDD structure is formed as shown in FIG. [0004] It should be noted that the surface channel type MOSF is
When the ET is formed, first, as shown in FIG. 5A, a well containing an impurity of a first conductivity type (hereinafter, referred to as an N-type) is formed on the surface of the silicon semiconductor substrate 501,
A silicon oxide film 502 of about 20 nm is formed, and BF _{2 is used} as a second conductivity type (hereinafter referred to as P-type) impurity.
Is implanted by ion implantation at an energy of 40 keV and a dose of about 1E12 to form a P-type impurity diffusion layer 503. Next, as shown in FIG.
02 is removed by wet etching, and then thermally oxidized again to form a gate insulating film 504 of about 10 nm. Next, polycrystalline silicon or the like is deposited by a CVD method to a thickness of about 300 nm, and after patterning, 850 is deposited.
After forming the gate electrode 505 by performing thermal oxidation to a degree, a P-type impurity such as BF ₂ is implanted by ion implantation at an energy of about 40 keV and a dose of about 1E13 to form a P-type impurity diffusion layer 506. Then, a silicon oxide film is formed by CVD method.
After depositing about 0 nm, the silicon oxide film is anisotropically etched by about 200 nm by dry etching or the like to form a sidewall spacer 507 of the silicon oxide film along the sidewall of the gate electrode 505. After that, a P-type impurity such as BF _{2 is} implanted by an ion implantation method at an energy of 50 keV and a dose of about 2E15.
By applying a high-temperature heat treatment such as a TA method, impurities in the source / drain 508 are activated. At this time, the gate electrode 505 has a P-type conductivity. In this way, a surface channel P-channel MOSFET having an LDD structure is formed as shown in FIG. [0006] The LD according to the prior art
When a buried channel P-channel MOSFET having a D structure is formed, boron introduced into the channel portion is diffused by subsequent thermal oxidation, and the depth of the P-type buried layer in the channel portion is increased. Furthermore, when impurities are introduced into the channel portion by the ion implantation method, crystal defects occur in the semiconductor substrate due to the ion implantation, so that the diffusion rate of the impurities is increased more than usual by the subsequent oxidation treatment,
The depth of the P-type buried layer in the channel portion becomes excessively large. As described above, when the depth of the P-type buried layer in the channel portion is increased, a punch-through phenomenon is likely to occur, so that there is a problem that miniaturization of the element becomes difficult. Further, when the element is made conductive, some carriers move on the channel surface even in the buried channel type MOSFET, so that the mobility is reduced due to the influence of surface scattering and the current driving capability is reduced. There was a problem that it would. Further, when a surface channel type MOSFET is formed by a conventional technique, impurities are diffused deeply in an oxidation step after ion implantation into a channel, so that a subthreshold coefficient is deteriorated and device characteristics are deteriorated. There was a problem. According to a method of manufacturing a semiconductor device of the present invention, a step of forming a first first conductivity type region by introducing a first conductivity type impurity into a semiconductor substrate; By introducing the second conductivity type impurity into the semiconductor substrate,
Forming a second conductivity type region above the first first conductivity type region, forming a gate insulating film by thermally oxidizing the surface of the semiconductor substrate, and forming a gate electrode on the gate insulating film Forming a semiconductor device, and introducing a second conductivity type impurity into the source / drain portions, wherein the thermal oxidation for forming the gate insulating film comprises the step of: The method is characterized in that the first conductivity type impurity forming the first conductivity type region is diffused to form a second first conductivity type region in the semiconductor substrate above the second conductivity type region. [0015] That is, the buried channel type P channel M of the present invention.
In an OSFET, after an N-type diffusion layer of arsenic is formed under a P-type buried channel layer, an oxidizing process is performed to partially diffuse arsenic and cause arsenic diffusion on the surface of the semiconductor substrate immediately below the gate insulating film. The concentration increases. Therefore, the impurity distribution in the channel portion is determined by N
A first impurity diffusion layer of a p-type, a second impurity diffusion layer serving as a P-type buried channel layer is formed below the first impurity diffusion layer, and a second impurity diffusion layer is formed below the second impurity diffusion layer. An N-type third impurity diffusion layer of arsenic is formed. With such a structure, the second impurity diffusion layer, which is a P-type buried channel layer, is separated from the interface between silicon and the silicon oxide film by the first impurity diffusion layer, and at the same time, has a different conductivity type. The impurity is canceled by the impurity diffusion layer of No. 3 so that a shallow P-type buried channel layer can be formed. In the MOSFET of the present invention, a high-temperature and short-time heat treatment is performed immediately after the impurity ions are implanted into the channel portion. By performing the oxidation treatment after recovering the crystal defect of the semiconductor substrate by the above, the accelerated diffusion of the impurity due to the crystal defect can be suppressed, and the depth of the P-type buried channel layer can be reduced. Hereinafter, the present invention will be described in more detail by way of examples with reference to sectional views of steps. First, a first embodiment of the present invention will be described. As shown in FIG. 1A, after forming an N-type well on the surface of a semiconductor substrate 101 containing silicon as a main component, a silicon oxide film 102 having a thickness of about 20 nm was formed on the surface by thermal oxidation. after the arsenic energy 200 keV, to form an N-type impurity diffusion layer 103 by injecting a dose of about 2E12 ion implantation method similarly energy 70 BF ₂ by ion implantation
By implanting at about keV and at a dose of about 3E12, a P-type impurity diffusion layer 104 is formed. FIG. 2A shows the impurity distribution in the depth direction in the silicon substrate at this time.
An N-type impurity diffusion layer 103 is provided below the N-type impurity diffusion layer 104.
Are formed. Next, as shown in FIG. 1B, after the silicon oxide film 102 is removed by wet etching, oxidation is performed at about 850 ° C. in an oxygen atmosphere, and then 900 ° C. in a nitrogen atmosphere. The gate oxide film 106 is formed by performing post-annealing from about 1000 degrees to about 1000 degrees. FIG. 2B shows the impurity concentration distribution after the gate oxide film is formed. Due to the gate oxidation, the peak concentration of the P-type impurity diffusion layer 202 in FIG. 2B is lower than that immediately after the ion implantation and has a gentle concentration distribution. Diffusion layer 201
Is near surface and depth 0.4 due to abnormal diffusion of arsenic
The concentration distribution is such that there are two peaks in a portion less than μm. When the density distribution is as shown in FIG.
As shown in FIG. 1B, an N-type impurity diffusion layer 105 is formed on the substrate surface, and a P-type impurity diffusion layer 104 is formed below the N-type impurity diffusion layer 105 as shown in FIG. The N-type impurity diffusion layer 103 is formed below the P-type impurity diffusion layer 104. Next, polycrystalline silicon containing a high concentration of phosphorus as an impurity is formed to a thickness of about 300 nm on the gate oxide film 106 by a CVD method. After a lithography step and an etching step, oxidation for recovering etching damage is performed. After performing the process to form the gate electrode 107, BF ₂ is implanted as a P-type impurity by ion implantation at an energy of about 40 keV and a dose of about 1E13 to form a P-type impurity diffusion layer. Then, C
After depositing a silicon oxide film by about 200 nm by the VD method, by etching the silicon oxide film by about 200 nm by anisotropic etching such as dry etching,
A side wall spacer 109 made of a silicon oxide film is formed on the side wall of the gate electrode 107. Next, BF ₂ is implanted by ion implantation at an energy of about 50 keV and a dose of about 2E15 to form a P-type impurity diffusion layer 110 in the source / drain portions. At this time, since the gate electrode contains a high concentration of phosphorus in advance, it has N-type conductivity. Then RT
By activating the impurities by annealing such as method A, N is formed below the gate oxide film as shown in FIG.
An N-type impurity diffusion layer 105 is formed, a P-type impurity diffusion layer 104 is formed below the N-type impurity diffusion layer 105, and an N-type impurity diffusion layer 103 is formed below the P-type impurity diffusion layer 104. The buried channel type P-channel MOSFET thus formed is formed. The above-described embodiment merely shows an example of the present invention, and the present invention is not limited to this. For example, the gate oxidation conditions are as follows: oxidation in an oxygen atmosphere at a temperature of about 850 ° C., and then in a nitrogen atmosphere at a temperature of 900 ° C. to 1 ° C.
Although it has been described that the post-annealing at about 000 degrees is performed, the present invention is not limited to this. Under the condition that the arsenic introduced into the semiconductor substrate at the same time as forming the oxide film causes abnormal diffusion and the arsenic concentration on the substrate surface increases. I just need. That is, in the above-described embodiment, an oxygen atmosphere is described, but an atmosphere containing not only oxygen but also hydrogen and chlorine may be used.
A temperature range from 50 degrees to 950 degrees, and more specifically a temperature range from 800 degrees to 900 degrees, is desirable. In the above-described embodiment, the buried channel type P-channel MOSFET has been described as an example. However, the present invention is not limited to this. For example, the buried channel type N-channel MOSFET may be used.
It is also applicable to T. Next, a second embodiment of the present invention will be described. As shown in FIG. 3A, an N-type well is formed on the surface of a semiconductor substrate 301 containing silicon as a main component, and then thermally oxidized to form a silicon oxide film 3 having a thickness of about 20 nm on the surface.
After forming 02, BF ₂ is implanted as a P-type impurity by ion implantation at an energy of about 70 keV and a dose of about 3E12. The ions implanted here lose their energy while repeatedly colliding with atoms or electron clouds inside the semiconductor substrate, and most of the ions remain at a depth of about 0.1 μm from the surface of the semiconductor substrate 301, leaving a P-type impurity diffusion layer. Step 303 is formed. If the ions implanted at this time collide with the nuclei of the silicon substrate, the atoms move and damage the crystal of the semiconductor substrate. In the prior art, the gate oxide film 304 was formed by removing the silicon oxide film 302 with such implantation damage occurring and performing an oxidation process again in an oxidation furnace. Since the impurity diffusion at the time of oxidation is accelerated, the P-type impurity diffusion layer 303 is deeply distributed. In order to suppress the accelerated diffusion of impurities due to such implantation damage, in the present invention, after forming a P-type impurity diffusion layer 303 by ion implantation, the implantation damage is removed by performing high-temperature short-time annealing by RTA or the like. By performing the gate oxidation after that, the P-type impurity diffusion layer 303 can be distributed shallowly as shown in FIG. Here, the annealing conditions by the RTA method are as follows.
Good about 00 to 1100 degrees, more specifically 90
The temperature is suitably about 0 ° to 1050 °, and the annealing time varies depending on the temperature, but about 10 seconds to several tens seconds is appropriate. Next, polycrystalline silicon containing a high concentration of phosphorus as an impurity is formed to a thickness of about 300 nm on the gate oxide film 304 by a CVD method. This polycrystalline silicon may be deposited in a state containing no impurities and then pre-deposited with phosphorus, or may be deposited in a state containing a high concentration of phosphorus. Here, a buried channel type P channel MOS
Since the FET is described as an example, polycrystalline silicon containing high concentration of phosphorus is used. However, when a MOSFET of a surface channel type or the like is formed, phosphorus may not be contained. After passing through the lithography process and the etching process for the polycrystalline silicon formed here, an oxidation process for recovering the etching damage is performed to form the gate electrode 305, and then BF _{2 is used} as a P-type impurity.
Energy 40 keV dose 1 by ion implantation
By implanting about E13, the P-type impurity diffusion layer 30 is formed.
6 is formed. Then, after depositing a silicon oxide film of about 200 nm by the CVD method, the silicon oxide film is etched by about 200 nm by anisotropic etching such as dry etching, so that the side wall of the gate electrode 305 is formed of the silicon oxide film. The spacer 307 is formed. Next, P-type impurity diffusion layers 308 are formed in the source / drain portions by implanting BF ₂ with an energy of about 50 keV and a dose of about 2E15 by ion implantation. At this time,
Since the gate electrode contains a high concentration of phosphorus in advance, it has N-type conductivity. Next, by activating the impurities by annealing such as the RTA method, FIG.
As shown in (c), a buried channel P-channel MOSFET in which the depth of the P-type impurity diffusion layer 303 formed in the channel portion is small is formed. The above-described embodiment is merely an example of the present invention, and the present invention is not limited to this. For example, in the above-described embodiment, a buried channel type P-channel MOSFET has been described as an example. However, the present invention is not limited to this.
Channel MOSFET or surface channel type N-channel M
OSFET, surface channel type P-channel MOSFET
Application to is also possible. Here, an embodiment in the case where the present invention is applied to a surface channel type P-channel MOSFET will be described. As shown in FIG. 4A, an N-type well is formed on the surface of a semiconductor substrate 301 containing silicon as a main component, and then a silicon oxide film 402 having a thickness of about 20 nm is formed on the surface by thermal oxidation. After formation, phosphorus is implanted as an N-type impurity by ion implantation at an energy of about 50 keV and a dose of about 3E12. The ions implanted here lose their energy while repeatedly colliding with atoms or electron clouds inside the semiconductor substrate, and most of the ions are lost.
And the n-type impurity diffusion layer 403 is formed at a depth of about 0.1 μm from the surface of the substrate. If the ions implanted at this time collide with the nuclei of the silicon substrate, the atoms move and damage the crystal of the semiconductor substrate. In the prior art, the gate oxide film 404 was formed by removing the silicon oxide film 402 with such implantation damage occurring and performing a new oxidation treatment in an oxidation furnace. Since the speed of impurity diffusion during oxidation is increased, the N-type impurity diffusion layer 403 is deeply distributed. In order to suppress the accelerated diffusion of the impurity due to such implantation damage, in the present invention, after forming the N-type impurity diffusion layer 403 by ion implantation, the implantation damage is removed by performing high-temperature short-time annealing by RTA or the like. By performing gate oxidation after that, the N-type impurity diffusion layer 403 can be distributed shallowly as shown in FIG. Here, the annealing condition by the RTA method is preferably a temperature of about 800 ° C. to 1100 ° C., more preferably about 900 ° C. to 1050 ° C., and the annealing time varies depending on the temperature. To several tens of seconds is appropriate. Next, C is formed on the gate oxide film 404.
Polycrystalline silicon is formed to a thickness of about 300 nm by a VD method, and after a lithography process and an etching process, an oxidation process for recovering etching damage is performed to form a gate electrode 405. Then, BF _{2 is used} as a P-type impurity. Is implanted by ion implantation at an energy of about 40 keV and a dose of about 1E13 to form a P-type impurity diffusion layer 406. Then, after depositing a silicon oxide film of about 200 nm by a CVD method, the silicon oxide film is etched by about 200 nm by anisotropic etching such as dry etching, so that the side wall of the silicon oxide film is formed on the side wall of the gate electrode 405. A spacer 407 is formed. Next, P-type impurity diffusion layers 408 are formed in the source / drain portions by implanting BF ₂ with an energy of about 50 keV and a dose of about 2E15 by ion implantation. At this time, the gate electrode has a P-type conductivity. Then RT
By activating the impurities by annealing such as method A, a buried channel P-channel MOSFET having a shallow N-type impurity diffusion layer 303 formed in the channel portion is formed as shown in FIG. You. The first embodiment of the present invention and the second embodiment
In the embodiment, it is described that the well is formed in advance, but the present invention is not limited to this, and the well is formed by the high energy ion implantation method before and after the impurity is introduced into the channel portion. Needless to say, this is acceptable. The MOS described in the first embodiment of the present invention
In the FET, the third impurity diffusion layer formed below the second impurity diffusion layer serving as a buried channel layer suppresses the punch-through phenomenon and at the same time improves the sub-threshold characteristic. it can. By miniaturizing the elements, the parasitic capacitance can be reduced, so that not only the operation speed of the circuit can be improved and the power consumption can be reduced, but also the yield can be expected to be improved by reducing the chip size. Further, since the N-type first impurity diffusion layer is formed above the P-type buried channel layer, which is the second impurity diffusion layer, carriers can be kept on the substrate even when the element is in a conductive state. Since the gas flows through the inside, a decrease in mobility due to surface scattering can be suppressed. When the mobility of carriers is increased, the current driving capability is improved, so that the operation speed of the circuit can be increased. Therefore, a high-performance semiconductor device can be provided. In the buried channel MOSFET described in the second embodiment of the present invention, the punch-through phenomenon is suppressed by reducing the depth of the buried channel layer, and at the same time, the subthreshold characteristic is improved and the element is miniaturized. Can be realized. By miniaturizing the elements, the parasitic capacitance can be reduced, so that not only the operation speed of the circuit can be improved and the power consumption can be reduced, but also the yield can be expected to be improved by reducing the chip size. Further, in the surface channel type MOSFET described in the second embodiment of the present invention, the sub-threshold characteristic is improved by reducing the depth of the impurity in the channel portion, and the surface impurity concentration of the channel is lower than that of the conventional one. Even in the same case, the effective mobility is increased due to the low impurity concentration in a portion slightly deeper than the surface, so that an improvement in current driving capability can be expected. For these reasons, according to the present invention, a high-performance semiconductor device can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing a main step of an embodiment of the present invention. FIG. 2 is a depth distribution of an impurity concentration in a main process according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a main step of one embodiment of the present invention. FIG. 4 is a cross-sectional view showing a main step of the embodiment of the present invention. FIG. 5 is a cross-sectional view in a main step showing a conventional example. [Description of Reference Numerals] 101, 301, 401, and 501 are semiconductor substrates. 102, 302, 402, and 502 are oxide films. 103 and 105 are N-type impurity diffusion layers. 104, 108, 110, 303, 306, 308, 4
Reference numerals 06, 408, 503, 506, and 508 denote P-type impurity diffusion layers. Reference numerals 106, 304, 404, and 504 are gate insulating films. 107, 305, 405, and 505 are gate electrodes. 109, 307, 407, and 507 are side wall spacers. Reference numeral 201 denotes an arsenic impurity concentration distribution. Reference numeral 202 denotes a boron impurity concentration distribution.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-6-236967 (JP, A) JP-A-6-132524 (JP, A) JP-A-3-203243 (JP, A) JP-A-5-205 55232 (JP, A) JP-A-59-193066 (JP, A) JP-A-60-50960 (JP, A) JP-A-56-142671 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) H01L 29/78 H01L 21/336

Claims (1)

(57) Claims 1. A step of forming a first first conductivity type region by introducing a first conductivity type impurity into a semiconductor substrate; and forming a second conductivity type impurity in the semiconductor substrate. Forming a second conductivity type region above the first first conductivity type region, forming a gate insulating film by thermally oxidizing the surface of the semiconductor substrate, A method for manufacturing a semiconductor device, comprising: a step of forming a gate electrode on an insulating film; and a step of introducing a second conductivity type impurity into a source / drain portion, wherein the thermal oxidation forming the gate insulating film Forming a second first conductivity type region in the semiconductor substrate above the second conductivity type region by diffusing the first conductivity type impurity constituting the first first conductivity type region. Features of semiconductor device Production method.