JPH06140590A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve the yield of bridging between a source and drain and gate electrodes by forming the p<->-area of the source and drain of a p-channel MOSFET and the p<+>-area of the source and drain of the MOSFET by forming a second insulating film on the side sections of the gate electrodes. CONSTITUTION:After an n-well 102 and a p-well 103 are formed on the surface of a p-type substrate 101, field oxide films 104 are formed. Then a gate oxide film 105 is formed and gate electrodes 106 are formed by depositing non-doped polysilicon 106. Thereafter, a photoresist 125 is formed after successively depositing a silicon nitride film 107 and silicon oxide film 108 and the silicon oxide film 108 is removed from an n-MOSFET area. After removing the film 108, the n<+>-arsenic area 127 of the source and drain of an n-MOSFET is formed by forming side walls 126 and implanting arsenic ions. Thereafter, the side walls 126 are removed and phosphorus ions are implanted, and then, an oxide film 128 is deposited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a short-channel CMOS transistor, in which source / drain formation is further simplified and the manufacturing cost is reduced.

[0002]

2. Description of the Related Art For forming a source / drain of a CMOS, one photomask is used for an n-channel transistor and one photomask is used for a p-channel transistor. In addition, as the device has a shorter channel, it is necessary to use a low doping concentration in the source / drain structure, attach sidewalls to the gate electrode, and then form the source / drain electrode at a high concentration. Therefore, two more photomasks are used. In other words, four photomasks are generally used for forming the CMOS source / drain.

Here, a conventional method of manufacturing a CMOS will be described with reference to the sectional views of FIGS. 5 and 6 and the process flow of FIG.

P-type silicon 101 with n-well 102, p
A well 103 is formed, and a field oxide film 104 is further formed by, for example, a selective oxidation method as shown in the element sectional view of FIG. Next, the gate oxide film 105 is formed to a film thickness of 10
nm (nanometer), non-doped polysilicon 106 is deposited to a film thickness of 300 nm, and a polysilicon gate electrode 106 is formed by using photolithography as shown in the cross-sectional view of the device in FIG. After forming the gate electrode, a photoresist 119 is formed by using the photolithography technique, and this is used as a mask for ion implantation, and phosphorus is added to the p-well at 40 keV and 2 × 10 ¹³ / cm 3.
About ² ions are implanted to form n ⁻ regions 113 of the source / drain of the nMOSFET as shown in the element cross-sectional view of FIG. 5C. Next, using a photolithography technique, a photoresist 120 is formed, and this is used as an ion implantation mask to form boron in the n well at 15 keV and 2 × 10 ^13.
/ Cm ² is injected into the p ^- region 109 of the source / drain of the pMOSFET as shown in the element cross-sectional view of FIG. 5D. Next, as shown in the element cross-sectional view of FIG. 5E, a silicon oxide film 121 is deposited to a film thickness of about 150 nm, and the silicon oxide film is anisotropically etched as shown in the element cross-sectional view of FIG. 6A. 121 to form the sidewall 122, and using the photolithography technique,
A photoresist 123 is formed, and using this as an ion implantation mask, arsenic is deposited on the p-well and the polysilicon on the p-well.
Ion implantation of 5 × 10 ¹⁵ / cm ^{2 at 0} keV, nM
An n ⁺ region 116 of the source / drain of the OSFET is formed. Next, using the photolithography technique once again, as shown in the element sectional view of FIG.
And then using this as an ion implantation mask, 5 × 1 of BF ₂ is applied to the n-well and the polysilicon on the n-well at 50 keV.
Ions are implanted by about 0 ¹⁵ / cm ² to form the p ⁺ regions 112 of the source / drain of the pMOSFET. Next, for example, N ₂ annealing is performed at 850 ° C. for about 30 minutes to activate the source / drain of the transistor and the region of the polysilicon electrode, and then titanium 117, for example, is used as shown in the element cross-sectional view of FIG. A film thickness of about 40 nm is deposited. Next, when heat treatment is performed at a temperature of about 700 degrees Celsius, titanium silicide 118 is formed in only the gate polysilicon and the diffusion layer in a self-aligned manner, and then silicidation is performed as shown in the element cross-sectional view of FIG. Only the remaining titanium and the reaction product thereof are selectively removed from the insulating film.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In forming the source / drain of the OS transistor, as is clear from the process flow after forming the gate electrode in FIG.
Four photomasks are used. Regarding the photolithography technique, the process used is not a batch process but mainly a single wafer process, and the alignment exposure apparatus used is expensive and a relatively expensive process. In addition, the photolithography process has a relatively large impact on yield degradation. Since there are such problems regarding the manufacturing price, it would be advantageous if the photolithography process could be reduced.

Further, this conventional n-channel MOSF is used.
The polysilicon electrode of ET is doped by arsenic ion implantation in order to suppress the short channel effect. 0.4 μm
The following CMOS technologies have problems with short channel effects when phosphorus is used instead of arsenic. On the other hand, if arsenic is used and activated at a low temperature and for a short time in order to suppress the short channel effect, it is difficult to obtain a sufficient doping concentration in the entire polysilicon layer. There is a problem that causes deterioration of the characteristics of.

When the silicide process is used, a thicker sidewall is required as compared with the optimal sidewall thickness for n-channel transistor characteristics so that the source / drain silicide does not short-circuit with the gate electrode silicide. Is. That is, the thickness of the sidewall for obtaining a high yield of the silicide process is
There is a problem that it is too thick at least for the device characteristics of the n-channel MOSFET. Also, since the silicide reaction consumes a large amount of silicon, most of the silicon in the shallow source / drain diffusion layer for suppressing the short channel effect is reacted, and as a result, the junction leakage current increases and the source / drain parasitic Resistance is rising. That is, with respect to the source / drain junction depth, the short channel effect and the salicide process have different requirements.

Moreover, since the source / drain junction depths of the n-channel MOSFET and the p-channel MOSFET are different, the optimum sidewall thickness of the n-channel MOSFET is different from that of the p-channel in terms of device characteristics. Therefore, n-channel MOSFET and p-channel MOSFET
There was a problem that each of the above could not be optimized independently.

[0009]

A feature of the present invention is that an n-channel MOS of a CMOS integrated circuit is provided on one main surface of a semiconductor substrate.
In a method of forming a FET and a p-channel MOSFET, a step of forming gate electrodes of both MOSFETs, a step of depositing a double layer having a lower layer of a silicon nitride film and an upper layer of a silicon oxide film on the entire surface, and the n-channel MO
Selectively removing the double-layered silicon oxide film from the formation region of the SFET and forming a sidewall of the silicon nitride film on the side of the gate electrode of the n-channel MOSFET; Forming a first n ⁺ region of the drain, said n channel M
Removing the side wall of the silicon nitride film of the OSFET to form the n ⁻ regions of the source / drain of the n-channel MOSFET; and forming the side wall of the first insulating film on the side of the gate electrode of the n-channel MOSFET. And removing the double-layered silicon oxide film remaining in the formation region of the p-channel MOSFET, and the n-channel MOS
Forming a second n ⁺ region of the source / drain of the FET, removing the double-layered silicon nitride film remaining in the region of the p-channel MOSFET, and p of the source / drain of the p-channel MOSFET ^- semiconductor including the steps of forming a region, and the step of the side walls of the second insulating film is formed on the side of the gate electrode of the p-channel MOSFET, to form a p ⁺ region of the source and drain of the p-channel MOSFET It is in the method of manufacturing the device.

Another feature of the present invention is that in a method of forming an n-channel MOSFET and a p-channel MOSFET of a CMOS integrated circuit on one main surface of a semiconductor substrate, both MOSs are provided.
Forming a gate electrode of the FET; depositing a double layer having a lower layer of a silicon nitride film and an upper layer of a silicon oxide film on the entire surface; and selectively forming the double layer from the formation region of the p-channel MOSFET. Are removed to form p ⁻ regions of the source / drain of the p-channel MOSFET, a side wall of the first insulating film is formed on the side of the gate electrode of the p-channel MOSFET, and the p-channel MOSF is formed.
A step of forming a p ⁺ region of the source / drain of ET; a step of removing the double-layer silicon nitride film remaining in the formation region of the n-channel MOSFET; and a step of removing the source / drain n ⁻ region of the n-channel MOSFET. Formed,
A second electrode is provided on the side of the gate electrode of the n-channel MOSFET.
Forming an insulating film sidewall of the n-channel MOSFET
And a step of forming n ⁺ regions of the source / drain.

[0011]

EXAMPLE A first example of the present invention will now be described with reference to FIGS. 1 and 2 showing cross-sectional views in the order of steps and FIG. 7 showing a step flow after formation of a gate electrode.

An n-well 102 and a p-well 103 are formed on a p-type substrate 101, and a filled oxide film 104 is further formed by, for example, a selective oxidation method as shown in the element sectional view of FIG. Next, a gate oxide film 105 is formed to a film thickness of about 10 nm, and non-doped polysilicon 106 is formed to a film thickness of 300 nm.
Then, the gate electrode 106 is formed by photolithography as shown in the element cross-sectional view of FIG. Next, a silicon nitride film 107 is deposited to a film thickness of 150 nm, a silicon oxide film 108 is deposited to a film thickness of 50 nm, and a photoresist 125 is formed using a photolithography technique as shown in the element cross-sectional view of FIG. Then, using this as an etching mask, the silicon oxide film 108 in the nMOSFET region is removed by isotropic etching. Next, the sidewalls 12 are anisotropically etched.
6 is formed, FIG. 1 nMOSFET source drain in the n ⁺ arsenic region 12 of arsenic as shown in element cross section by ion implantation about 1 × 10 ¹⁵ / cm ² at 70keV in (D)
Form 7. Next, hot phosphoric acid is used to form the sidewall 12
6 was removed, and phosphorus was ion-implanted at 40 keV to about 2 × 10 ¹³ / cm ² to form the n ⁻ regions 113 of the source and drain of the nMOSFET, and an oxide film was formed as shown in the element cross-sectional view of FIG. 128 is deposited to a film thickness of 300 nm.
Next, the sidewalls 129 are formed by anisotropic etching, and phosphorus is used as shown in the element cross-sectional view of FIG.
Ion implantation of 5 × 10 ¹⁵ / cm ^{2 at 0} keV and nM
An n ⁺ phosphorus region 130 of the source / drain of the OSFET is formed. Next, the silicon nitride film 10 remaining in the n-well
7 was removed, and boron was 2 × 10 ¹³ / cm ² at 15 keV.
More ion implantation is performed to form p ⁻ regions 109 of the source / drain of the pMOSFET, and a silicon oxide film 131 is deposited to a thickness of 150 nm as shown in FIG. Next, the sidewalls 132 are formed by anisotropic etching, and BF ₂ is applied at 50 keV for 5 hours as shown in FIG.
Ions are implanted at about 10 ¹⁵ / cm ² to form the p ⁺ regions 112 of the source / drain of the pMOSFET. That B
Although the F ₂ ion implantation also enters the nMOSFET region, the activated concentration of phosphorus is much higher than that of BF ₂ , and the junction depth of phosphorus can be deeper than BF ₂ , so that the nMOSF
The ET phosphorous-doped source / drain and polysilicon electrodes are preserved. Next, when the silicide technique is used, for example, heat treatment is performed at a temperature of 850 degrees Celsius to activate the ion-implanted impurities in the source / drain and the polysilicon electrode, and as shown in the element cross-sectional view of FIG. Titanium 117 is deposited to a film thickness of 40 nm.
Next, after the silicidation reaction is performed at a temperature of about 700 degrees Celsius, the titanium reaction product only in the insulating film is selectively removed, and titanium is removed as shown in the element cross-sectional view of FIG. The silicide 118 is diffused and formed only in the region of the polysilicon electrode.

In this embodiment, as can be seen from the above example,
Since the thick sidewalls are used without degrading the device characteristics, as shown in FIG. 11, it has the effect of improving the yield in terms of bridging of the source / drain and gate electrodes.

Moreover, since the present invention uses a deeper source / drain junction than the prior art, in the case of the silicide process, the junction leakage current and large parasitic resistance associated with the shallow junction can be avoided. Therefore, as shown in FIG. 12, there is an effect that the reliability is improved. Since the deterioration of the short channel effect can be suppressed even though the junction is deep,
The device characteristics can be improved as shown by the dependence of the threshold voltage on the gate electrode length.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4 which show cross sections in the order of steps and FIG. 8 which shows a step flow after gate electrode formation.

An n-well 102 and a p-well 103 are formed on a p-type substrate 101, and a field oxide film 104 is further formed by, for example, a selective oxidation method as shown in the element sectional view of FIG. Next, the gate oxide film 105 is formed to a film thickness of 10 nm.
And the non-doped polysilicon 106 is formed to a film thickness of 30
Deposited about 0 nm, doped the film with phosphorus diffusion,
As shown in the device cross-sectional view of FIG. 3B, the gate electrode 10 of phosphorus-doped polysilicon is formed by using the photolithography technique.
6 is formed. Next, the silicon nitride film 107 is formed to a film thickness of 15
The silicon oxide film 108 is deposited to a film thickness of 50 n.
m, and a photoresist 125 is formed by using the photolithography technique as shown in the cross-sectional view of the element of FIG. 3C, and this is used as a mask to form the oxide film 10 of the pMOSFET.
8 is removed by isotropic etching. Next, using the remaining silicon oxide film 108 as a mask, the silicon nitride film 107 of the pMOSFET is removed by hot phosphoric acid to remove boron by 1
PM by ion implantation of about 2 × 10 ¹³ / cm ² at 5 keV
A source / drain p ⁻ region 109 of the OSFET is formed, and a silicon oxide film 110 is deposited to a film thickness of about 200 nm as shown in the element sectional view of FIG. Next, the sidewalls 111 of the silicon oxide film 110 are formed by anisotropic etching, and BF ₂ is 5 × 1 at 50 keV.
Ion implantation of about 0 ¹⁵ / cm ^{2 is performed, and} as shown in the device cross-sectional view of FIG.
^{A +} region 112 is formed. Next, the silicon nitride film 107 remaining in the p well 103 is removed by hot phosphoric acid, and phosphorus is ion-implanted at 2 × 10 ¹³ / cm ² at 40 keV to form the n ⁻ region 113 of the source / drain of the nMOSFET. Then, as shown in the element cross-sectional view of FIG. 4B, an oxide film 114 is deposited to a film thickness of about 150 nm. Next, a sidewall 115 of a silicon oxide film is formed by anisotropic etching, and arsenic is added at 3 × 10 ¹⁵ / c at 70 keV.
as m ² and Io injection, the source and drain of the nMOSFET as shown in element cross-sectional view of FIG. 4 (C) n ⁺ region 11
6 is formed. Another photomask is used to prevent arsenic from entering the pMOSFET region, while an ohmic contact tunnel diode can be made without using that photomask. Whichever method is used, the number of lithography steps is reduced as a whole as compared with the conventional technique. This second embodiment is similar to the first embodiment as shown in FIG.
The effects shown in FIGS. 1, 12 and 13 are obtained.

[0017]

As described above, according to the present invention, it is possible to use three photomasks less than the conventional manufacturing method. Although the CVD deposition process and the etching process are increased as shown in FIGS. 7 to 9, there is an effect that the number of lithography processes having a relatively high manufacturing cost is reduced and the manufacturing cost is reduced as a whole. In addition, the present invention uses a small number of photolithography steps, so that the yield can be improved, and as a result, the manufacturing cost can be further reduced.

Further, according to the present invention, even in the case of an np gate CMOS, the characteristics of the short channel transistor are not deteriorated.
Phosphorus doping can be used for the gate electrode of the channel MOSFET. Therefore, as compared with the conventional technique, the doping concentration of the electrode can be increased, which has the effect of improving the device characteristics as shown in FIG. or,
Since the present invention uses one sidewall thickness for the n-channel MOSFET and the other for the p-channel MOSFET, the p-channel and n-channel source
The drain structure can be optimized separately. Therefore, the CMO
This has the effect of improving the device characteristics of S.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a CMOS according to a first embodiment of the present invention in the order of steps.

2A to 2D are cross-sectional views sequentially showing a step following that of FIG.

FIG. 3 is a cross-sectional view showing, in the order of steps, a method for manufacturing a CMOS according to the second embodiment of the present invention.

4A to 4C are cross-sectional views sequentially showing a step following that of FIG.

FIG. 5 is a cross-sectional view showing a method of manufacturing a CMOS in the related art in the order of steps.

6A to 6C are cross-sectional views sequentially showing a step following that of FIG.

FIG. 7 is a diagram showing a manufacturing process flow of the first embodiment of the present invention.

FIG. 8 is a diagram showing a manufacturing process flow of the second embodiment of the present invention.

FIG. 9 is a view showing a manufacturing process flow of a conventional technique.

FIG. 10 is a diagram showing a comparison between transistor drain currents of the present invention and a conventional technique.

FIG. 11 is a diagram showing a comparison between the yields of the present invention and the prior art.

FIG. 12 is a diagram showing a comparison between junction leakage currents of the present invention and the prior art.

FIG. 13 is a diagram showing the gate electrode length dependence of the threshold voltage in the present invention and the prior art.

[Explanation of symbols]

101 p-type substrate 102 n-well 103 p-well 104 field oxide film 105 gate oxide film 106 polysilicon gate electrode 107 silicon nitride film for ion implantation mask 108 silicon oxide film for hot phosphoric acid etching mask 109 source of pMOSFET P ⁻ region of drain 110 silicon oxide film for sidewall of pMOSFET 111 sidewall of pMOSFET 112 p ⁺ region of source / drain of pMOSFET 113 n ⁻ region of source / drain of nMOSFET 114 silicon for sidewall of nMOSFET n of the source and drain of the n ⁺ region 117 titanium 118 titanium silicide 119 source and drain sidewalls 116 nMOSFET oxide film 115 nMOSFET ^- Photoresist mask 120 source and drain of the phosphorus ions implanted frequency p ^- region boron ion implantation photoresist mask 121 photoresist mask arsenic ion implantation of the silicon oxide film 122 sidewall 123 of the source-drain n ⁺ region for the sidewall 124 Photoresist mask for BF ₂ ion implantation of p ⁺ region of source / drain 125 Photoresist for forming source / drain of CMOS 126 Sidewall 127 n ⁺ source / drain n ⁺ arsenic region 128 silicon oxide film 129 Sidewall 130 nMOSFET source / source N ⁺ phosphorus region of drain 131 silicon oxide film 132 sidewall

Claims (2)

[Claims] 1. A method of forming a first conductivity type channel MOSFET and a second conductivity type channel MOSFET of a CMOS integrated circuit on one main surface of a semiconductor substrate, comprising the steps of forming gate electrodes of both channel MOSFETs, A step of depositing a double layer in which a lower layer is a silicon nitride film and an upper layer is a silicon oxide film on the surface, and the silicon oxide film of the double layer is selectively removed from the formation region of the first conductivity type channel MOSFET, The first conductivity type channel MO
Forming a sidewall of the silicon nitride film on the side of the gate electrode of the SFET, and the first conductivity type channel MOSF
Forming a first region of the first conductivity type having a relatively high impurity concentration in the source / drain of ET; removing a sidewall of the silicon nitride film of the first conductivity type channel MOSFET; Of a first conductivity type region having a relatively low impurity concentration in the source / drain of the first conductivity type channel MOSFET, and the first conductivity type channel MOSF
Forming a sidewall of the first insulating film on the side of the gate electrode of ET and removing the double-layered silicon oxide film remaining in the formation region of the second conductivity type channel MOSFET;
Forming a second region of the first conductivity type having a relatively high impurity concentration in the source / drain of the first conductivity type channel MOSFET; and the second conductivity type channel MOSFE.
Removing the double-layered silicon nitride film remaining in the T region, and forming a second conductivity type region having a relatively low impurity concentration in the source / drain of the second conductivity type channel MOSFET, The second conductivity type channel MOS
Forming a side wall of the second insulating film on the side of the gate electrode of the FET, and forming a second conductivity type region having a relatively high impurity concentration in the source / drain of the second conductivity type channel MOSFET. A method of manufacturing a semiconductor device, comprising: 2. A method of forming a first conductivity type channel MOSFET and a second conductivity type channel MOSFET of a CMOS integrated circuit on one main surface of a semiconductor substrate, the method comprising the steps of forming gate electrodes of the both channel MOSFETs. A step of depositing a double layer having a lower layer of a silicon nitride film and an upper layer of a silicon oxide film on the surface, and selectively removing the double layer from a region where the second conductivity type channel MOSFET is formed, A second conductivity type region having a relatively low impurity concentration of the source / drain of the second conductivity type channel MOSFET is formed, and a side wall of the first insulating film is formed on a side portion of the gate electrode of the second conductivity type channel MOSFET. Removing the double-layered silicon oxide film remaining in the first conductivity type channel region; and the second conductivity type channel MOS.
Forming a second conductivity type region having a relatively high impurity concentration in the source / drain of the FET; removing the double-layered silicon nitride film remaining in the first conductivity type channel MOSFET region; First conductivity type channel MO
A first conductivity type region having a relatively low impurity concentration of the source / drain of the SFET is formed, and a sidewall of a second insulating film is formed on a side portion of the gate electrode of the first conductivity type channel MOSFET. And a step of forming a region of the first conductivity type having a relatively high impurity concentration in the source / drain of the one conductivity type channel MOSFET.