JP4115769B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a CMOS structure and a manufacturing method thereof.
[0002]
[Prior art]
Recently, with miniaturization, the gate length of a MOS transistor tends to be shortened.
[0003]
However, if the gate length is simply shortened, the transistor cannot be turned off.
[0004]
Therefore, an extension region of the source / drain diffusion layer can be formed by forming a sidewall spacer on the side surface of the gate electrode and implanting dopant impurities into the gate electrode on which the sidewall spacer is formed in a self-aligned manner. Has been done.
[0005]
If a dopant impurity is introduced in a self-aligned manner into a gate electrode having sidewall spacers formed on the side surfaces, the region into which the dopant impurity is introduced can be offset, so that even if the gate electrode is shortened, the transistor It can be turned off.
[0006]
[Problems to be solved by the invention]
However, while B used as a dopant impurity when forming the extension region of the PMOS transistor has a high diffusion rate during the heat treatment, As used as a dopant impurity when forming the extension region of the NMOS transistor is used during the heat treatment. The diffusion rate is slow. For this reason, in a semiconductor device having a CMOS structure, good electrical characteristics may not be obtained in either one of the NMOS transistor and the PMOS transistor.
[0007]
As shown in FIG. 12A, when the sidewall spacer 122 is formed thinly on the side surface of the gate electrode 120, an NMOS transistor 116b having a short gate length and good electrical characteristics can be obtained. In 116a, the channel length becomes extremely short and cannot be normally turned off.
[0008]
On the other hand, as shown in FIG. 12B, when the sidewall spacer 122 is formed thicker on the side surface of the gate electrode 120, both the NMOS transistor 126b and the PMOS transistor 126a can be turned on / off. In the NMOS transistor 126b, the length of the portion where the extension region 130 and the gate electrode 120 overlap is too short.
[0009]
FIG. 13 is a graph showing the relationship between the length of the portion where the gate electrode and the extension region overlap and the saturation current (reference: S. Thompson et al. Symp. On VLSI Tech. P.132). , 1998). The horizontal axis indicates the length of the overlap between the gate electrode and the extension region, and the vertical axis indicates the saturation current I _DSAT Is shown. FIG. 13 shows the measurement for the NMOS transistor. ■ in the figure indicates the thickness T of the gate insulating film _OX Is 4.5nm, power supply voltage V _CC Is 1.8V, gate length L _E Is 0.12 μm, and ▲ is T _OX , V _CC , L _E Is multiplied by 0.7, and ● is T _OX , V _CC , L _E Is multiplied by 0.5. In either case, the power supply voltage V _CC Is 1.8V and gate length L _E Is 0.12 μm. As can be seen from FIG. 13, if the length of the portion where the extension region and the gate electrode overlap is too short, the parasitic resistance increases and the on-current decreases. As described above, when the sidewall spacer is formed thick, a PMOS transistor having good electrical characteristics can be obtained. On the other hand, the on-current of the NMOS transistor is reduced.
[0010]
As described above, in the semiconductor device having the CMOS structure, if the gate length is further reduced, it is impossible to obtain good electrical characteristics in either the NMOS transistor or the PMOS transistor.
[0011]
An object of the present invention is to provide a semiconductor device having a CMOS structure capable of realizing good electrical characteristics in both NMOS and PMOS transistors even when the gate length is shortened, and a method for manufacturing the same. is there.
[0013]
[Means for Solving the Problems]
Up The purpose is In the method for manufacturing a semiconductor device, the PMOS transistor and the NMOS transistor are formed on a semiconductor substrate. Forming a gate electrode on the semiconductor substrate via an insulating film; forming a sidewall spacer on a side surface of the gate electrode; In the semiconductor substrate on both sides of the gate electrode of the PMOS transistor, a first extension region in which B is introduced as a dopant impurity using the gate electrode on which the sidewall spacer is formed as a mask, and As as a dopant impurity Forming a first pocket region into which the NMOS transistor is introduced, and the NMOS transistor In the semiconductor substrate on both sides of the gate electrode And forming a second extension region in which As is introduced as a dopant impurity using the gate electrode on which the sidewall spacer is formed as a mask. And a process of After the step of forming the second extension region, the second extension region Include As dopant impurities Amorphous by introducing Forming a second pocket region including the region And a process of By forming a first impurity diffusion region deeper than the first extension region in the semiconductor substrate on both sides of the gate electrode of the PMOS transistor, the first extension region, the first impurity diffusion region, and Forming a first source / drain region of the PMOS transistor having a second impurity diffusion region deeper than the second extension region in the semiconductor substrate on both sides of the gate electrode of the NMOS transistor. Forming a second source / drain region of the NMOS transistor having the second extension region and the second impurity diffusion region, and the first source / drain region and the second source. After the step of forming the / drain region, the dopant impurity Heat treatment to activate Craft It is achieved by a method for manufacturing a semiconductor device, characterized by comprising:
[0014]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment.
[0015]
(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIG.
[0016]
As shown in FIG. 1, an n-type well 12 is formed in a p-type silicon substrate 10.
[0017]
In the silicon substrate 10, element isolation regions 15 that define element regions 14a and 14b are formed.
[0018]
A PMOS transistor 16a is formed in the element region 14a on the right side of the drawing, and an NMOS transistor 16b is formed in the element region 14b on the left side of the drawing.
[0019]
First, the PMOS transistor 16a formed in the element region 14a on the right side of the page will be described.
[0020]
On the element region 14a, for example, SiO ₂ A gate insulating film 18 is formed.
[0021]
On the gate insulating film 18, a gate electrode 20a made of, for example, polysilicon is formed.
[0022]
A side wall spacer 22a made of, for example, SiN is formed on the side surface of the gate electrode 20a. The thickness of the sidewall spacer 22a is, for example, 5 to 20 nm.
[0023]
In the silicon substrate 10 on both sides of the gate electrode 20a having side wall spacers 22a formed on the side surfaces, a p-type extension region 24a constituting a shallow region of the extension source / drain is formed. In the extension region 24a, B (boron) is introduced as a dopant impurity. The dose amount of B is, for example, 2 × 10 ¹⁴ ~ 2x10 ¹⁵ cm ^-2 It has become. The end portion of the extension region 24a and the end portion of the gate electrode 20a overlap each other. The overlap capacitance between the extension region 24a and the gate electrode 20a is, for example, 0.25 [fF / μm] on one side. The overlap capacitance is a region where the gate electrode overlaps with the source / drain below the gate electrode, that is, a capacitance of the overlap region. The overlap capacity is proportional to the length of the overlap region.
[0024]
An n-type pocket region 26 is formed in the silicon substrate 10 on both sides of the gate electrode 20a where the sidewall spacers 22a are formed. The pocket region 26 is formed adjacent to the extension region 24a. In the pocket region 26, As is introduced as a dopant impurity. The dose amount of As is, for example, 1.6 × 10 ¹³ ~ 8x10 ¹³ cm ^-2 It has become. The pocket region 26 is for suppressing the short channel effect by suppressing the spread of the depletion layer.
[0025]
A side wall spacer 28 is further formed on the side surface of the side wall spacer 22.
[0026]
In the silicon substrate 10 on both sides of the gate electrode 20 on which the side wall spacers 22 and 28 are formed on the side surfaces, a p-type impurity diffusion region 24b constituting a deep region of the extension source / drain is formed. B is introduced into the impurity diffusion region 24b as a dopant impurity. The dose amount of B is, for example, 4 × 10 ¹⁵ ~ 1x10 ¹⁶ cm ^-2 It has become.
[0027]
The extension region 24a and the impurity diffusion region 24b constitute a source / drain diffusion layer 24 having an extension source / drain structure.
[0028]
Thus, the PMOS transistor 16a is formed in the element region 14a on the right side of the drawing.
[0029]
Next, the NMOS transistor 16b formed in the element region 14b on the left side of the page will be described.
[0030]
A gate electrode 20b is formed on the element region 14b with a gate insulating film 18 interposed therebetween.
[0031]
Side wall spacers 22b are formed on the side surfaces of the gate electrode 20b in the same manner as described above. The thickness of the sidewall spacer 22b is, for example, 5 to 20 nm as described above.
[0032]
In the silicon substrate 10 on both sides of the gate electrode 20b on which the sidewall spacer 22b is formed, an n-type extension region 30a constituting a shallow region of the extension source / drain is formed. As is introduced into the extension region 30a as a dopant impurity. The dose amount of As is, for example, 4 × 10 ¹⁴ ~ 2x10 ¹⁵ cm ^-2 It has become. The end portion of the extension region 30a and the end portion of the gate electrode 20 overlap each other. The length of the portion where the extension region 30a and the gate electrode 20b overlap is substantially equal to the length of the portion where the extension region 24a and the gate electrode 20a overlap. Similar to the overlap capacitance between the extension region 24a and the gate electrode 20a, the overlap capacitance between the extension region 30a and the gate electrode 20b is, for example, 0.25 [fF / μm] on one side.
[0033]
A p-type pocket region 32 is formed in the silicon substrate 10 on both sides of the gate electrode 20b having side wall spacers 22b and 28b formed on the side surfaces. The pocket region 32 is formed adjacent to the impurity diffusion region 30a. In the pocket region 32, In is introduced as a dopant impurity. The dose amount of In is, for example, 4 × 10 ¹³ ~ 8x10 ¹³ cm ^-2 It is high.
[0034]
The reason why the In dose is set high in this embodiment will be described in detail when the method for manufacturing the semiconductor device according to this embodiment is described.
[0035]
A side wall spacer 28b is further formed on the side surface of the side wall spacer 22b in the same manner as described above.
[0036]
In the silicon substrate 10 on both sides of the gate electrode 20b on which the sidewall spacers 22b and 28b are formed, an n-type impurity diffusion region 30b constituting a deep region of the extension source / drain is formed.
[0037]
The extension region 30a and the impurity diffusion region 30b constitute a source / drain diffusion layer 30 having an extension source / drain structure.
[0038]
Thus, the NMOS transistor 16b is formed in the element region 14b on the left side of the drawing.
[0039]
The semiconductor device according to the present embodiment includes the extension region 30a and the gate electrode 2. 0 b overlaps with each other, the extension region 24a and the gate electrode 2 0 The main feature is that the lengths of the portions where a overlaps each other are set to be approximately equal.
[0040]
In the conventional semiconductor device, the length of the portion where the extension region and the gate electrode overlap in the PMOS transistor is greatly different from the length of the portion where the extension region and the gate electrode overlap in the NMOS transistor. In some cases, good electrical characteristics cannot be obtained in either one of the PMOS transistor and the NMOS transistor.
[0041]
On the other hand, in this embodiment, the extension region 30a and the gate electrode 2 0 b overlaps with each other, the extension region 24a and the gate electrode 2 0 The length of the portion where a overlaps with each other is substantially equal. Therefore, according to the present embodiment, it is possible to provide a semiconductor device having a CMOS structure capable of realizing good electrical characteristics even when the gate length is shortened.
[0042]
(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 2 to 6 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.
[0043]
First, as shown in FIG. 2A, an n-type well 12 is formed on a p-type silicon substrate 10 by, eg, ion implantation.
[0044]
Next, the element isolation region 15 that defines the element regions 14a and 14b is formed by, for example, the STI method.
[0045]
Next, on the surface of the element regions 14a and 14b, for example, by a thermal oxidation method, for example, SiO 2 ₂ A gate insulating film 18 having a thickness of 2 nm is formed.
[0046]
Next, a 100 nm-thickness polysilicon film is formed on the entire surface by, eg, CVD. Thereafter, the polysilicon film is patterned using a photolithography technique. Thereby, gate electrodes 20a and 20b made of polysilicon are formed.
[0047]
Next, a SiN film having a thickness of 10 to 25 nm is formed on the entire surface by, eg, CVD. Thereafter, the SiN film is anisotropically etched. Thus, sidewall spacers 22a and 22b made of SiN are formed on the side surfaces of the gate electrodes 20a and 20b (see FIG. 2B). The thickness of the side wall spacers 22a and 22b is, for example, about 5 to 20 nm.
[0048]
Next, a photoresist film 34 is formed on the entire surface by, eg, spin coating. Thereafter, the photoresist film 34 is patterned using a photolithography technique. Thus, an opening 36 exposing the region where the PMOS transistor is to be formed is formed in the photoresist film 34 (see FIG. 3A).
[0049]
Next, B ions are implanted by ion implantation using the gate electrode 20a having the sidewall spacers 22a formed on the side surfaces and the photoresist film 34 as a mask. The ion implantation conditions are, for example, an acceleration voltage of 0.2 to 0.5 keV and a dose amount of 2 × 10. ¹⁴ ~ 2x10 ¹⁵ And Thus, the p-type extension region 24a constituting the shallow region of the extension source / drain is formed.
[0050]
Note that the region near the surface of the silicon substrate 10 is made amorphous by the implantation of B ions. The amorphous region 25 which is a region made amorphous by the implantation of B ions is represented by a broken line in the drawing. Since B is an element having a small mass, the amorphous region 25 is not formed in a deep region of the silicon substrate 10 and is formed only in a region near the surface of the silicon substrate 10.
[0051]
Next, as shown in FIG. 3B, As ions are implanted by an ion implantation method using the gate electrode 20a having the sidewall spacers 22a formed on the side surfaces and the photoresist film 34 as a mask. The ion implantation conditions are, for example, as follows. The acceleration voltage is, for example, 30 to 60 keV. The angle at which As ions are implanted is, for example, 30 degrees with respect to the normal of the surface of the silicon substrate 10. The dose amount is, for example, 1.6 × 10 ¹³ ~ 8x10 ¹³ cm ^-2 And At this time, As ions are implanted from four directions. The dose per direction is 0.4 × 10 ¹³ ~ 2x10 ¹³ cm ^-2 And Thus, the n-type pocket region 26 is formed.
[0052]
Since As is an element having a relatively small mass, the amorphous region 25 is not formed up to a deep region of the silicon substrate 10.
[0053]
Thereafter, the photoresist film 34 is removed.
[0054]
Next, a photoresist film 38 is formed on the entire surface by, eg, spin coating. Thereafter, the photoresist film 38 is patterned by using a photolithography technique. Thus, an opening 40 exposing the region where the NMOS transistor is to be formed is formed in the photoresist film 38 (see FIG. 4A).
[0055]
Next, As ions are implanted by ion implantation using the gate electrode 20b having the sidewall spacers 22b formed on the side surfaces and the photoresist film 38 as a mask. The ion implantation conditions are, for example, an acceleration voltage of 0.5 to 5 keV and a dose amount of 4 × 10. ¹⁴ ~ 2x10 ¹⁵ And Thus, the n-type extension region 30a constituting the shallow region of the extension source / drain is formed.
[0056]
Note that the region near the surface of the silicon substrate 10 is made amorphous by the implantation of As ions. An amorphous region 31 which is an amorphous region by As ion implantation is represented by a broken line in the drawing. Since As is an element having a relatively small mass, the amorphous region 31 is not formed in a deep region of the silicon substrate 10 but is formed only in a region near the surface of the silicon substrate 10.
[0057]
Next, as shown in FIG. 4B, In ions are introduced by ion implantation using the gate electrode 20b having the side wall spacers 22b formed on the side surfaces and the photoresist film 38 as a mask. The reason why In ions are introduced is to form the pocket region 32 and to make the region including the extension region 30a amorphous. Since In is an element having a larger mass than B or the like, the region including the extension region 30a can be made amorphous. The ion implantation conditions are set as follows, for example. The acceleration voltage is, for example, 30 to 120 keV. The angle at which In ions are implanted is, for example, 15 to 30 degrees with respect to the normal of the surface of the silicon substrate 10. The dose amount is, for example, 4 × 10 ¹³ ~ 8x10 ¹³ cm ^-2 And The dose per direction is 1 × 10 ¹³ ~ 2x10 ¹³ cm ^-2 And Thus, the p-type pocket region 32 is formed, and the amorphous region 33 is formed so as to include the extension region 30a.
[0058]
In general, the dose of In introduced to form the pocket region is 2 × 10 ¹³ cm ^-2 However, in this embodiment, not only the pocket region 32 but also the amorphous region 33 needs to be formed so as to include the extension region 30a. ¹³ ~ 8x10 ¹³ cm ^-2 And set high. In this embodiment, since the dose amount of In is high, the pocket region 32 is formed deep and wide.
[0059]
The In dose is 4 × 10. ¹³ ~ 8x10 ¹³ cm ^-2 However, the dose amount may be set higher. That is, the In dose may be set as appropriate so that the amorphous region 33 including the extension region 30a can be formed.
[0060]
Next, as shown in FIG. 5A, a SiN film having a thickness of 40 to 120 nm is formed on the entire surface by, eg, CVD. Thereafter, the SiN film is anisotropically etched. Thus, sidewall spacers 28a and 28b made of SiN are further formed on the side surfaces of the gate electrodes 20a and 20b on which the side wall spacers 22a and 22b are formed on the side surfaces. The thickness of the sidewall spacers 28a and 28b is set to, for example, about 30 to 100 nm.
[0061]
Next, as shown in FIG. 5B, a photoresist film 42 is formed on the entire surface by, eg, spin coating. Thereafter, the photoresist film 42 is patterned by using a photolithography technique. Thus, an opening 44 is formed in the photoresist film 42 to expose a region where the PMOS transistor is to be formed.
[0062]
Next, B ions are implanted by ion implantation using the gate electrode 20a having the sidewall spacers 28b formed on the side surfaces and the photoresist film 42 as a mask. The ion implantation conditions are, for example, 2 to 4 keV, and the dose amount is 4 × 10. ¹⁵ ~ 1x10 ¹⁶ cm ^-2 And Thus, the p-type extension region 24b constituting the deep region of the extension source / drain is formed. The extension region 24a and the impurity diffusion region 24b form a source / drain region 24 having an extension source / drain structure.
[0063]
Next, a photoresist film 46 is formed on the entire surface by, eg, spin coating. Thereafter, the photoresist film 46 is patterned by using a photolithography technique. Thus, an opening 48 is formed in the photoresist film 46 to expose the region where the NMOS transistor 16b is to be formed.
[0064]
Next, P ions are implanted by ion implantation using the gate electrode 20a having the sidewall spacers 22a and 28a formed on the side surfaces and the photoresist film 46 as a mask. The ion implantation conditions are, for example, an acceleration voltage of 3 to 8 keV and a dose amount of 4 × 10 4. ¹⁵ ~ 1x10 ¹⁶ cm ^-2 And Thus, the n-type extension region 30b constituting the deep region of the extension source / drain is formed. The extension region 30a and the impurity diffusion region 30b form a source / drain region 30 having an extension source / drain structure.
[0065]
Next, heat treatment for activating dopant impurities is performed by RTA (Rapid Thermal Annealing). The heat treatment temperature is, for example, 950 to 1100 ° C. The heat treatment time is, for example, 0.1 to 10 seconds.
[0066]
In the region where the PMOS transistor 16a is formed, since the extension region 24a is not particularly amorphous, B in the extension region 24a diffuses at a normal speed without being diffused at the time of heat treatment. On the other hand, since the amorphous region 33 is formed so as to include the extension region 30a in the region where the NMOS transistor 16b is formed, As in the extension region 30a is diffused at a high speed. For this reason, As in the extension region 30a formed in the region where the NMOS transistor 16b is formed is diffused at substantially the same speed as B in the extension region 24a formed in the region where the PMOS transistor 16a is formed. Therefore, the length of the portion where the extension region 30a and the gate electrode 20b overlap each other is substantially equal to the length of the portion where the extension region 24a and the gate electrode 20a overlap each other.
[0067]
Thus, the semiconductor device according to the present embodiment is manufactured.
[0068]
Thus, according to the present embodiment, since In is introduced at a high dose on both sides of the gate electrode 20b, the amorphous region 33 can be formed so as to include the extension region 30a. Therefore, according to the present embodiment, As in the extension region 30a can be diffused at a high speed in the region where the NMOS transistor 16a is formed. On the other hand, in the region where the PMOS transistor is formed, since the extension region 24a is not amorphous, B does not diffuse at a high speed. Therefore, according to the present embodiment, the length of the portion where the extension region 30a and the gate electrode 20b overlap is substantially equal to the length of the portion where the extension region 24a and the gate electrode 20a overlap. can do. For this reason, according to the present embodiment, it is possible to obtain desired electrical characteristics in both the NMOS transistor and the PMOS transistor even when the gate length is shortened. Therefore, according to the present embodiment, it is possible to provide a semiconductor device having a CMOS structure capable of realizing good electrical characteristics even when the gate length is shortened.
[0069]
(Evaluation results)
Next, the evaluation results of the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0070]
FIG. 7 is a graph showing the relationship between the gate length and the off current. Horizontal axis is gate length L _sem The vertical axis represents the off current I _off Is shown.
[0071]
FIG. 8 is a graph showing the relationship between on-current and off-current. The horizontal axis is the on-current I _on The vertical axis represents the off current I _off Is shown.
[0072]
In the figure, in the semiconductor device according to the present embodiment, specifically, in the semiconductor device according to the present embodiment, a side wall spacer is formed on the side surface of the gate electrode, and the dose amount of In when the pocket region is formed is 2 × 10. ¹⁴ cm ^-2 It shows the case where it is set high.
[0073]
In the drawing, □ indicates the dose amount of In when the side wall spacer is formed on the side surface of the gate electrode and the pocket region is formed. ¹³ cm ^-2 It shows the case where it is set low.
[0074]
In the figure, ■ indicates the dose amount of In when the pocket region is formed without forming the side wall spacer on the side surface of the gate electrode. ¹³ cm ^-2 It shows the case where it is set low.
[0075]
In either case, the drain voltage V _d Was set to 1V and measurement was performed.
[0076]
As shown in FIG. _off For example, the gate length L is 30 nA / μm. _sem Is shorter for □ than for ■ and shorter for ● than for □. From this, it can be seen that in the case of ●, that is, in the case of this embodiment, the off-current can be suppressed even when the gate electrode is shortened.
[0077]
Further, as shown in FIG. _off For example, when ON is 30 nA / μm, the ON current is larger in the cases of ● and ■ than in the case of □. From this, it can be seen that in the case of ●, that is, in the case of the present embodiment, the off-current can be kept small and the on-current can be secured large.
[0078]
(Modification)
Next, a modification of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 9 is a cross-sectional view showing a semiconductor device according to this modification.
[0079]
The semiconductor device according to this modification is mainly characterized in that the sidewall spacer 50 is formed so as to protrude from the side surfaces of the gate electrodes 20a and 20b.
[0080]
As shown in FIG. 9, side wall spacers 50a and 50b are formed on the side surfaces of the gate electrodes 20a and 20b so as to protrude from the side surfaces of the gate electrodes 20a and 20b, respectively. The side wall spacers 50a and 50b have a structure in which a silicon oxide film 52 and a silicon nitride film 54 are stacked.
[0081]
The gate electrode 20a in which the sidewall spacers 50a and 50b having such shapes are formed is referred to as a notch-type gate electrode.
[0082]
Thus, the side wall spacers 50a and 50b may be formed so as to protrude from the side surfaces of the gate electrodes 20a and 20b.
[0083]
Next, a method for manufacturing a semiconductor device according to this modification will be described with reference to FIGS. 10 and 11 are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to this modification.
[0084]
First, the steps up to forming the gate electrodes 20a and 20b are the same as the method for manufacturing the semiconductor device described above with reference to FIG.
[0085]
Next, as shown in FIG. 10A, an 8 nm-thickness silicon oxide film 52 is formed on the entire surface by, eg, CVD.
[0086]
Next, a 6 nm-thickness silicon nitride film 54 is formed on the entire surface by, eg, CVD.
[0087]
Next, as shown in FIG. 10B, the silicon nitride film 54 is anisotropically etched at a high selectivity with respect to the silicon oxide film 52.
[0088]
Next, as shown in FIG. 11A, the silicon oxide film 52 is wet-etched with a high selection ratio with respect to the silicon nitride film. Thus, sidewall spacers 50a and 50b formed by laminating the silicon oxide film 52 and the silicon nitride film 54 are formed.
[0089]
The subsequent method for manufacturing the semiconductor device is the same as the method for manufacturing the semiconductor device described above with reference to FIGS. 3A to 6B, and thus the description thereof is omitted (see FIG. 11B).
[0090]
Thus, the semiconductor device according to the present embodiment is manufactured.
[0091]
[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications can be made.
[0092]
For example, in the above embodiment, the amorphous region 33 is formed so as to include all of the extension regions 30 a, but it is not always necessary to include all of the extension regions 30 a by the amorphous region 33. This is because if the amorphous region 33 is formed at least in the region immediately below the gate electrode 20b, As can be diffused at a higher speed in the region immediately below the gate electrode 20b. If As can be accelerated and diffused at least in the region immediately below the gate electrode 20b, the length of the overlapping portion of the extension region 30a and the gate electrode 20b in the NMOS transistor 16b and the impurity diffusion region in the PMOS transistor 16a The length of the portion where 24a and the gate electrode 20a overlap can be made substantially equal.
[0093]
In the above embodiment, the case where SiN is used as the material of the sidewall spacers 22a and 22b has been described as an example. However, the material of the sidewall spacers 22a and 22b is not limited to SiN. For example, the material of the sidewall spacers 22a and 22b is SiO. ₂ Etc. may be used.
[0094]
Moreover, although the case where the side wall spacers 22a and 22b have a single layer structure has been described as an example in the above embodiment, the side wall spacers 22a and 22b having a laminated structure may be formed. For example, SiO ₂ Sidewall spacers 22a and 22b having a laminated structure in which a film and a SiN film are laminated may be formed.
[0095]
In the above-described embodiment, the case where As is introduced as the dopant impurity into the extension region 30a has been described as an example. However, the dopant impurity introduced into the extension region 30a is not limited to As. Sb or the like may be used. Even when P, Sb, or the like is introduced as a dopant impurity into the extension region 30a, the dopant impurity can be diffused at a higher rate during the heat treatment as in the case where As is introduced as the dopant impurity into the extension region 30a. .
[0096]
【The invention's effect】
As described above, according to the present invention, in a region where an NMOS transistor is formed, In is introduced at a high dose on both sides of the gate electrode, so that an amorphous region can be formed so as to include the extension region. . Therefore, according to the present invention, the As in the extension region can be diffused at a high speed in the region where the NMOS transistor is formed during the heat treatment. On the other hand, in the region where the PMOS transistor is formed, since the extension region is not amorphized, B does not diffuse at the time of heat treatment. Therefore, according to the present invention, the length of the portion where the extension region and the gate electrode overlap in the NMOS transistor is approximately equal to the length of the portion where the extension region and the gate electrode overlap in the PMOS transistor. Can be equal. For this reason, according to the present invention, it is possible to obtain desired electrical characteristics in both the NMOS transistor and the PMOS transistor even when the gate length is shortened. Therefore, according to the present invention, it is possible to provide a semiconductor device having a CMOS structure capable of realizing good electrical characteristics even when the gate length is shortened.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a process cross-sectional view (part 1) illustrating the method for manufacturing a semiconductor device according to the embodiment of the present invention;
FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 4 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 5 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 6 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 7 is a graph showing the relationship between gate length and off current.
FIG. 8 is a graph showing the relationship between on-current and off-current.
FIG. 9 is a cross-sectional view showing a semiconductor device according to a modification of one embodiment of the present invention.
FIG. 10 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 11 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;
FIG. 12 is a schematic view showing a proposed semiconductor device.
FIG. 13 is a graph showing the relationship between the length of the portion where the gate electrode and the extension region overlap and the saturation current.
[Explanation of symbols]
10 ... Silicon substrate
12 ... n-type well
14a, 14b ... element region
15: Element isolation region
16a ... PMOS transistor
16b ... NMOS transistor
18 ... Gate insulating film
20a, 20b ... gate electrodes
22a, 22b ... sidewall spacer
24 ... Source / drain diffusion layer
24a ... Extension area
24b ... impurity diffusion region
25: Amorphous region
26 ... Pocket area
28a, 28b ... sidewall spacers
30 ... Source / drain diffusion layer
30a ... Extension area
30b ... impurity diffusion region
31 ... Amorphous region
32 ... Pocket area
33 ... Amorphous region
34 ... Photoresist film
36 ... opening
38 ... Photoresist film
40 ... opening
42. Photoresist film
44 ... opening
46. Photoresist film
48 ... Opening
50a, 50b ... sidewall spacer
52. Silicon oxide film
54 ... Silicon nitride film
116a ... PMOS transistor
116b ... NMOS transistor
120 ... Gate electrode
122 .. Side wall spacer
126a ... PMOS transistor
126b ... NMOS transistor

Claims (2)

In a method for manufacturing a semiconductor device in which a PMOS transistor and an NMOS transistor are formed on a semiconductor substrate,
Forming a gate electrode via an insulating film on the semiconductor substrate,
Forming a sidewall spacer on a side surface of the gate electrode;
In the semiconductor substrate on both sides of the gate electrode of the PMOS transistor, a first extension region in which B is introduced as a dopant impurity using the gate electrode on which the sidewall spacer is formed as a mask, and As as a dopant impurity Forming a first pocket region having introduced therein;
Forming a second extension region in which As is introduced as a dopant impurity in the semiconductor substrate on both sides of the gate electrode of the NMOS transistor, using the gate electrode on which the sidewall spacer is formed as a mask ;
After the step of forming the second extension region, forming a second pocket region including an amorphous region by introducing In as a dopant impurity so as to include the second extension region ;
By forming a first impurity diffusion region deeper than the first extension region in the semiconductor substrate on both sides of the gate electrode of the PMOS transistor, the first extension region, the first impurity diffusion region, and Forming a first source / drain region of the PMOS transistor having a second impurity diffusion region deeper than the second extension region in the semiconductor substrate on both sides of the gate electrode of the NMOS transistor. Forming a second source / drain region of the NMOS transistor having the second extension region and the second impurity diffusion region;
Manufacturing a semiconductor device characterized by having said after the first source / drain region and the second source / drain regions and forming a row cormorants Engineering degree to a heat treatment to activate the dopant impurities Method. In the manufacturing method of the semiconductor device according to claim 1 ,
In the method for forming the second pocket region , In is introduced so that the dose amount is 4 × 10 ¹³ cm ⁻² or more.

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